1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /*
3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
4 */
5
6 #ifndef MLX5_IB_H
7 #define MLX5_IB_H
8
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <rdma/ib_verbs.h>
12 #include <rdma/ib_umem.h>
13 #include <rdma/ib_smi.h>
14 #include <linux/mlx5/driver.h>
15 #include <linux/mlx5/cq.h>
16 #include <linux/mlx5/fs.h>
17 #include <linux/mlx5/qp.h>
18 #include <linux/types.h>
19 #include <linux/mlx5/transobj.h>
20 #include <rdma/ib_user_verbs.h>
21 #include <rdma/mlx5-abi.h>
22 #include <rdma/uverbs_ioctl.h>
23 #include <rdma/mlx5_user_ioctl_cmds.h>
24 #include <rdma/mlx5_user_ioctl_verbs.h>
25
26 #include "srq.h"
27
28 #define mlx5_ib_dbg(_dev, format, arg...) \
29 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
30 __LINE__, current->pid, ##arg)
31
32 #define mlx5_ib_err(_dev, format, arg...) \
33 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
34 __LINE__, current->pid, ##arg)
35
36 #define mlx5_ib_warn(_dev, format, arg...) \
37 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
38 __LINE__, current->pid, ##arg)
39
40 #define MLX5_IB_DEFAULT_UIDX 0xffffff
41 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
42
43 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size)
44
45 enum {
46 MLX5_IB_MMAP_OFFSET_START = 9,
47 MLX5_IB_MMAP_OFFSET_END = 255,
48 };
49
50 enum {
51 MLX5_IB_MMAP_CMD_SHIFT = 8,
52 MLX5_IB_MMAP_CMD_MASK = 0xff,
53 };
54
55 enum {
56 MLX5_RES_SCAT_DATA32_CQE = 0x1,
57 MLX5_RES_SCAT_DATA64_CQE = 0x2,
58 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
59 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
60 };
61
62 enum mlx5_ib_mad_ifc_flags {
63 MLX5_MAD_IFC_IGNORE_MKEY = 1,
64 MLX5_MAD_IFC_IGNORE_BKEY = 2,
65 MLX5_MAD_IFC_NET_VIEW = 4,
66 };
67
68 enum {
69 MLX5_CROSS_CHANNEL_BFREG = 0,
70 };
71
72 enum {
73 MLX5_CQE_VERSION_V0,
74 MLX5_CQE_VERSION_V1,
75 };
76
77 enum {
78 MLX5_TM_MAX_RNDV_MSG_SIZE = 64,
79 MLX5_TM_MAX_SGE = 1,
80 };
81
82 enum {
83 MLX5_IB_INVALID_UAR_INDEX = BIT(31),
84 MLX5_IB_INVALID_BFREG = BIT(31),
85 };
86
87 enum {
88 MLX5_MAX_MEMIC_PAGES = 0x100,
89 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f,
90 };
91
92 enum {
93 MLX5_MEMIC_BASE_ALIGN = 6,
94 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN,
95 };
96
97 enum mlx5_ib_mmap_type {
98 MLX5_IB_MMAP_TYPE_MEMIC = 1,
99 MLX5_IB_MMAP_TYPE_VAR = 2,
100 MLX5_IB_MMAP_TYPE_UAR_WC = 3,
101 MLX5_IB_MMAP_TYPE_UAR_NC = 4,
102 };
103
104 struct mlx5_bfreg_info {
105 u32 *sys_pages;
106 int num_low_latency_bfregs;
107 unsigned int *count;
108
109 /*
110 * protect bfreg allocation data structs
111 */
112 struct mutex lock;
113 u32 ver;
114 u8 lib_uar_4k : 1;
115 u8 lib_uar_dyn : 1;
116 u32 num_sys_pages;
117 u32 num_static_sys_pages;
118 u32 total_num_bfregs;
119 u32 num_dyn_bfregs;
120 };
121
122 struct mlx5_ib_ucontext {
123 struct ib_ucontext ibucontext;
124 struct list_head db_page_list;
125
126 /* protect doorbell record alloc/free
127 */
128 struct mutex db_page_mutex;
129 struct mlx5_bfreg_info bfregi;
130 u8 cqe_version;
131 /* Transport Domain number */
132 u32 tdn;
133
134 u64 lib_caps;
135 u16 devx_uid;
136 /* For RoCE LAG TX affinity */
137 atomic_t tx_port_affinity;
138 };
139
to_mucontext(struct ib_ucontext * ibucontext)140 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
141 {
142 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
143 }
144
145 struct mlx5_ib_pd {
146 struct ib_pd ibpd;
147 u32 pdn;
148 u16 uid;
149 };
150
151 enum {
152 MLX5_IB_FLOW_ACTION_MODIFY_HEADER,
153 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT,
154 MLX5_IB_FLOW_ACTION_DECAP,
155 };
156
157 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
158 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
159 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
160 #error "Invalid number of bypass priorities"
161 #endif
162 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
163
164 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
165 #define MLX5_IB_NUM_SNIFFER_FTS 2
166 #define MLX5_IB_NUM_EGRESS_FTS 1
167 struct mlx5_ib_flow_prio {
168 struct mlx5_flow_table *flow_table;
169 unsigned int refcount;
170 };
171
172 struct mlx5_ib_flow_handler {
173 struct list_head list;
174 struct ib_flow ibflow;
175 struct mlx5_ib_flow_prio *prio;
176 struct mlx5_flow_handle *rule;
177 struct ib_counters *ibcounters;
178 struct mlx5_ib_dev *dev;
179 struct mlx5_ib_flow_matcher *flow_matcher;
180 };
181
182 struct mlx5_ib_flow_matcher {
183 struct mlx5_ib_match_params matcher_mask;
184 int mask_len;
185 enum mlx5_ib_flow_type flow_type;
186 enum mlx5_flow_namespace_type ns_type;
187 u16 priority;
188 struct mlx5_core_dev *mdev;
189 atomic_t usecnt;
190 u8 match_criteria_enable;
191 };
192
193 struct mlx5_ib_pp {
194 u16 index;
195 struct mlx5_core_dev *mdev;
196 };
197
198 struct mlx5_ib_flow_db {
199 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
200 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT];
201 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS];
202 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS];
203 struct mlx5_ib_flow_prio fdb;
204 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT];
205 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT];
206 struct mlx5_flow_table *lag_demux_ft;
207 /* Protect flow steering bypass flow tables
208 * when add/del flow rules.
209 * only single add/removal of flow steering rule could be done
210 * simultaneously.
211 */
212 struct mutex lock;
213 };
214
215 /* Use macros here so that don't have to duplicate
216 * enum ib_send_flags and enum ib_qp_type for low-level driver
217 */
218
219 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0)
220 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1)
221 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2)
222 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3)
223 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4)
224 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END
225
226 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
227 /*
228 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI
229 * creates the actual hardware QP.
230 */
231 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
232 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3
233 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4
234 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
235
236 #define MLX5_IB_UMR_OCTOWORD 16
237 #define MLX5_IB_UMR_XLT_ALIGNMENT 64
238
239 #define MLX5_IB_UPD_XLT_ZAP BIT(0)
240 #define MLX5_IB_UPD_XLT_ENABLE BIT(1)
241 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2)
242 #define MLX5_IB_UPD_XLT_ADDR BIT(3)
243 #define MLX5_IB_UPD_XLT_PD BIT(4)
244 #define MLX5_IB_UPD_XLT_ACCESS BIT(5)
245 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6)
246
247 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags.
248 *
249 * These flags are intended for internal use by the mlx5_ib driver, and they
250 * rely on the range reserved for that use in the ib_qp_create_flags enum.
251 */
252 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START
253 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1)
254
255 struct wr_list {
256 u16 opcode;
257 u16 next;
258 };
259
260 enum mlx5_ib_rq_flags {
261 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0,
262 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1,
263 };
264
265 struct mlx5_ib_wq {
266 struct mlx5_frag_buf_ctrl fbc;
267 u64 *wrid;
268 u32 *wr_data;
269 struct wr_list *w_list;
270 unsigned *wqe_head;
271 u16 unsig_count;
272
273 /* serialize post to the work queue
274 */
275 spinlock_t lock;
276 int wqe_cnt;
277 int max_post;
278 int max_gs;
279 int offset;
280 int wqe_shift;
281 unsigned head;
282 unsigned tail;
283 u16 cur_post;
284 u16 last_poll;
285 void *cur_edge;
286 };
287
288 enum mlx5_ib_wq_flags {
289 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1,
290 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2,
291 };
292
293 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
294 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16
295 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
296 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13
297 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3
298
299 struct mlx5_ib_rwq {
300 struct ib_wq ibwq;
301 struct mlx5_core_qp core_qp;
302 u32 rq_num_pas;
303 u32 log_rq_stride;
304 u32 log_rq_size;
305 u32 rq_page_offset;
306 u32 log_page_size;
307 u32 log_num_strides;
308 u32 two_byte_shift_en;
309 u32 single_stride_log_num_of_bytes;
310 struct ib_umem *umem;
311 size_t buf_size;
312 unsigned int page_shift;
313 struct mlx5_db db;
314 u32 user_index;
315 u32 wqe_count;
316 u32 wqe_shift;
317 int wq_sig;
318 u32 create_flags; /* Use enum mlx5_ib_wq_flags */
319 };
320
321 struct mlx5_ib_rwq_ind_table {
322 struct ib_rwq_ind_table ib_rwq_ind_tbl;
323 u32 rqtn;
324 u16 uid;
325 };
326
327 struct mlx5_ib_ubuffer {
328 struct ib_umem *umem;
329 int buf_size;
330 u64 buf_addr;
331 };
332
333 struct mlx5_ib_qp_base {
334 struct mlx5_ib_qp *container_mibqp;
335 struct mlx5_core_qp mqp;
336 struct mlx5_ib_ubuffer ubuffer;
337 };
338
339 struct mlx5_ib_qp_trans {
340 struct mlx5_ib_qp_base base;
341 u16 xrcdn;
342 u8 alt_port;
343 u8 atomic_rd_en;
344 u8 resp_depth;
345 };
346
347 struct mlx5_ib_rss_qp {
348 u32 tirn;
349 };
350
351 struct mlx5_ib_rq {
352 struct mlx5_ib_qp_base base;
353 struct mlx5_ib_wq *rq;
354 struct mlx5_ib_ubuffer ubuffer;
355 struct mlx5_db *doorbell;
356 u32 tirn;
357 u8 state;
358 u32 flags;
359 };
360
361 struct mlx5_ib_sq {
362 struct mlx5_ib_qp_base base;
363 struct mlx5_ib_wq *sq;
364 struct mlx5_ib_ubuffer ubuffer;
365 struct mlx5_db *doorbell;
366 struct mlx5_flow_handle *flow_rule;
367 u32 tisn;
368 u8 state;
369 };
370
371 struct mlx5_ib_raw_packet_qp {
372 struct mlx5_ib_sq sq;
373 struct mlx5_ib_rq rq;
374 };
375
376 struct mlx5_bf {
377 int buf_size;
378 unsigned long offset;
379 struct mlx5_sq_bfreg *bfreg;
380 };
381
382 struct mlx5_ib_dct {
383 struct mlx5_core_dct mdct;
384 u32 *in;
385 };
386
387 struct mlx5_ib_gsi_qp {
388 struct ib_qp *rx_qp;
389 u8 port_num;
390 struct ib_qp_cap cap;
391 struct ib_cq *cq;
392 struct mlx5_ib_gsi_wr *outstanding_wrs;
393 u32 outstanding_pi, outstanding_ci;
394 int num_qps;
395 /* Protects access to the tx_qps. Post send operations synchronize
396 * with tx_qp creation in setup_qp(). Also protects the
397 * outstanding_wrs array and indices.
398 */
399 spinlock_t lock;
400 struct ib_qp **tx_qps;
401 };
402
403 struct mlx5_ib_qp {
404 struct ib_qp ibqp;
405 union {
406 struct mlx5_ib_qp_trans trans_qp;
407 struct mlx5_ib_raw_packet_qp raw_packet_qp;
408 struct mlx5_ib_rss_qp rss_qp;
409 struct mlx5_ib_dct dct;
410 struct mlx5_ib_gsi_qp gsi;
411 };
412 struct mlx5_frag_buf buf;
413
414 struct mlx5_db db;
415 struct mlx5_ib_wq rq;
416
417 u8 sq_signal_bits;
418 u8 next_fence;
419 struct mlx5_ib_wq sq;
420
421 /* serialize qp state modifications
422 */
423 struct mutex mutex;
424 /* cached variant of create_flags from struct ib_qp_init_attr */
425 u32 flags;
426 u8 port;
427 u8 state;
428 int max_inline_data;
429 struct mlx5_bf bf;
430 u8 has_rq:1;
431 u8 is_rss:1;
432
433 /* only for user space QPs. For kernel
434 * we have it from the bf object
435 */
436 int bfregn;
437
438 struct list_head qps_list;
439 struct list_head cq_recv_list;
440 struct list_head cq_send_list;
441 struct mlx5_rate_limit rl;
442 u32 underlay_qpn;
443 u32 flags_en;
444 /*
445 * IB/core doesn't store low-level QP types, so
446 * store both MLX and IBTA types in the field below.
447 * IB_QPT_DRIVER will be break to DCI/DCT subtypes.
448 */
449 enum ib_qp_type type;
450 /* A flag to indicate if there's a new counter is configured
451 * but not take effective
452 */
453 u32 counter_pending;
454 u16 gsi_lag_port;
455 };
456
457 struct mlx5_ib_cq_buf {
458 struct mlx5_frag_buf_ctrl fbc;
459 struct mlx5_frag_buf frag_buf;
460 struct ib_umem *umem;
461 int cqe_size;
462 int nent;
463 };
464
465 struct mlx5_umr_wr {
466 struct ib_send_wr wr;
467 u64 virt_addr;
468 u64 offset;
469 struct ib_pd *pd;
470 unsigned int page_shift;
471 unsigned int xlt_size;
472 u64 length;
473 int access_flags;
474 u32 mkey;
475 u8 ignore_free_state:1;
476 };
477
umr_wr(const struct ib_send_wr * wr)478 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr)
479 {
480 return container_of(wr, struct mlx5_umr_wr, wr);
481 }
482
483 struct mlx5_shared_mr_info {
484 int mr_id;
485 struct ib_umem *umem;
486 };
487
488 enum mlx5_ib_cq_pr_flags {
489 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0,
490 };
491
492 struct mlx5_ib_cq {
493 struct ib_cq ibcq;
494 struct mlx5_core_cq mcq;
495 struct mlx5_ib_cq_buf buf;
496 struct mlx5_db db;
497
498 /* serialize access to the CQ
499 */
500 spinlock_t lock;
501
502 /* protect resize cq
503 */
504 struct mutex resize_mutex;
505 struct mlx5_ib_cq_buf *resize_buf;
506 struct ib_umem *resize_umem;
507 int cqe_size;
508 struct list_head list_send_qp;
509 struct list_head list_recv_qp;
510 u32 create_flags;
511 struct list_head wc_list;
512 enum ib_cq_notify_flags notify_flags;
513 struct work_struct notify_work;
514 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */
515 };
516
517 struct mlx5_ib_wc {
518 struct ib_wc wc;
519 struct list_head list;
520 };
521
522 struct mlx5_ib_srq {
523 struct ib_srq ibsrq;
524 struct mlx5_core_srq msrq;
525 struct mlx5_frag_buf buf;
526 struct mlx5_db db;
527 struct mlx5_frag_buf_ctrl fbc;
528 u64 *wrid;
529 /* protect SRQ hanlding
530 */
531 spinlock_t lock;
532 int head;
533 int tail;
534 u16 wqe_ctr;
535 struct ib_umem *umem;
536 /* serialize arming a SRQ
537 */
538 struct mutex mutex;
539 int wq_sig;
540 };
541
542 struct mlx5_ib_xrcd {
543 struct ib_xrcd ibxrcd;
544 u32 xrcdn;
545 };
546
547 enum mlx5_ib_mtt_access_flags {
548 MLX5_IB_MTT_READ = (1 << 0),
549 MLX5_IB_MTT_WRITE = (1 << 1),
550 };
551
552 struct mlx5_user_mmap_entry {
553 struct rdma_user_mmap_entry rdma_entry;
554 u8 mmap_flag;
555 u64 address;
556 u32 page_idx;
557 };
558
559 struct mlx5_ib_dm {
560 struct ib_dm ibdm;
561 phys_addr_t dev_addr;
562 u32 type;
563 size_t size;
564 union {
565 struct {
566 u32 obj_id;
567 } icm_dm;
568 /* other dm types specific params should be added here */
569 };
570 struct mlx5_user_mmap_entry mentry;
571 };
572
573 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
574
575 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
576 IB_ACCESS_REMOTE_WRITE |\
577 IB_ACCESS_REMOTE_READ |\
578 IB_ACCESS_REMOTE_ATOMIC |\
579 IB_ZERO_BASED)
580
581 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
582 IB_ACCESS_REMOTE_WRITE |\
583 IB_ACCESS_REMOTE_READ |\
584 IB_ZERO_BASED)
585
586 #define mlx5_update_odp_stats(mr, counter_name, value) \
587 atomic64_add(value, &((mr)->odp_stats.counter_name))
588
589 struct mlx5_ib_mr {
590 struct ib_mr ibmr;
591 void *descs;
592 dma_addr_t desc_map;
593 int ndescs;
594 int data_length;
595 int meta_ndescs;
596 int meta_length;
597 int max_descs;
598 int desc_size;
599 int access_mode;
600 struct mlx5_core_mkey mmkey;
601 struct ib_umem *umem;
602 struct mlx5_shared_mr_info *smr_info;
603 struct list_head list;
604 unsigned int order;
605 struct mlx5_cache_ent *cache_ent;
606 int npages;
607 struct mlx5_ib_dev *dev;
608 u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
609 struct mlx5_core_sig_ctx *sig;
610 void *descs_alloc;
611 int access_flags; /* Needed for rereg MR */
612
613 struct mlx5_ib_mr *parent;
614 /* Needed for IB_MR_TYPE_INTEGRITY */
615 struct mlx5_ib_mr *pi_mr;
616 struct mlx5_ib_mr *klm_mr;
617 struct mlx5_ib_mr *mtt_mr;
618 u64 data_iova;
619 u64 pi_iova;
620
621 /* For ODP and implicit */
622 atomic_t num_deferred_work;
623 wait_queue_head_t q_deferred_work;
624 struct xarray implicit_children;
625 union {
626 struct rcu_head rcu;
627 struct list_head elm;
628 struct work_struct work;
629 } odp_destroy;
630 struct ib_odp_counters odp_stats;
631 bool is_odp_implicit;
632
633 struct mlx5_async_work cb_work;
634 };
635
is_odp_mr(struct mlx5_ib_mr * mr)636 static inline bool is_odp_mr(struct mlx5_ib_mr *mr)
637 {
638 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem &&
639 mr->umem->is_odp;
640 }
641
642 struct mlx5_ib_mw {
643 struct ib_mw ibmw;
644 struct mlx5_core_mkey mmkey;
645 int ndescs;
646 };
647
648 struct mlx5_ib_devx_mr {
649 struct mlx5_core_mkey mmkey;
650 int ndescs;
651 };
652
653 struct mlx5_ib_umr_context {
654 struct ib_cqe cqe;
655 enum ib_wc_status status;
656 struct completion done;
657 };
658
659 struct umr_common {
660 struct ib_pd *pd;
661 struct ib_cq *cq;
662 struct ib_qp *qp;
663 /* control access to UMR QP
664 */
665 struct semaphore sem;
666 };
667
668 struct mlx5_cache_ent {
669 struct list_head head;
670 /* sync access to the cahce entry
671 */
672 spinlock_t lock;
673
674
675 char name[4];
676 u32 order;
677 u32 xlt;
678 u32 access_mode;
679 u32 page;
680
681 u8 disabled:1;
682 u8 fill_to_high_water:1;
683
684 /*
685 * - available_mrs is the length of list head, ie the number of MRs
686 * available for immediate allocation.
687 * - total_mrs is available_mrs plus all in use MRs that could be
688 * returned to the cache.
689 * - limit is the low water mark for available_mrs, 2* limit is the
690 * upper water mark.
691 * - pending is the number of MRs currently being created
692 */
693 u32 total_mrs;
694 u32 available_mrs;
695 u32 limit;
696 u32 pending;
697
698 /* Statistics */
699 u32 miss;
700
701 struct mlx5_ib_dev *dev;
702 struct work_struct work;
703 struct delayed_work dwork;
704 };
705
706 struct mlx5_mr_cache {
707 struct workqueue_struct *wq;
708 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES];
709 struct dentry *root;
710 unsigned long last_add;
711 };
712
713 struct mlx5_ib_port_resources {
714 struct mlx5_ib_gsi_qp *gsi;
715 struct work_struct pkey_change_work;
716 };
717
718 struct mlx5_ib_resources {
719 struct ib_cq *c0;
720 u32 xrcdn0;
721 u32 xrcdn1;
722 struct ib_pd *p0;
723 struct ib_srq *s0;
724 struct ib_srq *s1;
725 struct mlx5_ib_port_resources ports[2];
726 /* Protects changes to the port resources */
727 struct mutex mutex;
728 };
729
730 struct mlx5_ib_counters {
731 const char **names;
732 size_t *offsets;
733 u32 num_q_counters;
734 u32 num_cong_counters;
735 u32 num_ext_ppcnt_counters;
736 u16 set_id;
737 };
738
739 struct mlx5_ib_multiport_info;
740
741 struct mlx5_ib_multiport {
742 struct mlx5_ib_multiport_info *mpi;
743 /* To be held when accessing the multiport info */
744 spinlock_t mpi_lock;
745 };
746
747 struct mlx5_roce {
748 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
749 * netdev pointer
750 */
751 rwlock_t netdev_lock;
752 struct net_device *netdev;
753 struct notifier_block nb;
754 atomic_t tx_port_affinity;
755 enum ib_port_state last_port_state;
756 struct mlx5_ib_dev *dev;
757 u8 native_port_num;
758 };
759
760 struct mlx5_ib_port {
761 struct mlx5_ib_counters cnts;
762 struct mlx5_ib_multiport mp;
763 struct mlx5_ib_dbg_cc_params *dbg_cc_params;
764 struct mlx5_roce roce;
765 struct mlx5_eswitch_rep *rep;
766 };
767
768 struct mlx5_ib_dbg_param {
769 int offset;
770 struct mlx5_ib_dev *dev;
771 struct dentry *dentry;
772 u8 port_num;
773 };
774
775 enum mlx5_ib_dbg_cc_types {
776 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE,
777 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI,
778 MLX5_IB_DBG_CC_RP_TIME_RESET,
779 MLX5_IB_DBG_CC_RP_BYTE_RESET,
780 MLX5_IB_DBG_CC_RP_THRESHOLD,
781 MLX5_IB_DBG_CC_RP_AI_RATE,
782 MLX5_IB_DBG_CC_RP_MAX_RATE,
783 MLX5_IB_DBG_CC_RP_HAI_RATE,
784 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC,
785 MLX5_IB_DBG_CC_RP_MIN_RATE,
786 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP,
787 MLX5_IB_DBG_CC_RP_DCE_TCP_G,
788 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT,
789 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD,
790 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE,
791 MLX5_IB_DBG_CC_RP_GD,
792 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS,
793 MLX5_IB_DBG_CC_NP_CNP_DSCP,
794 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE,
795 MLX5_IB_DBG_CC_NP_CNP_PRIO,
796 MLX5_IB_DBG_CC_MAX,
797 };
798
799 struct mlx5_ib_dbg_cc_params {
800 struct dentry *root;
801 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX];
802 };
803
804 enum {
805 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100,
806 };
807
808 struct mlx5_ib_delay_drop {
809 struct mlx5_ib_dev *dev;
810 struct work_struct delay_drop_work;
811 /* serialize setting of delay drop */
812 struct mutex lock;
813 u32 timeout;
814 bool activate;
815 atomic_t events_cnt;
816 atomic_t rqs_cnt;
817 struct dentry *dir_debugfs;
818 };
819
820 enum mlx5_ib_stages {
821 MLX5_IB_STAGE_INIT,
822 MLX5_IB_STAGE_FS,
823 MLX5_IB_STAGE_CAPS,
824 MLX5_IB_STAGE_NON_DEFAULT_CB,
825 MLX5_IB_STAGE_ROCE,
826 MLX5_IB_STAGE_QP,
827 MLX5_IB_STAGE_SRQ,
828 MLX5_IB_STAGE_DEVICE_RESOURCES,
829 MLX5_IB_STAGE_DEVICE_NOTIFIER,
830 MLX5_IB_STAGE_ODP,
831 MLX5_IB_STAGE_COUNTERS,
832 MLX5_IB_STAGE_CONG_DEBUGFS,
833 MLX5_IB_STAGE_UAR,
834 MLX5_IB_STAGE_BFREG,
835 MLX5_IB_STAGE_PRE_IB_REG_UMR,
836 MLX5_IB_STAGE_WHITELIST_UID,
837 MLX5_IB_STAGE_IB_REG,
838 MLX5_IB_STAGE_POST_IB_REG_UMR,
839 MLX5_IB_STAGE_DELAY_DROP,
840 MLX5_IB_STAGE_RESTRACK,
841 MLX5_IB_STAGE_MAX,
842 };
843
844 struct mlx5_ib_stage {
845 int (*init)(struct mlx5_ib_dev *dev);
846 void (*cleanup)(struct mlx5_ib_dev *dev);
847 };
848
849 #define STAGE_CREATE(_stage, _init, _cleanup) \
850 .stage[_stage] = {.init = _init, .cleanup = _cleanup}
851
852 struct mlx5_ib_profile {
853 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX];
854 };
855
856 struct mlx5_ib_multiport_info {
857 struct list_head list;
858 struct mlx5_ib_dev *ibdev;
859 struct mlx5_core_dev *mdev;
860 struct notifier_block mdev_events;
861 struct completion unref_comp;
862 u64 sys_image_guid;
863 u32 mdev_refcnt;
864 bool is_master;
865 bool unaffiliate;
866 };
867
868 struct mlx5_ib_flow_action {
869 struct ib_flow_action ib_action;
870 union {
871 struct {
872 u64 ib_flags;
873 struct mlx5_accel_esp_xfrm *ctx;
874 } esp_aes_gcm;
875 struct {
876 struct mlx5_ib_dev *dev;
877 u32 sub_type;
878 union {
879 struct mlx5_modify_hdr *modify_hdr;
880 struct mlx5_pkt_reformat *pkt_reformat;
881 };
882 } flow_action_raw;
883 };
884 };
885
886 struct mlx5_dm {
887 struct mlx5_core_dev *dev;
888 /* This lock is used to protect the access to the shared
889 * allocation map when concurrent requests by different
890 * processes are handled.
891 */
892 spinlock_t lock;
893 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES);
894 };
895
896 struct mlx5_read_counters_attr {
897 struct mlx5_fc *hw_cntrs_hndl;
898 u64 *out;
899 u32 flags;
900 };
901
902 enum mlx5_ib_counters_type {
903 MLX5_IB_COUNTERS_FLOW,
904 };
905
906 struct mlx5_ib_mcounters {
907 struct ib_counters ibcntrs;
908 enum mlx5_ib_counters_type type;
909 /* number of counters supported for this counters type */
910 u32 counters_num;
911 struct mlx5_fc *hw_cntrs_hndl;
912 /* read function for this counters type */
913 int (*read_counters)(struct ib_device *ibdev,
914 struct mlx5_read_counters_attr *read_attr);
915 /* max index set as part of create_flow */
916 u32 cntrs_max_index;
917 /* number of counters data entries (<description,index> pair) */
918 u32 ncounters;
919 /* counters data array for descriptions and indexes */
920 struct mlx5_ib_flow_counters_desc *counters_data;
921 /* protects access to mcounters internal data */
922 struct mutex mcntrs_mutex;
923 };
924
925 static inline struct mlx5_ib_mcounters *
to_mcounters(struct ib_counters * ibcntrs)926 to_mcounters(struct ib_counters *ibcntrs)
927 {
928 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs);
929 }
930
931 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
932 bool is_egress,
933 struct mlx5_flow_act *action);
934 struct mlx5_ib_lb_state {
935 /* protect the user_td */
936 struct mutex mutex;
937 u32 user_td;
938 int qps;
939 bool enabled;
940 };
941
942 struct mlx5_ib_pf_eq {
943 struct notifier_block irq_nb;
944 struct mlx5_ib_dev *dev;
945 struct mlx5_eq *core;
946 struct work_struct work;
947 spinlock_t lock; /* Pagefaults spinlock */
948 struct workqueue_struct *wq;
949 mempool_t *pool;
950 };
951
952 struct mlx5_devx_event_table {
953 struct mlx5_nb devx_nb;
954 /* serialize updating the event_xa */
955 struct mutex event_xa_lock;
956 struct xarray event_xa;
957 };
958
959 struct mlx5_var_table {
960 /* serialize updating the bitmap */
961 struct mutex bitmap_lock;
962 unsigned long *bitmap;
963 u64 hw_start_addr;
964 u32 stride_size;
965 u64 num_var_hw_entries;
966 };
967
968 struct mlx5_ib_dev {
969 struct ib_device ib_dev;
970 struct mlx5_core_dev *mdev;
971 struct notifier_block mdev_events;
972 int num_ports;
973 /* serialize update of capability mask
974 */
975 struct mutex cap_mask_mutex;
976 u8 ib_active:1;
977 u8 is_rep:1;
978 u8 lag_active:1;
979 u8 wc_support:1;
980 u8 fill_delay;
981 struct umr_common umrc;
982 /* sync used page count stats
983 */
984 struct mlx5_ib_resources devr;
985
986 atomic_t mkey_var;
987 struct mlx5_mr_cache cache;
988 struct timer_list delay_timer;
989 /* Prevents soft lock on massive reg MRs */
990 struct mutex slow_path_mutex;
991 struct ib_odp_caps odp_caps;
992 u64 odp_max_size;
993 struct mlx5_ib_pf_eq odp_pf_eq;
994
995 /*
996 * Sleepable RCU that prevents destruction of MRs while they are still
997 * being used by a page fault handler.
998 */
999 struct srcu_struct odp_srcu;
1000 struct xarray odp_mkeys;
1001
1002 u32 null_mkey;
1003 struct mlx5_ib_flow_db *flow_db;
1004 /* protect resources needed as part of reset flow */
1005 spinlock_t reset_flow_resource_lock;
1006 struct list_head qp_list;
1007 /* Array with num_ports elements */
1008 struct mlx5_ib_port *port;
1009 struct mlx5_sq_bfreg bfreg;
1010 struct mlx5_sq_bfreg wc_bfreg;
1011 struct mlx5_sq_bfreg fp_bfreg;
1012 struct mlx5_ib_delay_drop delay_drop;
1013 const struct mlx5_ib_profile *profile;
1014
1015 struct mlx5_ib_lb_state lb;
1016 u8 umr_fence;
1017 struct list_head ib_dev_list;
1018 u64 sys_image_guid;
1019 struct mlx5_dm dm;
1020 u16 devx_whitelist_uid;
1021 struct mlx5_srq_table srq_table;
1022 struct mlx5_qp_table qp_table;
1023 struct mlx5_async_ctx async_ctx;
1024 struct mlx5_devx_event_table devx_event_table;
1025 struct mlx5_var_table var_table;
1026
1027 struct xarray sig_mrs;
1028 };
1029
to_mibcq(struct mlx5_core_cq * mcq)1030 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
1031 {
1032 return container_of(mcq, struct mlx5_ib_cq, mcq);
1033 }
1034
to_mxrcd(struct ib_xrcd * ibxrcd)1035 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
1036 {
1037 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
1038 }
1039
to_mdev(struct ib_device * ibdev)1040 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
1041 {
1042 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
1043 }
1044
mlx5_udata_to_mdev(struct ib_udata * udata)1045 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata)
1046 {
1047 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1048 udata, struct mlx5_ib_ucontext, ibucontext);
1049
1050 return to_mdev(context->ibucontext.device);
1051 }
1052
to_mcq(struct ib_cq * ibcq)1053 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
1054 {
1055 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
1056 }
1057
to_mibqp(struct mlx5_core_qp * mqp)1058 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
1059 {
1060 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
1061 }
1062
to_mibrwq(struct mlx5_core_qp * core_qp)1063 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp)
1064 {
1065 return container_of(core_qp, struct mlx5_ib_rwq, core_qp);
1066 }
1067
to_mpd(struct ib_pd * ibpd)1068 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
1069 {
1070 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
1071 }
1072
to_msrq(struct ib_srq * ibsrq)1073 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
1074 {
1075 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
1076 }
1077
to_mqp(struct ib_qp * ibqp)1078 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
1079 {
1080 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
1081 }
1082
to_mrwq(struct ib_wq * ibwq)1083 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq)
1084 {
1085 return container_of(ibwq, struct mlx5_ib_rwq, ibwq);
1086 }
1087
to_mrwq_ind_table(struct ib_rwq_ind_table * ib_rwq_ind_tbl)1088 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
1089 {
1090 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl);
1091 }
1092
to_mibsrq(struct mlx5_core_srq * msrq)1093 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
1094 {
1095 return container_of(msrq, struct mlx5_ib_srq, msrq);
1096 }
1097
to_mdm(struct ib_dm * ibdm)1098 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm)
1099 {
1100 return container_of(ibdm, struct mlx5_ib_dm, ibdm);
1101 }
1102
to_mmr(struct ib_mr * ibmr)1103 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
1104 {
1105 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
1106 }
1107
to_mmw(struct ib_mw * ibmw)1108 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw)
1109 {
1110 return container_of(ibmw, struct mlx5_ib_mw, ibmw);
1111 }
1112
1113 static inline struct mlx5_ib_flow_action *
to_mflow_act(struct ib_flow_action * ibact)1114 to_mflow_act(struct ib_flow_action *ibact)
1115 {
1116 return container_of(ibact, struct mlx5_ib_flow_action, ib_action);
1117 }
1118
1119 static inline struct mlx5_user_mmap_entry *
to_mmmap(struct rdma_user_mmap_entry * rdma_entry)1120 to_mmmap(struct rdma_user_mmap_entry *rdma_entry)
1121 {
1122 return container_of(rdma_entry,
1123 struct mlx5_user_mmap_entry, rdma_entry);
1124 }
1125
1126 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context,
1127 struct ib_udata *udata, unsigned long virt,
1128 struct mlx5_db *db);
1129 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
1130 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1131 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1132 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
1133 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1134 struct ib_udata *udata);
1135 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
mlx5_ib_destroy_ah(struct ib_ah * ah,u32 flags)1136 static inline int mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags)
1137 {
1138 return 0;
1139 }
1140 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr,
1141 struct ib_udata *udata);
1142 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1143 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
1144 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
1145 int mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata);
1146 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
1147 const struct ib_recv_wr **bad_wr);
1148 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1149 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1150 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1151 struct ib_qp_init_attr *init_attr,
1152 struct ib_udata *udata);
1153 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1154 int attr_mask, struct ib_udata *udata);
1155 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1156 struct ib_qp_init_attr *qp_init_attr);
1157 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata);
1158 void mlx5_ib_drain_sq(struct ib_qp *qp);
1159 void mlx5_ib_drain_rq(struct ib_qp *qp);
1160 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1161 size_t buflen, size_t *bc);
1162 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1163 size_t buflen, size_t *bc);
1164 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
1165 size_t buflen, size_t *bc);
1166 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
1167 struct ib_udata *udata);
1168 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
1169 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1170 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
1171 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
1172 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
1173 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
1174 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1175 u64 virt_addr, int access_flags,
1176 struct ib_udata *udata);
1177 int mlx5_ib_advise_mr(struct ib_pd *pd,
1178 enum ib_uverbs_advise_mr_advice advice,
1179 u32 flags,
1180 struct ib_sge *sg_list,
1181 u32 num_sge,
1182 struct uverbs_attr_bundle *attrs);
1183 int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1184 int mlx5_ib_dealloc_mw(struct ib_mw *mw);
1185 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
1186 int page_shift, int flags);
1187 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
1188 struct ib_udata *udata,
1189 int access_flags);
1190 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr);
1191 void mlx5_ib_fence_odp_mr(struct mlx5_ib_mr *mr);
1192 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1193 u64 length, u64 virt_addr, int access_flags,
1194 struct ib_pd *pd, struct ib_udata *udata);
1195 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1196 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1197 u32 max_num_sg);
1198 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd,
1199 u32 max_num_sg,
1200 u32 max_num_meta_sg);
1201 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1202 unsigned int *sg_offset);
1203 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
1204 int data_sg_nents, unsigned int *data_sg_offset,
1205 struct scatterlist *meta_sg, int meta_sg_nents,
1206 unsigned int *meta_sg_offset);
1207 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
1208 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1209 const struct ib_mad *in, struct ib_mad *out,
1210 size_t *out_mad_size, u16 *out_mad_pkey_index);
1211 int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata);
1212 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata);
1213 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset);
1214 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port);
1215 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev,
1216 struct ib_smp *out_mad);
1217 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
1218 __be64 *sys_image_guid);
1219 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
1220 u16 *max_pkeys);
1221 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
1222 u32 *vendor_id);
1223 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
1224 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
1225 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index,
1226 u16 *pkey);
1227 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index,
1228 union ib_gid *gid);
1229 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port,
1230 struct ib_port_attr *props);
1231 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1232 struct ib_port_attr *props);
1233 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr,
1234 unsigned long max_page_shift,
1235 int *count, int *shift,
1236 int *ncont, int *order);
1237 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1238 int page_shift, size_t offset, size_t num_pages,
1239 __be64 *pas, int access_flags);
1240 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem,
1241 int page_shift, __be64 *pas, int access_flags);
1242 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
1243 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq);
1244 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev);
1245 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev);
1246
1247 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev,
1248 unsigned int entry, int access_flags);
1249 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
1250 int mlx5_mr_cache_invalidate(struct mlx5_ib_mr *mr);
1251
1252 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1253 struct ib_mr_status *mr_status);
1254 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
1255 struct ib_wq_init_attr *init_attr,
1256 struct ib_udata *udata);
1257 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata);
1258 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
1259 u32 wq_attr_mask, struct ib_udata *udata);
1260 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table,
1261 struct ib_rwq_ind_table_init_attr *init_attr,
1262 struct ib_udata *udata);
1263 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
1264 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
1265 struct ib_ucontext *context,
1266 struct ib_dm_alloc_attr *attr,
1267 struct uverbs_attr_bundle *attrs);
1268 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs);
1269 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1270 struct ib_dm_mr_attr *attr,
1271 struct uverbs_attr_bundle *attrs);
1272
1273 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1274 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev);
1275 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
1276 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev);
1277 int __init mlx5_ib_odp_init(void);
1278 void mlx5_ib_odp_cleanup(void);
1279 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent);
1280 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
1281 struct mlx5_ib_mr *mr, int flags);
1282
1283 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1284 enum ib_uverbs_advise_mr_advice advice,
1285 u32 flags, struct ib_sge *sg_list, u32 num_sge);
1286 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr, bool enable);
1287 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev * dev)1288 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
1289 {
1290 return;
1291 }
1292
mlx5_ib_odp_init_one(struct mlx5_ib_dev * ibdev)1293 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev * ibdev)1294 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {}
mlx5_ib_odp_init(void)1295 static inline int mlx5_ib_odp_init(void) { return 0; }
mlx5_ib_odp_cleanup(void)1296 static inline void mlx5_ib_odp_cleanup(void) {}
mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent * ent)1297 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {}
mlx5_odp_populate_xlt(void * xlt,size_t idx,size_t nentries,struct mlx5_ib_mr * mr,int flags)1298 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
1299 struct mlx5_ib_mr *mr, int flags) {}
1300
1301 static inline int
mlx5_ib_advise_mr_prefetch(struct ib_pd * pd,enum ib_uverbs_advise_mr_advice advice,u32 flags,struct ib_sge * sg_list,u32 num_sge)1302 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1303 enum ib_uverbs_advise_mr_advice advice, u32 flags,
1304 struct ib_sge *sg_list, u32 num_sge)
1305 {
1306 return -EOPNOTSUPP;
1307 }
mlx5_ib_init_odp_mr(struct mlx5_ib_mr * mr,bool enable)1308 static inline int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr, bool enable)
1309 {
1310 return -EOPNOTSUPP;
1311 }
1312 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1313
1314 extern const struct mmu_interval_notifier_ops mlx5_mn_ops;
1315
1316 /* Needed for rep profile */
1317 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
1318 const struct mlx5_ib_profile *profile,
1319 int stage);
1320 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
1321 const struct mlx5_ib_profile *profile);
1322
1323 int mlx5_ib_get_vf_config(struct ib_device *device, int vf,
1324 u8 port, struct ifla_vf_info *info);
1325 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf,
1326 u8 port, int state);
1327 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf,
1328 u8 port, struct ifla_vf_stats *stats);
1329 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u8 port,
1330 struct ifla_vf_guid *node_guid,
1331 struct ifla_vf_guid *port_guid);
1332 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port,
1333 u64 guid, int type);
1334
1335 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
1336 const struct ib_gid_attr *attr);
1337
1338 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1339 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num);
1340
1341 /* GSI QP helper functions */
1342 int mlx5_ib_create_gsi(struct ib_pd *pd, struct mlx5_ib_qp *mqp,
1343 struct ib_qp_init_attr *attr);
1344 int mlx5_ib_destroy_gsi(struct mlx5_ib_qp *mqp);
1345 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr,
1346 int attr_mask);
1347 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
1348 int qp_attr_mask,
1349 struct ib_qp_init_attr *qp_init_attr);
1350 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr,
1351 const struct ib_send_wr **bad_wr);
1352 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr,
1353 const struct ib_recv_wr **bad_wr);
1354 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi);
1355
1356 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc);
1357
1358 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi,
1359 int bfregn);
1360 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi);
1361 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev,
1362 u8 ib_port_num,
1363 u8 *native_port_num);
1364 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev,
1365 u8 port_num);
1366
1367 extern const struct uapi_definition mlx5_ib_devx_defs[];
1368 extern const struct uapi_definition mlx5_ib_flow_defs[];
1369 extern const struct uapi_definition mlx5_ib_qos_defs[];
1370 extern const struct uapi_definition mlx5_ib_std_types_defs[];
1371
init_query_mad(struct ib_smp * mad)1372 static inline void init_query_mad(struct ib_smp *mad)
1373 {
1374 mad->base_version = 1;
1375 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
1376 mad->class_version = 1;
1377 mad->method = IB_MGMT_METHOD_GET;
1378 }
1379
is_qp1(enum ib_qp_type qp_type)1380 static inline int is_qp1(enum ib_qp_type qp_type)
1381 {
1382 return qp_type == MLX5_IB_QPT_HW_GSI || qp_type == IB_QPT_GSI;
1383 }
1384
1385 #define MLX5_MAX_UMR_SHIFT 16
1386 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
1387
check_cq_create_flags(u32 flags)1388 static inline u32 check_cq_create_flags(u32 flags)
1389 {
1390 /*
1391 * It returns non-zero value for unsupported CQ
1392 * create flags, otherwise it returns zero.
1393 */
1394 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN |
1395 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION));
1396 }
1397
verify_assign_uidx(u8 cqe_version,u32 cmd_uidx,u32 * user_index)1398 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
1399 u32 *user_index)
1400 {
1401 if (cqe_version) {
1402 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
1403 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
1404 return -EINVAL;
1405 *user_index = cmd_uidx;
1406 } else {
1407 *user_index = MLX5_IB_DEFAULT_UIDX;
1408 }
1409
1410 return 0;
1411 }
1412
get_qp_user_index(struct mlx5_ib_ucontext * ucontext,struct mlx5_ib_create_qp * ucmd,int inlen,u32 * user_index)1413 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext,
1414 struct mlx5_ib_create_qp *ucmd,
1415 int inlen,
1416 u32 *user_index)
1417 {
1418 u8 cqe_version = ucontext->cqe_version;
1419
1420 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version &&
1421 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1422 return 0;
1423
1424 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version)
1425 return -EINVAL;
1426
1427 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1428 }
1429
get_srq_user_index(struct mlx5_ib_ucontext * ucontext,struct mlx5_ib_create_srq * ucmd,int inlen,u32 * user_index)1430 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
1431 struct mlx5_ib_create_srq *ucmd,
1432 int inlen,
1433 u32 *user_index)
1434 {
1435 u8 cqe_version = ucontext->cqe_version;
1436
1437 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version &&
1438 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1439 return 0;
1440
1441 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version)
1442 return -EINVAL;
1443
1444 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1445 }
1446
get_uars_per_sys_page(struct mlx5_ib_dev * dev,bool lib_support)1447 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support)
1448 {
1449 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1450 MLX5_UARS_IN_PAGE : 1;
1451 }
1452
get_num_static_uars(struct mlx5_ib_dev * dev,struct mlx5_bfreg_info * bfregi)1453 static inline int get_num_static_uars(struct mlx5_ib_dev *dev,
1454 struct mlx5_bfreg_info *bfregi)
1455 {
1456 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages;
1457 }
1458
1459 unsigned long mlx5_ib_get_xlt_emergency_page(void);
1460 void mlx5_ib_put_xlt_emergency_page(void);
1461
1462 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1463 struct mlx5_bfreg_info *bfregi, u32 bfregn,
1464 bool dyn_bfreg);
1465
mlx5_ib_can_load_pas_with_umr(struct mlx5_ib_dev * dev,size_t length)1466 static inline bool mlx5_ib_can_load_pas_with_umr(struct mlx5_ib_dev *dev,
1467 size_t length)
1468 {
1469 /*
1470 * umr_check_mkey_mask() rejects MLX5_MKEY_MASK_PAGE_SIZE which is
1471 * always set if MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (aka
1472 * MLX5_IB_UPD_XLT_ADDR and MLX5_IB_UPD_XLT_ENABLE) is set. Thus, a mkey
1473 * can never be enabled without this capability. Simplify this weird
1474 * quirky hardware by just saying it can't use PAS lists with UMR at
1475 * all.
1476 */
1477 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled))
1478 return false;
1479
1480 /*
1481 * length is the size of the MR in bytes when mlx5_ib_update_xlt() is
1482 * used.
1483 */
1484 if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset) &&
1485 length >= MLX5_MAX_UMR_PAGES * PAGE_SIZE)
1486 return false;
1487 return true;
1488 }
1489
1490 /*
1491 * true if an existing MR can be reconfigured to new access_flags using UMR.
1492 * Older HW cannot use UMR to update certain elements of the MKC. See
1493 * umr_check_mkey_mask(), get_umr_update_access_mask() and umr_check_mkey_mask()
1494 */
mlx5_ib_can_reconfig_with_umr(struct mlx5_ib_dev * dev,unsigned int current_access_flags,unsigned int target_access_flags)1495 static inline bool mlx5_ib_can_reconfig_with_umr(struct mlx5_ib_dev *dev,
1496 unsigned int current_access_flags,
1497 unsigned int target_access_flags)
1498 {
1499 unsigned int diffs = current_access_flags ^ target_access_flags;
1500
1501 if ((diffs & IB_ACCESS_REMOTE_ATOMIC) &&
1502 MLX5_CAP_GEN(dev->mdev, atomic) &&
1503 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled))
1504 return false;
1505
1506 if ((diffs & IB_ACCESS_RELAXED_ORDERING) &&
1507 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) &&
1508 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr))
1509 return false;
1510
1511 if ((diffs & IB_ACCESS_RELAXED_ORDERING) &&
1512 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) &&
1513 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr))
1514 return false;
1515
1516 return true;
1517 }
1518
1519 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev);
1520
mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev * dev)1521 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev)
1522 {
1523 return dev->lag_active ||
1524 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 &&
1525 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity));
1526 }
1527 #endif /* MLX5_IB_H */
1528