1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * rt5645.c -- RT5645 ALSA SoC audio codec driver
4 *
5 * Copyright 2013 Realtek Semiconductor Corp.
6 * Author: Bard Liao <bardliao@realtek.com>
7 */
8
9 #include <linux/module.h>
10 #include <linux/moduleparam.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/i2c.h>
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17 #include <linux/gpio.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/acpi.h>
20 #include <linux/dmi.h>
21 #include <linux/regulator/consumer.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/jack.h>
26 #include <sound/soc.h>
27 #include <sound/soc-dapm.h>
28 #include <sound/initval.h>
29 #include <sound/tlv.h>
30
31 #include "rl6231.h"
32 #include "rt5645.h"
33
34 #define QUIRK_INV_JD1_1(q) ((q) & 1)
35 #define QUIRK_LEVEL_IRQ(q) (((q) >> 1) & 1)
36 #define QUIRK_IN2_DIFF(q) (((q) >> 2) & 1)
37 #define QUIRK_JD_MODE(q) (((q) >> 4) & 7)
38 #define QUIRK_DMIC1_DATA_PIN(q) (((q) >> 8) & 3)
39 #define QUIRK_DMIC2_DATA_PIN(q) (((q) >> 12) & 3)
40
41 static unsigned int quirk = -1;
42 module_param(quirk, uint, 0444);
43 MODULE_PARM_DESC(quirk, "RT5645 pdata quirk override");
44
45 #define RT5645_DEVICE_ID 0x6308
46 #define RT5650_DEVICE_ID 0x6419
47
48 #define RT5645_PR_RANGE_BASE (0xff + 1)
49 #define RT5645_PR_SPACING 0x100
50
51 #define RT5645_PR_BASE (RT5645_PR_RANGE_BASE + (0 * RT5645_PR_SPACING))
52
53 #define RT5645_HWEQ_NUM 57
54
55 #define TIME_TO_POWER_MS 400
56
57 static const struct regmap_range_cfg rt5645_ranges[] = {
58 {
59 .name = "PR",
60 .range_min = RT5645_PR_BASE,
61 .range_max = RT5645_PR_BASE + 0xf8,
62 .selector_reg = RT5645_PRIV_INDEX,
63 .selector_mask = 0xff,
64 .selector_shift = 0x0,
65 .window_start = RT5645_PRIV_DATA,
66 .window_len = 0x1,
67 },
68 };
69
70 static const struct reg_sequence init_list[] = {
71 {RT5645_PR_BASE + 0x3d, 0x3600},
72 {RT5645_PR_BASE + 0x1c, 0xfd70},
73 {RT5645_PR_BASE + 0x20, 0x611f},
74 {RT5645_PR_BASE + 0x21, 0x4040},
75 {RT5645_PR_BASE + 0x23, 0x0004},
76 {RT5645_ASRC_4, 0x0120},
77 };
78
79 static const struct reg_sequence rt5650_init_list[] = {
80 {0xf6, 0x0100},
81 };
82
83 static const struct reg_default rt5645_reg[] = {
84 { 0x00, 0x0000 },
85 { 0x01, 0xc8c8 },
86 { 0x02, 0xc8c8 },
87 { 0x03, 0xc8c8 },
88 { 0x0a, 0x0002 },
89 { 0x0b, 0x2827 },
90 { 0x0c, 0xe000 },
91 { 0x0d, 0x0000 },
92 { 0x0e, 0x0000 },
93 { 0x0f, 0x0808 },
94 { 0x14, 0x3333 },
95 { 0x16, 0x4b00 },
96 { 0x18, 0x018b },
97 { 0x19, 0xafaf },
98 { 0x1a, 0xafaf },
99 { 0x1b, 0x0001 },
100 { 0x1c, 0x2f2f },
101 { 0x1d, 0x2f2f },
102 { 0x1e, 0x0000 },
103 { 0x20, 0x0000 },
104 { 0x27, 0x7060 },
105 { 0x28, 0x7070 },
106 { 0x29, 0x8080 },
107 { 0x2a, 0x5656 },
108 { 0x2b, 0x5454 },
109 { 0x2c, 0xaaa0 },
110 { 0x2d, 0x0000 },
111 { 0x2f, 0x1002 },
112 { 0x31, 0x5000 },
113 { 0x32, 0x0000 },
114 { 0x33, 0x0000 },
115 { 0x34, 0x0000 },
116 { 0x35, 0x0000 },
117 { 0x3b, 0x0000 },
118 { 0x3c, 0x007f },
119 { 0x3d, 0x0000 },
120 { 0x3e, 0x007f },
121 { 0x3f, 0x0000 },
122 { 0x40, 0x001f },
123 { 0x41, 0x0000 },
124 { 0x42, 0x001f },
125 { 0x45, 0x6000 },
126 { 0x46, 0x003e },
127 { 0x47, 0x003e },
128 { 0x48, 0xf807 },
129 { 0x4a, 0x0004 },
130 { 0x4d, 0x0000 },
131 { 0x4e, 0x0000 },
132 { 0x4f, 0x01ff },
133 { 0x50, 0x0000 },
134 { 0x51, 0x0000 },
135 { 0x52, 0x01ff },
136 { 0x53, 0xf000 },
137 { 0x56, 0x0111 },
138 { 0x57, 0x0064 },
139 { 0x58, 0xef0e },
140 { 0x59, 0xf0f0 },
141 { 0x5a, 0xef0e },
142 { 0x5b, 0xf0f0 },
143 { 0x5c, 0xef0e },
144 { 0x5d, 0xf0f0 },
145 { 0x5e, 0xf000 },
146 { 0x5f, 0x0000 },
147 { 0x61, 0x0300 },
148 { 0x62, 0x0000 },
149 { 0x63, 0x00c2 },
150 { 0x64, 0x0000 },
151 { 0x65, 0x0000 },
152 { 0x66, 0x0000 },
153 { 0x6a, 0x0000 },
154 { 0x6c, 0x0aaa },
155 { 0x70, 0x8000 },
156 { 0x71, 0x8000 },
157 { 0x72, 0x8000 },
158 { 0x73, 0x7770 },
159 { 0x74, 0x3e00 },
160 { 0x75, 0x2409 },
161 { 0x76, 0x000a },
162 { 0x77, 0x0c00 },
163 { 0x78, 0x0000 },
164 { 0x79, 0x0123 },
165 { 0x80, 0x0000 },
166 { 0x81, 0x0000 },
167 { 0x82, 0x0000 },
168 { 0x83, 0x0000 },
169 { 0x84, 0x0000 },
170 { 0x85, 0x0000 },
171 { 0x8a, 0x0120 },
172 { 0x8e, 0x0004 },
173 { 0x8f, 0x1100 },
174 { 0x90, 0x0646 },
175 { 0x91, 0x0c06 },
176 { 0x93, 0x0000 },
177 { 0x94, 0x0200 },
178 { 0x95, 0x0000 },
179 { 0x9a, 0x2184 },
180 { 0x9b, 0x010a },
181 { 0x9c, 0x0aea },
182 { 0x9d, 0x000c },
183 { 0x9e, 0x0400 },
184 { 0xa0, 0xa0a8 },
185 { 0xa1, 0x0059 },
186 { 0xa2, 0x0001 },
187 { 0xae, 0x6000 },
188 { 0xaf, 0x0000 },
189 { 0xb0, 0x6000 },
190 { 0xb1, 0x0000 },
191 { 0xb2, 0x0000 },
192 { 0xb3, 0x001f },
193 { 0xb4, 0x020c },
194 { 0xb5, 0x1f00 },
195 { 0xb6, 0x0000 },
196 { 0xbb, 0x0000 },
197 { 0xbc, 0x0000 },
198 { 0xbd, 0x0000 },
199 { 0xbe, 0x0000 },
200 { 0xbf, 0x3100 },
201 { 0xc0, 0x0000 },
202 { 0xc1, 0x0000 },
203 { 0xc2, 0x0000 },
204 { 0xc3, 0x2000 },
205 { 0xcd, 0x0000 },
206 { 0xce, 0x0000 },
207 { 0xcf, 0x1813 },
208 { 0xd0, 0x0690 },
209 { 0xd1, 0x1c17 },
210 { 0xd3, 0xb320 },
211 { 0xd4, 0x0000 },
212 { 0xd6, 0x0400 },
213 { 0xd9, 0x0809 },
214 { 0xda, 0x0000 },
215 { 0xdb, 0x0003 },
216 { 0xdc, 0x0049 },
217 { 0xdd, 0x001b },
218 { 0xdf, 0x0008 },
219 { 0xe0, 0x4000 },
220 { 0xe6, 0x8000 },
221 { 0xe7, 0x0200 },
222 { 0xec, 0xb300 },
223 { 0xed, 0x0000 },
224 { 0xf0, 0x001f },
225 { 0xf1, 0x020c },
226 { 0xf2, 0x1f00 },
227 { 0xf3, 0x0000 },
228 { 0xf4, 0x4000 },
229 { 0xf8, 0x0000 },
230 { 0xf9, 0x0000 },
231 { 0xfa, 0x2060 },
232 { 0xfb, 0x4040 },
233 { 0xfc, 0x0000 },
234 { 0xfd, 0x0002 },
235 { 0xfe, 0x10ec },
236 { 0xff, 0x6308 },
237 };
238
239 static const struct reg_default rt5650_reg[] = {
240 { 0x00, 0x0000 },
241 { 0x01, 0xc8c8 },
242 { 0x02, 0xc8c8 },
243 { 0x03, 0xc8c8 },
244 { 0x0a, 0x0002 },
245 { 0x0b, 0x2827 },
246 { 0x0c, 0xe000 },
247 { 0x0d, 0x0000 },
248 { 0x0e, 0x0000 },
249 { 0x0f, 0x0808 },
250 { 0x14, 0x3333 },
251 { 0x16, 0x4b00 },
252 { 0x18, 0x018b },
253 { 0x19, 0xafaf },
254 { 0x1a, 0xafaf },
255 { 0x1b, 0x0001 },
256 { 0x1c, 0x2f2f },
257 { 0x1d, 0x2f2f },
258 { 0x1e, 0x0000 },
259 { 0x20, 0x0000 },
260 { 0x27, 0x7060 },
261 { 0x28, 0x7070 },
262 { 0x29, 0x8080 },
263 { 0x2a, 0x5656 },
264 { 0x2b, 0x5454 },
265 { 0x2c, 0xaaa0 },
266 { 0x2d, 0x0000 },
267 { 0x2f, 0x5002 },
268 { 0x31, 0x5000 },
269 { 0x32, 0x0000 },
270 { 0x33, 0x0000 },
271 { 0x34, 0x0000 },
272 { 0x35, 0x0000 },
273 { 0x3b, 0x0000 },
274 { 0x3c, 0x007f },
275 { 0x3d, 0x0000 },
276 { 0x3e, 0x007f },
277 { 0x3f, 0x0000 },
278 { 0x40, 0x001f },
279 { 0x41, 0x0000 },
280 { 0x42, 0x001f },
281 { 0x45, 0x6000 },
282 { 0x46, 0x003e },
283 { 0x47, 0x003e },
284 { 0x48, 0xf807 },
285 { 0x4a, 0x0004 },
286 { 0x4d, 0x0000 },
287 { 0x4e, 0x0000 },
288 { 0x4f, 0x01ff },
289 { 0x50, 0x0000 },
290 { 0x51, 0x0000 },
291 { 0x52, 0x01ff },
292 { 0x53, 0xf000 },
293 { 0x56, 0x0111 },
294 { 0x57, 0x0064 },
295 { 0x58, 0xef0e },
296 { 0x59, 0xf0f0 },
297 { 0x5a, 0xef0e },
298 { 0x5b, 0xf0f0 },
299 { 0x5c, 0xef0e },
300 { 0x5d, 0xf0f0 },
301 { 0x5e, 0xf000 },
302 { 0x5f, 0x0000 },
303 { 0x61, 0x0300 },
304 { 0x62, 0x0000 },
305 { 0x63, 0x00c2 },
306 { 0x64, 0x0000 },
307 { 0x65, 0x0000 },
308 { 0x66, 0x0000 },
309 { 0x6a, 0x0000 },
310 { 0x6c, 0x0aaa },
311 { 0x70, 0x8000 },
312 { 0x71, 0x8000 },
313 { 0x72, 0x8000 },
314 { 0x73, 0x7770 },
315 { 0x74, 0x3e00 },
316 { 0x75, 0x2409 },
317 { 0x76, 0x000a },
318 { 0x77, 0x0c00 },
319 { 0x78, 0x0000 },
320 { 0x79, 0x0123 },
321 { 0x7a, 0x0123 },
322 { 0x80, 0x0000 },
323 { 0x81, 0x0000 },
324 { 0x82, 0x0000 },
325 { 0x83, 0x0000 },
326 { 0x84, 0x0000 },
327 { 0x85, 0x0000 },
328 { 0x8a, 0x0120 },
329 { 0x8e, 0x0004 },
330 { 0x8f, 0x1100 },
331 { 0x90, 0x0646 },
332 { 0x91, 0x0c06 },
333 { 0x93, 0x0000 },
334 { 0x94, 0x0200 },
335 { 0x95, 0x0000 },
336 { 0x9a, 0x2184 },
337 { 0x9b, 0x010a },
338 { 0x9c, 0x0aea },
339 { 0x9d, 0x000c },
340 { 0x9e, 0x0400 },
341 { 0xa0, 0xa0a8 },
342 { 0xa1, 0x0059 },
343 { 0xa2, 0x0001 },
344 { 0xae, 0x6000 },
345 { 0xaf, 0x0000 },
346 { 0xb0, 0x6000 },
347 { 0xb1, 0x0000 },
348 { 0xb2, 0x0000 },
349 { 0xb3, 0x001f },
350 { 0xb4, 0x020c },
351 { 0xb5, 0x1f00 },
352 { 0xb6, 0x0000 },
353 { 0xbb, 0x0000 },
354 { 0xbc, 0x0000 },
355 { 0xbd, 0x0000 },
356 { 0xbe, 0x0000 },
357 { 0xbf, 0x3100 },
358 { 0xc0, 0x0000 },
359 { 0xc1, 0x0000 },
360 { 0xc2, 0x0000 },
361 { 0xc3, 0x2000 },
362 { 0xcd, 0x0000 },
363 { 0xce, 0x0000 },
364 { 0xcf, 0x1813 },
365 { 0xd0, 0x0690 },
366 { 0xd1, 0x1c17 },
367 { 0xd3, 0xb320 },
368 { 0xd4, 0x0000 },
369 { 0xd6, 0x0400 },
370 { 0xd9, 0x0809 },
371 { 0xda, 0x0000 },
372 { 0xdb, 0x0003 },
373 { 0xdc, 0x0049 },
374 { 0xdd, 0x001b },
375 { 0xdf, 0x0008 },
376 { 0xe0, 0x4000 },
377 { 0xe6, 0x8000 },
378 { 0xe7, 0x0200 },
379 { 0xec, 0xb300 },
380 { 0xed, 0x0000 },
381 { 0xf0, 0x001f },
382 { 0xf1, 0x020c },
383 { 0xf2, 0x1f00 },
384 { 0xf3, 0x0000 },
385 { 0xf4, 0x4000 },
386 { 0xf8, 0x0000 },
387 { 0xf9, 0x0000 },
388 { 0xfa, 0x2060 },
389 { 0xfb, 0x4040 },
390 { 0xfc, 0x0000 },
391 { 0xfd, 0x0002 },
392 { 0xfe, 0x10ec },
393 { 0xff, 0x6308 },
394 };
395
396 struct rt5645_eq_param_s {
397 unsigned short reg;
398 unsigned short val;
399 };
400
401 struct rt5645_eq_param_s_be16 {
402 __be16 reg;
403 __be16 val;
404 };
405
406 static const char *const rt5645_supply_names[] = {
407 "avdd",
408 "cpvdd",
409 };
410
411 struct rt5645_priv {
412 struct snd_soc_component *component;
413 struct rt5645_platform_data pdata;
414 struct regmap *regmap;
415 struct i2c_client *i2c;
416 struct gpio_desc *gpiod_hp_det;
417 struct snd_soc_jack *hp_jack;
418 struct snd_soc_jack *mic_jack;
419 struct snd_soc_jack *btn_jack;
420 struct delayed_work jack_detect_work, rcclock_work;
421 struct regulator_bulk_data supplies[ARRAY_SIZE(rt5645_supply_names)];
422 struct rt5645_eq_param_s *eq_param;
423 struct timer_list btn_check_timer;
424 struct mutex jd_mutex;
425
426 int codec_type;
427 int sysclk;
428 int sysclk_src;
429 int lrck[RT5645_AIFS];
430 int bclk[RT5645_AIFS];
431 int master[RT5645_AIFS];
432
433 int pll_src;
434 int pll_in;
435 int pll_out;
436
437 int jack_type;
438 bool en_button_func;
439 bool hp_on;
440 int v_id;
441 };
442
rt5645_reset(struct snd_soc_component * component)443 static int rt5645_reset(struct snd_soc_component *component)
444 {
445 return snd_soc_component_write(component, RT5645_RESET, 0);
446 }
447
rt5645_volatile_register(struct device * dev,unsigned int reg)448 static bool rt5645_volatile_register(struct device *dev, unsigned int reg)
449 {
450 int i;
451
452 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
453 if (reg >= rt5645_ranges[i].range_min &&
454 reg <= rt5645_ranges[i].range_max) {
455 return true;
456 }
457 }
458
459 switch (reg) {
460 case RT5645_RESET:
461 case RT5645_PRIV_INDEX:
462 case RT5645_PRIV_DATA:
463 case RT5645_IN1_CTRL1:
464 case RT5645_IN1_CTRL2:
465 case RT5645_IN1_CTRL3:
466 case RT5645_A_JD_CTRL1:
467 case RT5645_ADC_EQ_CTRL1:
468 case RT5645_EQ_CTRL1:
469 case RT5645_ALC_CTRL_1:
470 case RT5645_IRQ_CTRL2:
471 case RT5645_IRQ_CTRL3:
472 case RT5645_INT_IRQ_ST:
473 case RT5645_IL_CMD:
474 case RT5650_4BTN_IL_CMD1:
475 case RT5645_VENDOR_ID:
476 case RT5645_VENDOR_ID1:
477 case RT5645_VENDOR_ID2:
478 return true;
479 default:
480 return false;
481 }
482 }
483
rt5645_readable_register(struct device * dev,unsigned int reg)484 static bool rt5645_readable_register(struct device *dev, unsigned int reg)
485 {
486 int i;
487
488 for (i = 0; i < ARRAY_SIZE(rt5645_ranges); i++) {
489 if (reg >= rt5645_ranges[i].range_min &&
490 reg <= rt5645_ranges[i].range_max) {
491 return true;
492 }
493 }
494
495 switch (reg) {
496 case RT5645_RESET:
497 case RT5645_SPK_VOL:
498 case RT5645_HP_VOL:
499 case RT5645_LOUT1:
500 case RT5645_IN1_CTRL1:
501 case RT5645_IN1_CTRL2:
502 case RT5645_IN1_CTRL3:
503 case RT5645_IN2_CTRL:
504 case RT5645_INL1_INR1_VOL:
505 case RT5645_SPK_FUNC_LIM:
506 case RT5645_ADJ_HPF_CTRL:
507 case RT5645_DAC1_DIG_VOL:
508 case RT5645_DAC2_DIG_VOL:
509 case RT5645_DAC_CTRL:
510 case RT5645_STO1_ADC_DIG_VOL:
511 case RT5645_MONO_ADC_DIG_VOL:
512 case RT5645_ADC_BST_VOL1:
513 case RT5645_ADC_BST_VOL2:
514 case RT5645_STO1_ADC_MIXER:
515 case RT5645_MONO_ADC_MIXER:
516 case RT5645_AD_DA_MIXER:
517 case RT5645_STO_DAC_MIXER:
518 case RT5645_MONO_DAC_MIXER:
519 case RT5645_DIG_MIXER:
520 case RT5650_A_DAC_SOUR:
521 case RT5645_DIG_INF1_DATA:
522 case RT5645_PDM_OUT_CTRL:
523 case RT5645_REC_L1_MIXER:
524 case RT5645_REC_L2_MIXER:
525 case RT5645_REC_R1_MIXER:
526 case RT5645_REC_R2_MIXER:
527 case RT5645_HPMIXL_CTRL:
528 case RT5645_HPOMIXL_CTRL:
529 case RT5645_HPMIXR_CTRL:
530 case RT5645_HPOMIXR_CTRL:
531 case RT5645_HPO_MIXER:
532 case RT5645_SPK_L_MIXER:
533 case RT5645_SPK_R_MIXER:
534 case RT5645_SPO_MIXER:
535 case RT5645_SPO_CLSD_RATIO:
536 case RT5645_OUT_L1_MIXER:
537 case RT5645_OUT_R1_MIXER:
538 case RT5645_OUT_L_GAIN1:
539 case RT5645_OUT_L_GAIN2:
540 case RT5645_OUT_R_GAIN1:
541 case RT5645_OUT_R_GAIN2:
542 case RT5645_LOUT_MIXER:
543 case RT5645_HAPTIC_CTRL1:
544 case RT5645_HAPTIC_CTRL2:
545 case RT5645_HAPTIC_CTRL3:
546 case RT5645_HAPTIC_CTRL4:
547 case RT5645_HAPTIC_CTRL5:
548 case RT5645_HAPTIC_CTRL6:
549 case RT5645_HAPTIC_CTRL7:
550 case RT5645_HAPTIC_CTRL8:
551 case RT5645_HAPTIC_CTRL9:
552 case RT5645_HAPTIC_CTRL10:
553 case RT5645_PWR_DIG1:
554 case RT5645_PWR_DIG2:
555 case RT5645_PWR_ANLG1:
556 case RT5645_PWR_ANLG2:
557 case RT5645_PWR_MIXER:
558 case RT5645_PWR_VOL:
559 case RT5645_PRIV_INDEX:
560 case RT5645_PRIV_DATA:
561 case RT5645_I2S1_SDP:
562 case RT5645_I2S2_SDP:
563 case RT5645_ADDA_CLK1:
564 case RT5645_ADDA_CLK2:
565 case RT5645_DMIC_CTRL1:
566 case RT5645_DMIC_CTRL2:
567 case RT5645_TDM_CTRL_1:
568 case RT5645_TDM_CTRL_2:
569 case RT5645_TDM_CTRL_3:
570 case RT5650_TDM_CTRL_4:
571 case RT5645_GLB_CLK:
572 case RT5645_PLL_CTRL1:
573 case RT5645_PLL_CTRL2:
574 case RT5645_ASRC_1:
575 case RT5645_ASRC_2:
576 case RT5645_ASRC_3:
577 case RT5645_ASRC_4:
578 case RT5645_DEPOP_M1:
579 case RT5645_DEPOP_M2:
580 case RT5645_DEPOP_M3:
581 case RT5645_CHARGE_PUMP:
582 case RT5645_MICBIAS:
583 case RT5645_A_JD_CTRL1:
584 case RT5645_VAD_CTRL4:
585 case RT5645_CLSD_OUT_CTRL:
586 case RT5645_ADC_EQ_CTRL1:
587 case RT5645_ADC_EQ_CTRL2:
588 case RT5645_EQ_CTRL1:
589 case RT5645_EQ_CTRL2:
590 case RT5645_ALC_CTRL_1:
591 case RT5645_ALC_CTRL_2:
592 case RT5645_ALC_CTRL_3:
593 case RT5645_ALC_CTRL_4:
594 case RT5645_ALC_CTRL_5:
595 case RT5645_JD_CTRL:
596 case RT5645_IRQ_CTRL1:
597 case RT5645_IRQ_CTRL2:
598 case RT5645_IRQ_CTRL3:
599 case RT5645_INT_IRQ_ST:
600 case RT5645_GPIO_CTRL1:
601 case RT5645_GPIO_CTRL2:
602 case RT5645_GPIO_CTRL3:
603 case RT5645_BASS_BACK:
604 case RT5645_MP3_PLUS1:
605 case RT5645_MP3_PLUS2:
606 case RT5645_ADJ_HPF1:
607 case RT5645_ADJ_HPF2:
608 case RT5645_HP_CALIB_AMP_DET:
609 case RT5645_SV_ZCD1:
610 case RT5645_SV_ZCD2:
611 case RT5645_IL_CMD:
612 case RT5645_IL_CMD2:
613 case RT5645_IL_CMD3:
614 case RT5650_4BTN_IL_CMD1:
615 case RT5650_4BTN_IL_CMD2:
616 case RT5645_DRC1_HL_CTRL1:
617 case RT5645_DRC2_HL_CTRL1:
618 case RT5645_ADC_MONO_HP_CTRL1:
619 case RT5645_ADC_MONO_HP_CTRL2:
620 case RT5645_DRC2_CTRL1:
621 case RT5645_DRC2_CTRL2:
622 case RT5645_DRC2_CTRL3:
623 case RT5645_DRC2_CTRL4:
624 case RT5645_DRC2_CTRL5:
625 case RT5645_JD_CTRL3:
626 case RT5645_JD_CTRL4:
627 case RT5645_GEN_CTRL1:
628 case RT5645_GEN_CTRL2:
629 case RT5645_GEN_CTRL3:
630 case RT5645_VENDOR_ID:
631 case RT5645_VENDOR_ID1:
632 case RT5645_VENDOR_ID2:
633 return true;
634 default:
635 return false;
636 }
637 }
638
639 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
640 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
641 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
642 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
643 static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
644
645 /* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
646 static const DECLARE_TLV_DB_RANGE(bst_tlv,
647 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
648 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
649 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
650 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
651 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
652 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
653 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
654 );
655
656 /* {-6, -4.5, -3, -1.5, 0, 0.82, 1.58, 2.28} dB */
657 static const DECLARE_TLV_DB_RANGE(spk_clsd_tlv,
658 0, 4, TLV_DB_SCALE_ITEM(-600, 150, 0),
659 5, 5, TLV_DB_SCALE_ITEM(82, 0, 0),
660 6, 6, TLV_DB_SCALE_ITEM(158, 0, 0),
661 7, 7, TLV_DB_SCALE_ITEM(228, 0, 0)
662 );
663
rt5645_hweq_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)664 static int rt5645_hweq_info(struct snd_kcontrol *kcontrol,
665 struct snd_ctl_elem_info *uinfo)
666 {
667 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
668 uinfo->count = RT5645_HWEQ_NUM * sizeof(struct rt5645_eq_param_s);
669
670 return 0;
671 }
672
rt5645_hweq_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)673 static int rt5645_hweq_get(struct snd_kcontrol *kcontrol,
674 struct snd_ctl_elem_value *ucontrol)
675 {
676 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
677 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
678 struct rt5645_eq_param_s_be16 *eq_param =
679 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;
680 int i;
681
682 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
683 eq_param[i].reg = cpu_to_be16(rt5645->eq_param[i].reg);
684 eq_param[i].val = cpu_to_be16(rt5645->eq_param[i].val);
685 }
686
687 return 0;
688 }
689
rt5645_validate_hweq(unsigned short reg)690 static bool rt5645_validate_hweq(unsigned short reg)
691 {
692 if ((reg >= 0x1a4 && reg <= 0x1cd) | (reg >= 0x1e5 && reg <= 0x1f8) |
693 (reg == RT5645_EQ_CTRL2))
694 return true;
695
696 return false;
697 }
698
rt5645_hweq_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)699 static int rt5645_hweq_put(struct snd_kcontrol *kcontrol,
700 struct snd_ctl_elem_value *ucontrol)
701 {
702 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
703 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
704 struct rt5645_eq_param_s_be16 *eq_param =
705 (struct rt5645_eq_param_s_be16 *)ucontrol->value.bytes.data;
706 int i;
707
708 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
709 rt5645->eq_param[i].reg = be16_to_cpu(eq_param[i].reg);
710 rt5645->eq_param[i].val = be16_to_cpu(eq_param[i].val);
711 }
712
713 /* The final setting of the table should be RT5645_EQ_CTRL2 */
714 for (i = RT5645_HWEQ_NUM - 1; i >= 0; i--) {
715 if (rt5645->eq_param[i].reg == 0)
716 continue;
717 else if (rt5645->eq_param[i].reg != RT5645_EQ_CTRL2)
718 return 0;
719 else
720 break;
721 }
722
723 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
724 if (!rt5645_validate_hweq(rt5645->eq_param[i].reg) &&
725 rt5645->eq_param[i].reg != 0)
726 return 0;
727 else if (rt5645->eq_param[i].reg == 0)
728 break;
729 }
730
731 return 0;
732 }
733
734 #define RT5645_HWEQ(xname) \
735 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
736 .info = rt5645_hweq_info, \
737 .get = rt5645_hweq_get, \
738 .put = rt5645_hweq_put \
739 }
740
rt5645_spk_put_volsw(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)741 static int rt5645_spk_put_volsw(struct snd_kcontrol *kcontrol,
742 struct snd_ctl_elem_value *ucontrol)
743 {
744 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
745 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
746 int ret;
747
748 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
749 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PU);
750
751 ret = snd_soc_put_volsw(kcontrol, ucontrol);
752
753 mod_delayed_work(system_power_efficient_wq, &rt5645->rcclock_work,
754 msecs_to_jiffies(200));
755
756 return ret;
757 }
758
759 static const char * const rt5645_dac1_vol_ctrl_mode_text[] = {
760 "immediately", "zero crossing", "soft ramp"
761 };
762
763 static SOC_ENUM_SINGLE_DECL(
764 rt5645_dac1_vol_ctrl_mode, RT5645_PR_BASE,
765 RT5645_DA1_ZDET_SFT, rt5645_dac1_vol_ctrl_mode_text);
766
767 static const struct snd_kcontrol_new rt5645_snd_controls[] = {
768 /* Speaker Output Volume */
769 SOC_DOUBLE("Speaker Channel Switch", RT5645_SPK_VOL,
770 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
771 SOC_DOUBLE_EXT_TLV("Speaker Playback Volume", RT5645_SPK_VOL,
772 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, snd_soc_get_volsw,
773 rt5645_spk_put_volsw, out_vol_tlv),
774
775 /* ClassD modulator Speaker Gain Ratio */
776 SOC_SINGLE_TLV("Speaker ClassD Playback Volume", RT5645_SPO_CLSD_RATIO,
777 RT5645_SPK_G_CLSD_SFT, 7, 0, spk_clsd_tlv),
778
779 /* Headphone Output Volume */
780 SOC_DOUBLE("Headphone Channel Switch", RT5645_HP_VOL,
781 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
782 SOC_DOUBLE_TLV("Headphone Playback Volume", RT5645_HP_VOL,
783 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
784
785 /* OUTPUT Control */
786 SOC_DOUBLE("OUT Playback Switch", RT5645_LOUT1,
787 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
788 SOC_DOUBLE("OUT Channel Switch", RT5645_LOUT1,
789 RT5645_VOL_L_SFT, RT5645_VOL_R_SFT, 1, 1),
790 SOC_DOUBLE_TLV("OUT Playback Volume", RT5645_LOUT1,
791 RT5645_L_VOL_SFT, RT5645_R_VOL_SFT, 39, 1, out_vol_tlv),
792
793 /* DAC Digital Volume */
794 SOC_DOUBLE("DAC2 Playback Switch", RT5645_DAC_CTRL,
795 RT5645_M_DAC_L2_VOL_SFT, RT5645_M_DAC_R2_VOL_SFT, 1, 1),
796 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5645_DAC1_DIG_VOL,
797 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
798 SOC_DOUBLE_TLV("Mono DAC Playback Volume", RT5645_DAC2_DIG_VOL,
799 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 87, 0, dac_vol_tlv),
800
801 /* IN1/IN2 Control */
802 SOC_SINGLE_TLV("IN1 Boost", RT5645_IN1_CTRL1,
803 RT5645_BST_SFT1, 12, 0, bst_tlv),
804 SOC_SINGLE_TLV("IN2 Boost", RT5645_IN2_CTRL,
805 RT5645_BST_SFT2, 8, 0, bst_tlv),
806
807 /* INL/INR Volume Control */
808 SOC_DOUBLE_TLV("IN Capture Volume", RT5645_INL1_INR1_VOL,
809 RT5645_INL_VOL_SFT, RT5645_INR_VOL_SFT, 31, 1, in_vol_tlv),
810
811 /* ADC Digital Volume Control */
812 SOC_DOUBLE("ADC Capture Switch", RT5645_STO1_ADC_DIG_VOL,
813 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
814 SOC_DOUBLE_TLV("ADC Capture Volume", RT5645_STO1_ADC_DIG_VOL,
815 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
816 SOC_DOUBLE("Mono ADC Capture Switch", RT5645_MONO_ADC_DIG_VOL,
817 RT5645_L_MUTE_SFT, RT5645_R_MUTE_SFT, 1, 1),
818 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5645_MONO_ADC_DIG_VOL,
819 RT5645_L_VOL_SFT + 1, RT5645_R_VOL_SFT + 1, 63, 0, adc_vol_tlv),
820
821 /* ADC Boost Volume Control */
822 SOC_DOUBLE_TLV("ADC Boost Capture Volume", RT5645_ADC_BST_VOL1,
823 RT5645_STO1_ADC_L_BST_SFT, RT5645_STO1_ADC_R_BST_SFT, 3, 0,
824 adc_bst_tlv),
825 SOC_DOUBLE_TLV("Mono ADC Boost Capture Volume", RT5645_ADC_BST_VOL2,
826 RT5645_MONO_ADC_L_BST_SFT, RT5645_MONO_ADC_R_BST_SFT, 3, 0,
827 adc_bst_tlv),
828
829 /* I2S2 function select */
830 SOC_SINGLE("I2S2 Func Switch", RT5645_GPIO_CTRL1, RT5645_I2S2_SEL_SFT,
831 1, 1),
832 RT5645_HWEQ("Speaker HWEQ"),
833
834 /* Digital Soft Volume Control */
835 SOC_ENUM("DAC1 Digital Volume Control Func", rt5645_dac1_vol_ctrl_mode),
836 };
837
838 /**
839 * set_dmic_clk - Set parameter of dmic.
840 *
841 * @w: DAPM widget.
842 * @kcontrol: The kcontrol of this widget.
843 * @event: Event id.
844 *
845 */
set_dmic_clk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)846 static int set_dmic_clk(struct snd_soc_dapm_widget *w,
847 struct snd_kcontrol *kcontrol, int event)
848 {
849 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
850 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
851 int idx, rate;
852
853 rate = rt5645->sysclk / rl6231_get_pre_div(rt5645->regmap,
854 RT5645_ADDA_CLK1, RT5645_I2S_PD1_SFT);
855 idx = rl6231_calc_dmic_clk(rate);
856 if (idx < 0)
857 dev_err(component->dev, "Failed to set DMIC clock\n");
858 else
859 snd_soc_component_update_bits(component, RT5645_DMIC_CTRL1,
860 RT5645_DMIC_CLK_MASK, idx << RT5645_DMIC_CLK_SFT);
861 return idx;
862 }
863
is_sys_clk_from_pll(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)864 static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
865 struct snd_soc_dapm_widget *sink)
866 {
867 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
868 unsigned int val;
869
870 val = snd_soc_component_read(component, RT5645_GLB_CLK);
871 val &= RT5645_SCLK_SRC_MASK;
872 if (val == RT5645_SCLK_SRC_PLL1)
873 return 1;
874 else
875 return 0;
876 }
877
is_using_asrc(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)878 static int is_using_asrc(struct snd_soc_dapm_widget *source,
879 struct snd_soc_dapm_widget *sink)
880 {
881 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
882 unsigned int reg, shift, val;
883
884 switch (source->shift) {
885 case 0:
886 reg = RT5645_ASRC_3;
887 shift = 0;
888 break;
889 case 1:
890 reg = RT5645_ASRC_3;
891 shift = 4;
892 break;
893 case 3:
894 reg = RT5645_ASRC_2;
895 shift = 0;
896 break;
897 case 8:
898 reg = RT5645_ASRC_2;
899 shift = 4;
900 break;
901 case 9:
902 reg = RT5645_ASRC_2;
903 shift = 8;
904 break;
905 case 10:
906 reg = RT5645_ASRC_2;
907 shift = 12;
908 break;
909 default:
910 return 0;
911 }
912
913 val = (snd_soc_component_read(component, reg) >> shift) & 0xf;
914 switch (val) {
915 case 1:
916 case 2:
917 case 3:
918 case 4:
919 return 1;
920 default:
921 return 0;
922 }
923
924 }
925
rt5645_enable_hweq(struct snd_soc_component * component)926 static int rt5645_enable_hweq(struct snd_soc_component *component)
927 {
928 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
929 int i;
930
931 for (i = 0; i < RT5645_HWEQ_NUM; i++) {
932 if (rt5645_validate_hweq(rt5645->eq_param[i].reg))
933 regmap_write(rt5645->regmap, rt5645->eq_param[i].reg,
934 rt5645->eq_param[i].val);
935 else
936 break;
937 }
938
939 return 0;
940 }
941
942 /**
943 * rt5645_sel_asrc_clk_src - select ASRC clock source for a set of filters
944 * @component: SoC audio component device.
945 * @filter_mask: mask of filters.
946 * @clk_src: clock source
947 *
948 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5645 can
949 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
950 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
951 * ASRC function will track i2s clock and generate a corresponding system clock
952 * for codec. This function provides an API to select the clock source for a
953 * set of filters specified by the mask. And the codec driver will turn on ASRC
954 * for these filters if ASRC is selected as their clock source.
955 */
rt5645_sel_asrc_clk_src(struct snd_soc_component * component,unsigned int filter_mask,unsigned int clk_src)956 int rt5645_sel_asrc_clk_src(struct snd_soc_component *component,
957 unsigned int filter_mask, unsigned int clk_src)
958 {
959 unsigned int asrc2_mask = 0;
960 unsigned int asrc2_value = 0;
961 unsigned int asrc3_mask = 0;
962 unsigned int asrc3_value = 0;
963
964 switch (clk_src) {
965 case RT5645_CLK_SEL_SYS:
966 case RT5645_CLK_SEL_I2S1_ASRC:
967 case RT5645_CLK_SEL_I2S2_ASRC:
968 case RT5645_CLK_SEL_SYS2:
969 break;
970
971 default:
972 return -EINVAL;
973 }
974
975 if (filter_mask & RT5645_DA_STEREO_FILTER) {
976 asrc2_mask |= RT5645_DA_STO_CLK_SEL_MASK;
977 asrc2_value = (asrc2_value & ~RT5645_DA_STO_CLK_SEL_MASK)
978 | (clk_src << RT5645_DA_STO_CLK_SEL_SFT);
979 }
980
981 if (filter_mask & RT5645_DA_MONO_L_FILTER) {
982 asrc2_mask |= RT5645_DA_MONOL_CLK_SEL_MASK;
983 asrc2_value = (asrc2_value & ~RT5645_DA_MONOL_CLK_SEL_MASK)
984 | (clk_src << RT5645_DA_MONOL_CLK_SEL_SFT);
985 }
986
987 if (filter_mask & RT5645_DA_MONO_R_FILTER) {
988 asrc2_mask |= RT5645_DA_MONOR_CLK_SEL_MASK;
989 asrc2_value = (asrc2_value & ~RT5645_DA_MONOR_CLK_SEL_MASK)
990 | (clk_src << RT5645_DA_MONOR_CLK_SEL_SFT);
991 }
992
993 if (filter_mask & RT5645_AD_STEREO_FILTER) {
994 asrc2_mask |= RT5645_AD_STO1_CLK_SEL_MASK;
995 asrc2_value = (asrc2_value & ~RT5645_AD_STO1_CLK_SEL_MASK)
996 | (clk_src << RT5645_AD_STO1_CLK_SEL_SFT);
997 }
998
999 if (filter_mask & RT5645_AD_MONO_L_FILTER) {
1000 asrc3_mask |= RT5645_AD_MONOL_CLK_SEL_MASK;
1001 asrc3_value = (asrc3_value & ~RT5645_AD_MONOL_CLK_SEL_MASK)
1002 | (clk_src << RT5645_AD_MONOL_CLK_SEL_SFT);
1003 }
1004
1005 if (filter_mask & RT5645_AD_MONO_R_FILTER) {
1006 asrc3_mask |= RT5645_AD_MONOR_CLK_SEL_MASK;
1007 asrc3_value = (asrc3_value & ~RT5645_AD_MONOR_CLK_SEL_MASK)
1008 | (clk_src << RT5645_AD_MONOR_CLK_SEL_SFT);
1009 }
1010
1011 if (asrc2_mask)
1012 snd_soc_component_update_bits(component, RT5645_ASRC_2,
1013 asrc2_mask, asrc2_value);
1014
1015 if (asrc3_mask)
1016 snd_soc_component_update_bits(component, RT5645_ASRC_3,
1017 asrc3_mask, asrc3_value);
1018
1019 return 0;
1020 }
1021 EXPORT_SYMBOL_GPL(rt5645_sel_asrc_clk_src);
1022
1023 /* Digital Mixer */
1024 static const struct snd_kcontrol_new rt5645_sto1_adc_l_mix[] = {
1025 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1026 RT5645_M_ADC_L1_SFT, 1, 1),
1027 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1028 RT5645_M_ADC_L2_SFT, 1, 1),
1029 };
1030
1031 static const struct snd_kcontrol_new rt5645_sto1_adc_r_mix[] = {
1032 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_STO1_ADC_MIXER,
1033 RT5645_M_ADC_R1_SFT, 1, 1),
1034 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_STO1_ADC_MIXER,
1035 RT5645_M_ADC_R2_SFT, 1, 1),
1036 };
1037
1038 static const struct snd_kcontrol_new rt5645_mono_adc_l_mix[] = {
1039 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1040 RT5645_M_MONO_ADC_L1_SFT, 1, 1),
1041 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1042 RT5645_M_MONO_ADC_L2_SFT, 1, 1),
1043 };
1044
1045 static const struct snd_kcontrol_new rt5645_mono_adc_r_mix[] = {
1046 SOC_DAPM_SINGLE("ADC1 Switch", RT5645_MONO_ADC_MIXER,
1047 RT5645_M_MONO_ADC_R1_SFT, 1, 1),
1048 SOC_DAPM_SINGLE("ADC2 Switch", RT5645_MONO_ADC_MIXER,
1049 RT5645_M_MONO_ADC_R2_SFT, 1, 1),
1050 };
1051
1052 static const struct snd_kcontrol_new rt5645_dac_l_mix[] = {
1053 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1054 RT5645_M_ADCMIX_L_SFT, 1, 1),
1055 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1056 RT5645_M_DAC1_L_SFT, 1, 1),
1057 };
1058
1059 static const struct snd_kcontrol_new rt5645_dac_r_mix[] = {
1060 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5645_AD_DA_MIXER,
1061 RT5645_M_ADCMIX_R_SFT, 1, 1),
1062 SOC_DAPM_SINGLE_AUTODISABLE("DAC1 Switch", RT5645_AD_DA_MIXER,
1063 RT5645_M_DAC1_R_SFT, 1, 1),
1064 };
1065
1066 static const struct snd_kcontrol_new rt5645_sto_dac_l_mix[] = {
1067 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1068 RT5645_M_DAC_L1_SFT, 1, 1),
1069 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_STO_DAC_MIXER,
1070 RT5645_M_DAC_L2_SFT, 1, 1),
1071 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1072 RT5645_M_DAC_R1_STO_L_SFT, 1, 1),
1073 };
1074
1075 static const struct snd_kcontrol_new rt5645_sto_dac_r_mix[] = {
1076 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_STO_DAC_MIXER,
1077 RT5645_M_DAC_R1_SFT, 1, 1),
1078 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
1079 RT5645_M_DAC_R2_SFT, 1, 1),
1080 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_STO_DAC_MIXER,
1081 RT5645_M_DAC_L1_STO_R_SFT, 1, 1),
1082 };
1083
1084 static const struct snd_kcontrol_new rt5645_mono_dac_l_mix[] = {
1085 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_MONO_DAC_MIXER,
1086 RT5645_M_DAC_L1_MONO_L_SFT, 1, 1),
1087 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1088 RT5645_M_DAC_L2_MONO_L_SFT, 1, 1),
1089 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1090 RT5645_M_DAC_R2_MONO_L_SFT, 1, 1),
1091 };
1092
1093 static const struct snd_kcontrol_new rt5645_mono_dac_r_mix[] = {
1094 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_MONO_DAC_MIXER,
1095 RT5645_M_DAC_R1_MONO_R_SFT, 1, 1),
1096 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
1097 RT5645_M_DAC_R2_MONO_R_SFT, 1, 1),
1098 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_MONO_DAC_MIXER,
1099 RT5645_M_DAC_L2_MONO_R_SFT, 1, 1),
1100 };
1101
1102 static const struct snd_kcontrol_new rt5645_dig_l_mix[] = {
1103 SOC_DAPM_SINGLE("Sto DAC Mix L Switch", RT5645_DIG_MIXER,
1104 RT5645_M_STO_L_DAC_L_SFT, 1, 1),
1105 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1106 RT5645_M_DAC_L2_DAC_L_SFT, 1, 1),
1107 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1108 RT5645_M_DAC_R2_DAC_L_SFT, 1, 1),
1109 };
1110
1111 static const struct snd_kcontrol_new rt5645_dig_r_mix[] = {
1112 SOC_DAPM_SINGLE("Sto DAC Mix R Switch", RT5645_DIG_MIXER,
1113 RT5645_M_STO_R_DAC_R_SFT, 1, 1),
1114 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
1115 RT5645_M_DAC_R2_DAC_R_SFT, 1, 1),
1116 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_DIG_MIXER,
1117 RT5645_M_DAC_L2_DAC_R_SFT, 1, 1),
1118 };
1119
1120 /* Analog Input Mixer */
1121 static const struct snd_kcontrol_new rt5645_rec_l_mix[] = {
1122 SOC_DAPM_SINGLE("HPOL Switch", RT5645_REC_L2_MIXER,
1123 RT5645_M_HP_L_RM_L_SFT, 1, 1),
1124 SOC_DAPM_SINGLE("INL Switch", RT5645_REC_L2_MIXER,
1125 RT5645_M_IN_L_RM_L_SFT, 1, 1),
1126 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_L2_MIXER,
1127 RT5645_M_BST2_RM_L_SFT, 1, 1),
1128 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_L2_MIXER,
1129 RT5645_M_BST1_RM_L_SFT, 1, 1),
1130 SOC_DAPM_SINGLE("OUT MIXL Switch", RT5645_REC_L2_MIXER,
1131 RT5645_M_OM_L_RM_L_SFT, 1, 1),
1132 };
1133
1134 static const struct snd_kcontrol_new rt5645_rec_r_mix[] = {
1135 SOC_DAPM_SINGLE("HPOR Switch", RT5645_REC_R2_MIXER,
1136 RT5645_M_HP_R_RM_R_SFT, 1, 1),
1137 SOC_DAPM_SINGLE("INR Switch", RT5645_REC_R2_MIXER,
1138 RT5645_M_IN_R_RM_R_SFT, 1, 1),
1139 SOC_DAPM_SINGLE("BST2 Switch", RT5645_REC_R2_MIXER,
1140 RT5645_M_BST2_RM_R_SFT, 1, 1),
1141 SOC_DAPM_SINGLE("BST1 Switch", RT5645_REC_R2_MIXER,
1142 RT5645_M_BST1_RM_R_SFT, 1, 1),
1143 SOC_DAPM_SINGLE("OUT MIXR Switch", RT5645_REC_R2_MIXER,
1144 RT5645_M_OM_R_RM_R_SFT, 1, 1),
1145 };
1146
1147 static const struct snd_kcontrol_new rt5645_spk_l_mix[] = {
1148 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPK_L_MIXER,
1149 RT5645_M_DAC_L1_SM_L_SFT, 1, 1),
1150 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_SPK_L_MIXER,
1151 RT5645_M_DAC_L2_SM_L_SFT, 1, 1),
1152 SOC_DAPM_SINGLE("INL Switch", RT5645_SPK_L_MIXER,
1153 RT5645_M_IN_L_SM_L_SFT, 1, 1),
1154 SOC_DAPM_SINGLE("BST1 Switch", RT5645_SPK_L_MIXER,
1155 RT5645_M_BST1_L_SM_L_SFT, 1, 1),
1156 };
1157
1158 static const struct snd_kcontrol_new rt5645_spk_r_mix[] = {
1159 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPK_R_MIXER,
1160 RT5645_M_DAC_R1_SM_R_SFT, 1, 1),
1161 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
1162 RT5645_M_DAC_R2_SM_R_SFT, 1, 1),
1163 SOC_DAPM_SINGLE("INR Switch", RT5645_SPK_R_MIXER,
1164 RT5645_M_IN_R_SM_R_SFT, 1, 1),
1165 SOC_DAPM_SINGLE("BST2 Switch", RT5645_SPK_R_MIXER,
1166 RT5645_M_BST2_R_SM_R_SFT, 1, 1),
1167 };
1168
1169 static const struct snd_kcontrol_new rt5645_out_l_mix[] = {
1170 SOC_DAPM_SINGLE("BST1 Switch", RT5645_OUT_L1_MIXER,
1171 RT5645_M_BST1_OM_L_SFT, 1, 1),
1172 SOC_DAPM_SINGLE("INL Switch", RT5645_OUT_L1_MIXER,
1173 RT5645_M_IN_L_OM_L_SFT, 1, 1),
1174 SOC_DAPM_SINGLE("DAC L2 Switch", RT5645_OUT_L1_MIXER,
1175 RT5645_M_DAC_L2_OM_L_SFT, 1, 1),
1176 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_OUT_L1_MIXER,
1177 RT5645_M_DAC_L1_OM_L_SFT, 1, 1),
1178 };
1179
1180 static const struct snd_kcontrol_new rt5645_out_r_mix[] = {
1181 SOC_DAPM_SINGLE("BST2 Switch", RT5645_OUT_R1_MIXER,
1182 RT5645_M_BST2_OM_R_SFT, 1, 1),
1183 SOC_DAPM_SINGLE("INR Switch", RT5645_OUT_R1_MIXER,
1184 RT5645_M_IN_R_OM_R_SFT, 1, 1),
1185 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
1186 RT5645_M_DAC_R2_OM_R_SFT, 1, 1),
1187 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_OUT_R1_MIXER,
1188 RT5645_M_DAC_R1_OM_R_SFT, 1, 1),
1189 };
1190
1191 static const struct snd_kcontrol_new rt5645_spo_l_mix[] = {
1192 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1193 RT5645_M_DAC_R1_SPM_L_SFT, 1, 1),
1194 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_SPO_MIXER,
1195 RT5645_M_DAC_L1_SPM_L_SFT, 1, 1),
1196 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1197 RT5645_M_SV_R_SPM_L_SFT, 1, 1),
1198 SOC_DAPM_SINGLE("SPKVOL L Switch", RT5645_SPO_MIXER,
1199 RT5645_M_SV_L_SPM_L_SFT, 1, 1),
1200 };
1201
1202 static const struct snd_kcontrol_new rt5645_spo_r_mix[] = {
1203 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_SPO_MIXER,
1204 RT5645_M_DAC_R1_SPM_R_SFT, 1, 1),
1205 SOC_DAPM_SINGLE("SPKVOL R Switch", RT5645_SPO_MIXER,
1206 RT5645_M_SV_R_SPM_R_SFT, 1, 1),
1207 };
1208
1209 static const struct snd_kcontrol_new rt5645_hpo_mix[] = {
1210 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPO_MIXER,
1211 RT5645_M_DAC1_HM_SFT, 1, 1),
1212 SOC_DAPM_SINGLE("HPVOL Switch", RT5645_HPO_MIXER,
1213 RT5645_M_HPVOL_HM_SFT, 1, 1),
1214 };
1215
1216 static const struct snd_kcontrol_new rt5645_hpvoll_mix[] = {
1217 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXL_CTRL,
1218 RT5645_M_DAC1_HV_SFT, 1, 1),
1219 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXL_CTRL,
1220 RT5645_M_DAC2_HV_SFT, 1, 1),
1221 SOC_DAPM_SINGLE("INL Switch", RT5645_HPOMIXL_CTRL,
1222 RT5645_M_IN_HV_SFT, 1, 1),
1223 SOC_DAPM_SINGLE("BST1 Switch", RT5645_HPOMIXL_CTRL,
1224 RT5645_M_BST1_HV_SFT, 1, 1),
1225 };
1226
1227 static const struct snd_kcontrol_new rt5645_hpvolr_mix[] = {
1228 SOC_DAPM_SINGLE("DAC1 Switch", RT5645_HPOMIXR_CTRL,
1229 RT5645_M_DAC1_HV_SFT, 1, 1),
1230 SOC_DAPM_SINGLE("DAC2 Switch", RT5645_HPOMIXR_CTRL,
1231 RT5645_M_DAC2_HV_SFT, 1, 1),
1232 SOC_DAPM_SINGLE("INR Switch", RT5645_HPOMIXR_CTRL,
1233 RT5645_M_IN_HV_SFT, 1, 1),
1234 SOC_DAPM_SINGLE("BST2 Switch", RT5645_HPOMIXR_CTRL,
1235 RT5645_M_BST2_HV_SFT, 1, 1),
1236 };
1237
1238 static const struct snd_kcontrol_new rt5645_lout_mix[] = {
1239 SOC_DAPM_SINGLE("DAC L1 Switch", RT5645_LOUT_MIXER,
1240 RT5645_M_DAC_L1_LM_SFT, 1, 1),
1241 SOC_DAPM_SINGLE("DAC R1 Switch", RT5645_LOUT_MIXER,
1242 RT5645_M_DAC_R1_LM_SFT, 1, 1),
1243 SOC_DAPM_SINGLE("OUTMIX L Switch", RT5645_LOUT_MIXER,
1244 RT5645_M_OV_L_LM_SFT, 1, 1),
1245 SOC_DAPM_SINGLE("OUTMIX R Switch", RT5645_LOUT_MIXER,
1246 RT5645_M_OV_R_LM_SFT, 1, 1),
1247 };
1248
1249 /*DAC1 L/R source*/ /* MX-29 [9:8] [11:10] */
1250 static const char * const rt5645_dac1_src[] = {
1251 "IF1 DAC", "IF2 DAC", "IF3 DAC"
1252 };
1253
1254 static SOC_ENUM_SINGLE_DECL(
1255 rt5645_dac1l_enum, RT5645_AD_DA_MIXER,
1256 RT5645_DAC1_L_SEL_SFT, rt5645_dac1_src);
1257
1258 static const struct snd_kcontrol_new rt5645_dac1l_mux =
1259 SOC_DAPM_ENUM("DAC1 L source", rt5645_dac1l_enum);
1260
1261 static SOC_ENUM_SINGLE_DECL(
1262 rt5645_dac1r_enum, RT5645_AD_DA_MIXER,
1263 RT5645_DAC1_R_SEL_SFT, rt5645_dac1_src);
1264
1265 static const struct snd_kcontrol_new rt5645_dac1r_mux =
1266 SOC_DAPM_ENUM("DAC1 R source", rt5645_dac1r_enum);
1267
1268 /*DAC2 L/R source*/ /* MX-1B [6:4] [2:0] */
1269 static const char * const rt5645_dac12_src[] = {
1270 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "VAD_ADC"
1271 };
1272
1273 static SOC_ENUM_SINGLE_DECL(
1274 rt5645_dac2l_enum, RT5645_DAC_CTRL,
1275 RT5645_DAC2_L_SEL_SFT, rt5645_dac12_src);
1276
1277 static const struct snd_kcontrol_new rt5645_dac_l2_mux =
1278 SOC_DAPM_ENUM("DAC2 L source", rt5645_dac2l_enum);
1279
1280 static const char * const rt5645_dacr2_src[] = {
1281 "IF1 DAC", "IF2 DAC", "IF3 DAC", "Mono ADC", "Haptic"
1282 };
1283
1284 static SOC_ENUM_SINGLE_DECL(
1285 rt5645_dac2r_enum, RT5645_DAC_CTRL,
1286 RT5645_DAC2_R_SEL_SFT, rt5645_dacr2_src);
1287
1288 static const struct snd_kcontrol_new rt5645_dac_r2_mux =
1289 SOC_DAPM_ENUM("DAC2 R source", rt5645_dac2r_enum);
1290
1291 /* Stereo1 ADC source */
1292 /* MX-27 [12] */
1293 static const char * const rt5645_stereo_adc1_src[] = {
1294 "DAC MIX", "ADC"
1295 };
1296
1297 static SOC_ENUM_SINGLE_DECL(
1298 rt5645_stereo1_adc1_enum, RT5645_STO1_ADC_MIXER,
1299 RT5645_ADC_1_SRC_SFT, rt5645_stereo_adc1_src);
1300
1301 static const struct snd_kcontrol_new rt5645_sto_adc1_mux =
1302 SOC_DAPM_ENUM("Stereo1 ADC1 Mux", rt5645_stereo1_adc1_enum);
1303
1304 /* MX-27 [11] */
1305 static const char * const rt5645_stereo_adc2_src[] = {
1306 "DAC MIX", "DMIC"
1307 };
1308
1309 static SOC_ENUM_SINGLE_DECL(
1310 rt5645_stereo1_adc2_enum, RT5645_STO1_ADC_MIXER,
1311 RT5645_ADC_2_SRC_SFT, rt5645_stereo_adc2_src);
1312
1313 static const struct snd_kcontrol_new rt5645_sto_adc2_mux =
1314 SOC_DAPM_ENUM("Stereo1 ADC2 Mux", rt5645_stereo1_adc2_enum);
1315
1316 /* MX-27 [8] */
1317 static const char * const rt5645_stereo_dmic_src[] = {
1318 "DMIC1", "DMIC2"
1319 };
1320
1321 static SOC_ENUM_SINGLE_DECL(
1322 rt5645_stereo1_dmic_enum, RT5645_STO1_ADC_MIXER,
1323 RT5645_DMIC_SRC_SFT, rt5645_stereo_dmic_src);
1324
1325 static const struct snd_kcontrol_new rt5645_sto1_dmic_mux =
1326 SOC_DAPM_ENUM("Stereo1 DMIC source", rt5645_stereo1_dmic_enum);
1327
1328 /* Mono ADC source */
1329 /* MX-28 [12] */
1330 static const char * const rt5645_mono_adc_l1_src[] = {
1331 "Mono DAC MIXL", "ADC"
1332 };
1333
1334 static SOC_ENUM_SINGLE_DECL(
1335 rt5645_mono_adc_l1_enum, RT5645_MONO_ADC_MIXER,
1336 RT5645_MONO_ADC_L1_SRC_SFT, rt5645_mono_adc_l1_src);
1337
1338 static const struct snd_kcontrol_new rt5645_mono_adc_l1_mux =
1339 SOC_DAPM_ENUM("Mono ADC1 left source", rt5645_mono_adc_l1_enum);
1340 /* MX-28 [11] */
1341 static const char * const rt5645_mono_adc_l2_src[] = {
1342 "Mono DAC MIXL", "DMIC"
1343 };
1344
1345 static SOC_ENUM_SINGLE_DECL(
1346 rt5645_mono_adc_l2_enum, RT5645_MONO_ADC_MIXER,
1347 RT5645_MONO_ADC_L2_SRC_SFT, rt5645_mono_adc_l2_src);
1348
1349 static const struct snd_kcontrol_new rt5645_mono_adc_l2_mux =
1350 SOC_DAPM_ENUM("Mono ADC2 left source", rt5645_mono_adc_l2_enum);
1351
1352 /* MX-28 [8] */
1353 static const char * const rt5645_mono_dmic_src[] = {
1354 "DMIC1", "DMIC2"
1355 };
1356
1357 static SOC_ENUM_SINGLE_DECL(
1358 rt5645_mono_dmic_l_enum, RT5645_MONO_ADC_MIXER,
1359 RT5645_MONO_DMIC_L_SRC_SFT, rt5645_mono_dmic_src);
1360
1361 static const struct snd_kcontrol_new rt5645_mono_dmic_l_mux =
1362 SOC_DAPM_ENUM("Mono DMIC left source", rt5645_mono_dmic_l_enum);
1363 /* MX-28 [1:0] */
1364 static SOC_ENUM_SINGLE_DECL(
1365 rt5645_mono_dmic_r_enum, RT5645_MONO_ADC_MIXER,
1366 RT5645_MONO_DMIC_R_SRC_SFT, rt5645_mono_dmic_src);
1367
1368 static const struct snd_kcontrol_new rt5645_mono_dmic_r_mux =
1369 SOC_DAPM_ENUM("Mono DMIC Right source", rt5645_mono_dmic_r_enum);
1370 /* MX-28 [4] */
1371 static const char * const rt5645_mono_adc_r1_src[] = {
1372 "Mono DAC MIXR", "ADC"
1373 };
1374
1375 static SOC_ENUM_SINGLE_DECL(
1376 rt5645_mono_adc_r1_enum, RT5645_MONO_ADC_MIXER,
1377 RT5645_MONO_ADC_R1_SRC_SFT, rt5645_mono_adc_r1_src);
1378
1379 static const struct snd_kcontrol_new rt5645_mono_adc_r1_mux =
1380 SOC_DAPM_ENUM("Mono ADC1 right source", rt5645_mono_adc_r1_enum);
1381 /* MX-28 [3] */
1382 static const char * const rt5645_mono_adc_r2_src[] = {
1383 "Mono DAC MIXR", "DMIC"
1384 };
1385
1386 static SOC_ENUM_SINGLE_DECL(
1387 rt5645_mono_adc_r2_enum, RT5645_MONO_ADC_MIXER,
1388 RT5645_MONO_ADC_R2_SRC_SFT, rt5645_mono_adc_r2_src);
1389
1390 static const struct snd_kcontrol_new rt5645_mono_adc_r2_mux =
1391 SOC_DAPM_ENUM("Mono ADC2 right source", rt5645_mono_adc_r2_enum);
1392
1393 /* MX-77 [9:8] */
1394 static const char * const rt5645_if1_adc_in_src[] = {
1395 "IF_ADC1/IF_ADC2/VAD_ADC", "IF_ADC2/IF_ADC1/VAD_ADC",
1396 "VAD_ADC/IF_ADC1/IF_ADC2", "VAD_ADC/IF_ADC2/IF_ADC1"
1397 };
1398
1399 static SOC_ENUM_SINGLE_DECL(
1400 rt5645_if1_adc_in_enum, RT5645_TDM_CTRL_1,
1401 RT5645_IF1_ADC_IN_SFT, rt5645_if1_adc_in_src);
1402
1403 static const struct snd_kcontrol_new rt5645_if1_adc_in_mux =
1404 SOC_DAPM_ENUM("IF1 ADC IN source", rt5645_if1_adc_in_enum);
1405
1406 /* MX-78 [4:0] */
1407 static const char * const rt5650_if1_adc_in_src[] = {
1408 "IF_ADC1/IF_ADC2/DAC_REF/Null",
1409 "IF_ADC1/IF_ADC2/Null/DAC_REF",
1410 "IF_ADC1/DAC_REF/IF_ADC2/Null",
1411 "IF_ADC1/DAC_REF/Null/IF_ADC2",
1412 "IF_ADC1/Null/DAC_REF/IF_ADC2",
1413 "IF_ADC1/Null/IF_ADC2/DAC_REF",
1414
1415 "IF_ADC2/IF_ADC1/DAC_REF/Null",
1416 "IF_ADC2/IF_ADC1/Null/DAC_REF",
1417 "IF_ADC2/DAC_REF/IF_ADC1/Null",
1418 "IF_ADC2/DAC_REF/Null/IF_ADC1",
1419 "IF_ADC2/Null/DAC_REF/IF_ADC1",
1420 "IF_ADC2/Null/IF_ADC1/DAC_REF",
1421
1422 "DAC_REF/IF_ADC1/IF_ADC2/Null",
1423 "DAC_REF/IF_ADC1/Null/IF_ADC2",
1424 "DAC_REF/IF_ADC2/IF_ADC1/Null",
1425 "DAC_REF/IF_ADC2/Null/IF_ADC1",
1426 "DAC_REF/Null/IF_ADC1/IF_ADC2",
1427 "DAC_REF/Null/IF_ADC2/IF_ADC1",
1428
1429 "Null/IF_ADC1/IF_ADC2/DAC_REF",
1430 "Null/IF_ADC1/DAC_REF/IF_ADC2",
1431 "Null/IF_ADC2/IF_ADC1/DAC_REF",
1432 "Null/IF_ADC2/DAC_REF/IF_ADC1",
1433 "Null/DAC_REF/IF_ADC1/IF_ADC2",
1434 "Null/DAC_REF/IF_ADC2/IF_ADC1",
1435 };
1436
1437 static SOC_ENUM_SINGLE_DECL(
1438 rt5650_if1_adc_in_enum, RT5645_TDM_CTRL_2,
1439 0, rt5650_if1_adc_in_src);
1440
1441 static const struct snd_kcontrol_new rt5650_if1_adc_in_mux =
1442 SOC_DAPM_ENUM("IF1 ADC IN source", rt5650_if1_adc_in_enum);
1443
1444 /* MX-78 [15:14][13:12][11:10] */
1445 static const char * const rt5645_tdm_adc_swap_select[] = {
1446 "L/R", "R/L", "L/L", "R/R"
1447 };
1448
1449 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot0_1_enum,
1450 RT5645_TDM_CTRL_2, 14, rt5645_tdm_adc_swap_select);
1451
1452 static const struct snd_kcontrol_new rt5650_if1_adc1_in_mux =
1453 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5650_tdm_adc_slot0_1_enum);
1454
1455 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot2_3_enum,
1456 RT5645_TDM_CTRL_2, 12, rt5645_tdm_adc_swap_select);
1457
1458 static const struct snd_kcontrol_new rt5650_if1_adc2_in_mux =
1459 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5650_tdm_adc_slot2_3_enum);
1460
1461 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_adc_slot4_5_enum,
1462 RT5645_TDM_CTRL_2, 10, rt5645_tdm_adc_swap_select);
1463
1464 static const struct snd_kcontrol_new rt5650_if1_adc3_in_mux =
1465 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5650_tdm_adc_slot4_5_enum);
1466
1467 /* MX-77 [7:6][5:4][3:2] */
1468 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot0_1_enum,
1469 RT5645_TDM_CTRL_1, 6, rt5645_tdm_adc_swap_select);
1470
1471 static const struct snd_kcontrol_new rt5645_if1_adc1_in_mux =
1472 SOC_DAPM_ENUM("IF1 ADC1 IN source", rt5645_tdm_adc_slot0_1_enum);
1473
1474 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot2_3_enum,
1475 RT5645_TDM_CTRL_1, 4, rt5645_tdm_adc_swap_select);
1476
1477 static const struct snd_kcontrol_new rt5645_if1_adc2_in_mux =
1478 SOC_DAPM_ENUM("IF1 ADC2 IN source", rt5645_tdm_adc_slot2_3_enum);
1479
1480 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_adc_slot4_5_enum,
1481 RT5645_TDM_CTRL_1, 2, rt5645_tdm_adc_swap_select);
1482
1483 static const struct snd_kcontrol_new rt5645_if1_adc3_in_mux =
1484 SOC_DAPM_ENUM("IF1 ADC3 IN source", rt5645_tdm_adc_slot4_5_enum);
1485
1486 /* MX-79 [14:12][10:8][6:4][2:0] */
1487 static const char * const rt5645_tdm_dac_swap_select[] = {
1488 "Slot0", "Slot1", "Slot2", "Slot3"
1489 };
1490
1491 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac0_enum,
1492 RT5645_TDM_CTRL_3, 12, rt5645_tdm_dac_swap_select);
1493
1494 static const struct snd_kcontrol_new rt5645_if1_dac0_tdm_sel_mux =
1495 SOC_DAPM_ENUM("IF1 DAC0 source", rt5645_tdm_dac0_enum);
1496
1497 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac1_enum,
1498 RT5645_TDM_CTRL_3, 8, rt5645_tdm_dac_swap_select);
1499
1500 static const struct snd_kcontrol_new rt5645_if1_dac1_tdm_sel_mux =
1501 SOC_DAPM_ENUM("IF1 DAC1 source", rt5645_tdm_dac1_enum);
1502
1503 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac2_enum,
1504 RT5645_TDM_CTRL_3, 4, rt5645_tdm_dac_swap_select);
1505
1506 static const struct snd_kcontrol_new rt5645_if1_dac2_tdm_sel_mux =
1507 SOC_DAPM_ENUM("IF1 DAC2 source", rt5645_tdm_dac2_enum);
1508
1509 static SOC_ENUM_SINGLE_DECL(rt5645_tdm_dac3_enum,
1510 RT5645_TDM_CTRL_3, 0, rt5645_tdm_dac_swap_select);
1511
1512 static const struct snd_kcontrol_new rt5645_if1_dac3_tdm_sel_mux =
1513 SOC_DAPM_ENUM("IF1 DAC3 source", rt5645_tdm_dac3_enum);
1514
1515 /* MX-7a [14:12][10:8][6:4][2:0] */
1516 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac0_enum,
1517 RT5650_TDM_CTRL_4, 12, rt5645_tdm_dac_swap_select);
1518
1519 static const struct snd_kcontrol_new rt5650_if1_dac0_tdm_sel_mux =
1520 SOC_DAPM_ENUM("IF1 DAC0 source", rt5650_tdm_dac0_enum);
1521
1522 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac1_enum,
1523 RT5650_TDM_CTRL_4, 8, rt5645_tdm_dac_swap_select);
1524
1525 static const struct snd_kcontrol_new rt5650_if1_dac1_tdm_sel_mux =
1526 SOC_DAPM_ENUM("IF1 DAC1 source", rt5650_tdm_dac1_enum);
1527
1528 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac2_enum,
1529 RT5650_TDM_CTRL_4, 4, rt5645_tdm_dac_swap_select);
1530
1531 static const struct snd_kcontrol_new rt5650_if1_dac2_tdm_sel_mux =
1532 SOC_DAPM_ENUM("IF1 DAC2 source", rt5650_tdm_dac2_enum);
1533
1534 static SOC_ENUM_SINGLE_DECL(rt5650_tdm_dac3_enum,
1535 RT5650_TDM_CTRL_4, 0, rt5645_tdm_dac_swap_select);
1536
1537 static const struct snd_kcontrol_new rt5650_if1_dac3_tdm_sel_mux =
1538 SOC_DAPM_ENUM("IF1 DAC3 source", rt5650_tdm_dac3_enum);
1539
1540 /* MX-2d [3] [2] */
1541 static const char * const rt5650_a_dac1_src[] = {
1542 "DAC1", "Stereo DAC Mixer"
1543 };
1544
1545 static SOC_ENUM_SINGLE_DECL(
1546 rt5650_a_dac1_l_enum, RT5650_A_DAC_SOUR,
1547 RT5650_A_DAC1_L_IN_SFT, rt5650_a_dac1_src);
1548
1549 static const struct snd_kcontrol_new rt5650_a_dac1_l_mux =
1550 SOC_DAPM_ENUM("A DAC1 L source", rt5650_a_dac1_l_enum);
1551
1552 static SOC_ENUM_SINGLE_DECL(
1553 rt5650_a_dac1_r_enum, RT5650_A_DAC_SOUR,
1554 RT5650_A_DAC1_R_IN_SFT, rt5650_a_dac1_src);
1555
1556 static const struct snd_kcontrol_new rt5650_a_dac1_r_mux =
1557 SOC_DAPM_ENUM("A DAC1 R source", rt5650_a_dac1_r_enum);
1558
1559 /* MX-2d [1] [0] */
1560 static const char * const rt5650_a_dac2_src[] = {
1561 "Stereo DAC Mixer", "Mono DAC Mixer"
1562 };
1563
1564 static SOC_ENUM_SINGLE_DECL(
1565 rt5650_a_dac2_l_enum, RT5650_A_DAC_SOUR,
1566 RT5650_A_DAC2_L_IN_SFT, rt5650_a_dac2_src);
1567
1568 static const struct snd_kcontrol_new rt5650_a_dac2_l_mux =
1569 SOC_DAPM_ENUM("A DAC2 L source", rt5650_a_dac2_l_enum);
1570
1571 static SOC_ENUM_SINGLE_DECL(
1572 rt5650_a_dac2_r_enum, RT5650_A_DAC_SOUR,
1573 RT5650_A_DAC2_R_IN_SFT, rt5650_a_dac2_src);
1574
1575 static const struct snd_kcontrol_new rt5650_a_dac2_r_mux =
1576 SOC_DAPM_ENUM("A DAC2 R source", rt5650_a_dac2_r_enum);
1577
1578 /* MX-2F [13:12] */
1579 static const char * const rt5645_if2_adc_in_src[] = {
1580 "IF_ADC1", "IF_ADC2", "VAD_ADC"
1581 };
1582
1583 static SOC_ENUM_SINGLE_DECL(
1584 rt5645_if2_adc_in_enum, RT5645_DIG_INF1_DATA,
1585 RT5645_IF2_ADC_IN_SFT, rt5645_if2_adc_in_src);
1586
1587 static const struct snd_kcontrol_new rt5645_if2_adc_in_mux =
1588 SOC_DAPM_ENUM("IF2 ADC IN source", rt5645_if2_adc_in_enum);
1589
1590 /* MX-31 [15] [13] [11] [9] */
1591 static const char * const rt5645_pdm_src[] = {
1592 "Mono DAC", "Stereo DAC"
1593 };
1594
1595 static SOC_ENUM_SINGLE_DECL(
1596 rt5645_pdm1_l_enum, RT5645_PDM_OUT_CTRL,
1597 RT5645_PDM1_L_SFT, rt5645_pdm_src);
1598
1599 static const struct snd_kcontrol_new rt5645_pdm1_l_mux =
1600 SOC_DAPM_ENUM("PDM1 L source", rt5645_pdm1_l_enum);
1601
1602 static SOC_ENUM_SINGLE_DECL(
1603 rt5645_pdm1_r_enum, RT5645_PDM_OUT_CTRL,
1604 RT5645_PDM1_R_SFT, rt5645_pdm_src);
1605
1606 static const struct snd_kcontrol_new rt5645_pdm1_r_mux =
1607 SOC_DAPM_ENUM("PDM1 R source", rt5645_pdm1_r_enum);
1608
1609 /* MX-9D [9:8] */
1610 static const char * const rt5645_vad_adc_src[] = {
1611 "Sto1 ADC L", "Mono ADC L", "Mono ADC R"
1612 };
1613
1614 static SOC_ENUM_SINGLE_DECL(
1615 rt5645_vad_adc_enum, RT5645_VAD_CTRL4,
1616 RT5645_VAD_SEL_SFT, rt5645_vad_adc_src);
1617
1618 static const struct snd_kcontrol_new rt5645_vad_adc_mux =
1619 SOC_DAPM_ENUM("VAD ADC source", rt5645_vad_adc_enum);
1620
1621 static const struct snd_kcontrol_new spk_l_vol_control =
1622 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1623 RT5645_L_MUTE_SFT, 1, 1);
1624
1625 static const struct snd_kcontrol_new spk_r_vol_control =
1626 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_SPK_VOL,
1627 RT5645_R_MUTE_SFT, 1, 1);
1628
1629 static const struct snd_kcontrol_new hp_l_vol_control =
1630 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1631 RT5645_L_MUTE_SFT, 1, 1);
1632
1633 static const struct snd_kcontrol_new hp_r_vol_control =
1634 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_HP_VOL,
1635 RT5645_R_MUTE_SFT, 1, 1);
1636
1637 static const struct snd_kcontrol_new pdm1_l_vol_control =
1638 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1639 RT5645_M_PDM1_L, 1, 1);
1640
1641 static const struct snd_kcontrol_new pdm1_r_vol_control =
1642 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5645_PDM_OUT_CTRL,
1643 RT5645_M_PDM1_R, 1, 1);
1644
hp_amp_power(struct snd_soc_component * component,int on)1645 static void hp_amp_power(struct snd_soc_component *component, int on)
1646 {
1647 static int hp_amp_power_count;
1648 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
1649
1650 if (on) {
1651 if (hp_amp_power_count <= 0) {
1652 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1653 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x3100);
1654 snd_soc_component_write(component, RT5645_CHARGE_PUMP,
1655 0x0e06);
1656 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);
1657 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1658 RT5645_HP_DCC_INT1, 0x9f01);
1659 msleep(20);
1660 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1661 RT5645_HP_CO_MASK, RT5645_HP_CO_EN);
1662 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1663 0x3e, 0x7400);
1664 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);
1665 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1666 RT5645_MAMP_INT_REG2, 0xfc00);
1667 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
1668 msleep(90);
1669 rt5645->hp_on = true;
1670 } else {
1671 /* depop parameters */
1672 snd_soc_component_update_bits(component, RT5645_DEPOP_M2,
1673 RT5645_DEPOP_MASK, RT5645_DEPOP_MAN);
1674 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x000d);
1675 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1676 RT5645_HP_DCC_INT1, 0x9f01);
1677 mdelay(150);
1678 /* headphone amp power on */
1679 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1680 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0);
1681 snd_soc_component_update_bits(component, RT5645_PWR_VOL,
1682 RT5645_PWR_HV_L | RT5645_PWR_HV_R,
1683 RT5645_PWR_HV_L | RT5645_PWR_HV_R);
1684 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1685 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1686 RT5645_PWR_HA,
1687 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1688 RT5645_PWR_HA);
1689 mdelay(5);
1690 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1691 RT5645_PWR_FV1 | RT5645_PWR_FV2,
1692 RT5645_PWR_FV1 | RT5645_PWR_FV2);
1693
1694 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1695 RT5645_HP_CO_MASK | RT5645_HP_SG_MASK,
1696 RT5645_HP_CO_EN | RT5645_HP_SG_EN);
1697 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1698 0x14, 0x1aaa);
1699 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1700 0x24, 0x0430);
1701 }
1702 }
1703 hp_amp_power_count++;
1704 } else {
1705 hp_amp_power_count--;
1706 if (hp_amp_power_count <= 0) {
1707 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
1708 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1709 0x3e, 0x7400);
1710 snd_soc_component_write(component, RT5645_DEPOP_M3, 0x0737);
1711 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1712 RT5645_MAMP_INT_REG2, 0xfc00);
1713 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
1714 msleep(100);
1715 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0001);
1716
1717 } else {
1718 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1719 RT5645_HP_SG_MASK |
1720 RT5645_HP_L_SMT_MASK |
1721 RT5645_HP_R_SMT_MASK,
1722 RT5645_HP_SG_DIS |
1723 RT5645_HP_L_SMT_DIS |
1724 RT5645_HP_R_SMT_DIS);
1725 /* headphone amp power down */
1726 snd_soc_component_write(component, RT5645_DEPOP_M1, 0x0000);
1727 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1728 RT5645_PWR_HP_L | RT5645_PWR_HP_R |
1729 RT5645_PWR_HA, 0);
1730 snd_soc_component_update_bits(component, RT5645_DEPOP_M2,
1731 RT5645_DEPOP_MASK, 0);
1732 }
1733 }
1734 }
1735 }
1736
rt5645_hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1737 static int rt5645_hp_event(struct snd_soc_dapm_widget *w,
1738 struct snd_kcontrol *kcontrol, int event)
1739 {
1740 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1741 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
1742
1743 switch (event) {
1744 case SND_SOC_DAPM_POST_PMU:
1745 hp_amp_power(component, 1);
1746 /* headphone unmute sequence */
1747 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1748 snd_soc_component_update_bits(component, RT5645_DEPOP_M3,
1749 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1750 RT5645_CP_FQ3_MASK,
1751 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ1_SFT) |
1752 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1753 (RT5645_CP_FQ_192_KHZ << RT5645_CP_FQ3_SFT));
1754 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1755 RT5645_MAMP_INT_REG2, 0xfc00);
1756 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1757 RT5645_SMT_TRIG_MASK, RT5645_SMT_TRIG_EN);
1758 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1759 RT5645_RSTN_MASK, RT5645_RSTN_EN);
1760 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1761 RT5645_RSTN_MASK | RT5645_HP_L_SMT_MASK |
1762 RT5645_HP_R_SMT_MASK, RT5645_RSTN_DIS |
1763 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1764 msleep(40);
1765 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1766 RT5645_HP_SG_MASK | RT5645_HP_L_SMT_MASK |
1767 RT5645_HP_R_SMT_MASK, RT5645_HP_SG_DIS |
1768 RT5645_HP_L_SMT_DIS | RT5645_HP_R_SMT_DIS);
1769 }
1770 break;
1771
1772 case SND_SOC_DAPM_PRE_PMD:
1773 /* headphone mute sequence */
1774 if (rt5645->codec_type == CODEC_TYPE_RT5645) {
1775 snd_soc_component_update_bits(component, RT5645_DEPOP_M3,
1776 RT5645_CP_FQ1_MASK | RT5645_CP_FQ2_MASK |
1777 RT5645_CP_FQ3_MASK,
1778 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ1_SFT) |
1779 (RT5645_CP_FQ_12_KHZ << RT5645_CP_FQ2_SFT) |
1780 (RT5645_CP_FQ_96_KHZ << RT5645_CP_FQ3_SFT));
1781 regmap_write(rt5645->regmap, RT5645_PR_BASE +
1782 RT5645_MAMP_INT_REG2, 0xfc00);
1783 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1784 RT5645_HP_SG_MASK, RT5645_HP_SG_EN);
1785 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1786 RT5645_RSTP_MASK, RT5645_RSTP_EN);
1787 snd_soc_component_update_bits(component, RT5645_DEPOP_M1,
1788 RT5645_RSTP_MASK | RT5645_HP_L_SMT_MASK |
1789 RT5645_HP_R_SMT_MASK, RT5645_RSTP_DIS |
1790 RT5645_HP_L_SMT_EN | RT5645_HP_R_SMT_EN);
1791 msleep(30);
1792 }
1793 hp_amp_power(component, 0);
1794 break;
1795
1796 default:
1797 return 0;
1798 }
1799
1800 return 0;
1801 }
1802
rt5645_spk_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1803 static int rt5645_spk_event(struct snd_soc_dapm_widget *w,
1804 struct snd_kcontrol *kcontrol, int event)
1805 {
1806 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1807
1808 switch (event) {
1809 case SND_SOC_DAPM_POST_PMU:
1810 rt5645_enable_hweq(component);
1811 snd_soc_component_update_bits(component, RT5645_PWR_DIG1,
1812 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1813 RT5645_PWR_CLS_D_L,
1814 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1815 RT5645_PWR_CLS_D_L);
1816 snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,
1817 RT5645_DET_CLK_MASK, RT5645_DET_CLK_MODE1);
1818 break;
1819
1820 case SND_SOC_DAPM_PRE_PMD:
1821 snd_soc_component_update_bits(component, RT5645_GEN_CTRL3,
1822 RT5645_DET_CLK_MASK, RT5645_DET_CLK_DIS);
1823 snd_soc_component_write(component, RT5645_EQ_CTRL2, 0);
1824 snd_soc_component_update_bits(component, RT5645_PWR_DIG1,
1825 RT5645_PWR_CLS_D | RT5645_PWR_CLS_D_R |
1826 RT5645_PWR_CLS_D_L, 0);
1827 break;
1828
1829 default:
1830 return 0;
1831 }
1832
1833 return 0;
1834 }
1835
rt5645_lout_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1836 static int rt5645_lout_event(struct snd_soc_dapm_widget *w,
1837 struct snd_kcontrol *kcontrol, int event)
1838 {
1839 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1840
1841 switch (event) {
1842 case SND_SOC_DAPM_POST_PMU:
1843 hp_amp_power(component, 1);
1844 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1845 RT5645_PWR_LM, RT5645_PWR_LM);
1846 snd_soc_component_update_bits(component, RT5645_LOUT1,
1847 RT5645_L_MUTE | RT5645_R_MUTE, 0);
1848 break;
1849
1850 case SND_SOC_DAPM_PRE_PMD:
1851 snd_soc_component_update_bits(component, RT5645_LOUT1,
1852 RT5645_L_MUTE | RT5645_R_MUTE,
1853 RT5645_L_MUTE | RT5645_R_MUTE);
1854 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
1855 RT5645_PWR_LM, 0);
1856 hp_amp_power(component, 0);
1857 break;
1858
1859 default:
1860 return 0;
1861 }
1862
1863 return 0;
1864 }
1865
rt5645_bst2_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)1866 static int rt5645_bst2_event(struct snd_soc_dapm_widget *w,
1867 struct snd_kcontrol *kcontrol, int event)
1868 {
1869 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1870
1871 switch (event) {
1872 case SND_SOC_DAPM_POST_PMU:
1873 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,
1874 RT5645_PWR_BST2_P, RT5645_PWR_BST2_P);
1875 break;
1876
1877 case SND_SOC_DAPM_PRE_PMD:
1878 snd_soc_component_update_bits(component, RT5645_PWR_ANLG2,
1879 RT5645_PWR_BST2_P, 0);
1880 break;
1881
1882 default:
1883 return 0;
1884 }
1885
1886 return 0;
1887 }
1888
rt5650_hp_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)1889 static int rt5650_hp_event(struct snd_soc_dapm_widget *w,
1890 struct snd_kcontrol *k, int event)
1891 {
1892 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1893 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
1894
1895 switch (event) {
1896 case SND_SOC_DAPM_POST_PMU:
1897 if (rt5645->hp_on) {
1898 msleep(100);
1899 rt5645->hp_on = false;
1900 }
1901 break;
1902
1903 default:
1904 return 0;
1905 }
1906
1907 return 0;
1908 }
1909
rt5645_set_micbias1_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)1910 static int rt5645_set_micbias1_event(struct snd_soc_dapm_widget *w,
1911 struct snd_kcontrol *k, int event)
1912 {
1913 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1914
1915 switch (event) {
1916 case SND_SOC_DAPM_PRE_PMU:
1917 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1918 RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
1919 RT5645_MICBIAS1_POW_CTRL_SEL_M);
1920 break;
1921
1922 case SND_SOC_DAPM_POST_PMD:
1923 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1924 RT5645_MICBIAS1_POW_CTRL_SEL_MASK,
1925 RT5645_MICBIAS1_POW_CTRL_SEL_A);
1926 break;
1927
1928 default:
1929 return 0;
1930 }
1931
1932 return 0;
1933 }
1934
rt5645_set_micbias2_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * k,int event)1935 static int rt5645_set_micbias2_event(struct snd_soc_dapm_widget *w,
1936 struct snd_kcontrol *k, int event)
1937 {
1938 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1939
1940 switch (event) {
1941 case SND_SOC_DAPM_PRE_PMU:
1942 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1943 RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
1944 RT5645_MICBIAS2_POW_CTRL_SEL_M);
1945 break;
1946
1947 case SND_SOC_DAPM_POST_PMD:
1948 snd_soc_component_update_bits(component, RT5645_GEN_CTRL2,
1949 RT5645_MICBIAS2_POW_CTRL_SEL_MASK,
1950 RT5645_MICBIAS2_POW_CTRL_SEL_A);
1951 break;
1952
1953 default:
1954 return 0;
1955 }
1956
1957 return 0;
1958 }
1959
1960 static const struct snd_soc_dapm_widget rt5645_dapm_widgets[] = {
1961 SND_SOC_DAPM_SUPPLY("LDO2", RT5645_PWR_MIXER,
1962 RT5645_PWR_LDO2_BIT, 0, NULL, 0),
1963 SND_SOC_DAPM_SUPPLY("PLL1", RT5645_PWR_ANLG2,
1964 RT5645_PWR_PLL_BIT, 0, NULL, 0),
1965
1966 SND_SOC_DAPM_SUPPLY("JD Power", RT5645_PWR_ANLG2,
1967 RT5645_PWR_JD1_BIT, 0, NULL, 0),
1968 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5645_PWR_VOL,
1969 RT5645_PWR_MIC_DET_BIT, 0, NULL, 0),
1970
1971 /* ASRC */
1972 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5645_ASRC_1,
1973 11, 0, NULL, 0),
1974 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5645_ASRC_1,
1975 12, 0, NULL, 0),
1976 SND_SOC_DAPM_SUPPLY_S("DAC STO ASRC", 1, RT5645_ASRC_1,
1977 10, 0, NULL, 0),
1978 SND_SOC_DAPM_SUPPLY_S("DAC MONO L ASRC", 1, RT5645_ASRC_1,
1979 9, 0, NULL, 0),
1980 SND_SOC_DAPM_SUPPLY_S("DAC MONO R ASRC", 1, RT5645_ASRC_1,
1981 8, 0, NULL, 0),
1982 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5645_ASRC_1,
1983 7, 0, NULL, 0),
1984 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5645_ASRC_1,
1985 5, 0, NULL, 0),
1986 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5645_ASRC_1,
1987 4, 0, NULL, 0),
1988 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5645_ASRC_1,
1989 3, 0, NULL, 0),
1990 SND_SOC_DAPM_SUPPLY_S("ADC MONO L ASRC", 1, RT5645_ASRC_1,
1991 1, 0, NULL, 0),
1992 SND_SOC_DAPM_SUPPLY_S("ADC MONO R ASRC", 1, RT5645_ASRC_1,
1993 0, 0, NULL, 0),
1994
1995 /* Input Side */
1996 /* micbias */
1997 SND_SOC_DAPM_SUPPLY("micbias1", RT5645_PWR_ANLG2,
1998 RT5645_PWR_MB1_BIT, 0, rt5645_set_micbias1_event,
1999 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2000 SND_SOC_DAPM_SUPPLY("micbias2", RT5645_PWR_ANLG2,
2001 RT5645_PWR_MB2_BIT, 0, rt5645_set_micbias2_event,
2002 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2003 /* Input Lines */
2004 SND_SOC_DAPM_INPUT("DMIC L1"),
2005 SND_SOC_DAPM_INPUT("DMIC R1"),
2006 SND_SOC_DAPM_INPUT("DMIC L2"),
2007 SND_SOC_DAPM_INPUT("DMIC R2"),
2008
2009 SND_SOC_DAPM_INPUT("IN1P"),
2010 SND_SOC_DAPM_INPUT("IN1N"),
2011 SND_SOC_DAPM_INPUT("IN2P"),
2012 SND_SOC_DAPM_INPUT("IN2N"),
2013
2014 SND_SOC_DAPM_INPUT("Haptic Generator"),
2015
2016 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2017 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2018 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2019 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2020 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5645_DMIC_CTRL1,
2021 RT5645_DMIC_1_EN_SFT, 0, NULL, 0),
2022 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5645_DMIC_CTRL1,
2023 RT5645_DMIC_2_EN_SFT, 0, NULL, 0),
2024 /* Boost */
2025 SND_SOC_DAPM_PGA("BST1", RT5645_PWR_ANLG2,
2026 RT5645_PWR_BST1_BIT, 0, NULL, 0),
2027 SND_SOC_DAPM_PGA_E("BST2", RT5645_PWR_ANLG2,
2028 RT5645_PWR_BST2_BIT, 0, NULL, 0, rt5645_bst2_event,
2029 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2030 /* Input Volume */
2031 SND_SOC_DAPM_PGA("INL VOL", RT5645_PWR_VOL,
2032 RT5645_PWR_IN_L_BIT, 0, NULL, 0),
2033 SND_SOC_DAPM_PGA("INR VOL", RT5645_PWR_VOL,
2034 RT5645_PWR_IN_R_BIT, 0, NULL, 0),
2035 /* REC Mixer */
2036 SND_SOC_DAPM_MIXER("RECMIXL", RT5645_PWR_MIXER, RT5645_PWR_RM_L_BIT,
2037 0, rt5645_rec_l_mix, ARRAY_SIZE(rt5645_rec_l_mix)),
2038 SND_SOC_DAPM_MIXER("RECMIXR", RT5645_PWR_MIXER, RT5645_PWR_RM_R_BIT,
2039 0, rt5645_rec_r_mix, ARRAY_SIZE(rt5645_rec_r_mix)),
2040 /* ADCs */
2041 SND_SOC_DAPM_ADC("ADC L", NULL, SND_SOC_NOPM, 0, 0),
2042 SND_SOC_DAPM_ADC("ADC R", NULL, SND_SOC_NOPM, 0, 0),
2043
2044 SND_SOC_DAPM_SUPPLY("ADC L power", RT5645_PWR_DIG1,
2045 RT5645_PWR_ADC_L_BIT, 0, NULL, 0),
2046 SND_SOC_DAPM_SUPPLY("ADC R power", RT5645_PWR_DIG1,
2047 RT5645_PWR_ADC_R_BIT, 0, NULL, 0),
2048
2049 /* ADC Mux */
2050 SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
2051 &rt5645_sto1_dmic_mux),
2052 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2053 &rt5645_sto_adc2_mux),
2054 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2055 &rt5645_sto_adc2_mux),
2056 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2057 &rt5645_sto_adc1_mux),
2058 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2059 &rt5645_sto_adc1_mux),
2060 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2061 &rt5645_mono_dmic_l_mux),
2062 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2063 &rt5645_mono_dmic_r_mux),
2064 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2065 &rt5645_mono_adc_l2_mux),
2066 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2067 &rt5645_mono_adc_l1_mux),
2068 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2069 &rt5645_mono_adc_r1_mux),
2070 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2071 &rt5645_mono_adc_r2_mux),
2072 /* ADC Mixer */
2073
2074 SND_SOC_DAPM_SUPPLY_S("adc stereo1 filter", 1, RT5645_PWR_DIG2,
2075 RT5645_PWR_ADC_S1F_BIT, 0, NULL, 0),
2076 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
2077 rt5645_sto1_adc_l_mix, ARRAY_SIZE(rt5645_sto1_adc_l_mix),
2078 NULL, 0),
2079 SND_SOC_DAPM_MIXER_E("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
2080 rt5645_sto1_adc_r_mix, ARRAY_SIZE(rt5645_sto1_adc_r_mix),
2081 NULL, 0),
2082 SND_SOC_DAPM_SUPPLY_S("adc mono left filter", 1, RT5645_PWR_DIG2,
2083 RT5645_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2084 SND_SOC_DAPM_MIXER_E("Mono ADC MIXL", SND_SOC_NOPM, 0, 0,
2085 rt5645_mono_adc_l_mix, ARRAY_SIZE(rt5645_mono_adc_l_mix),
2086 NULL, 0),
2087 SND_SOC_DAPM_SUPPLY_S("adc mono right filter", 1, RT5645_PWR_DIG2,
2088 RT5645_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2089 SND_SOC_DAPM_MIXER_E("Mono ADC MIXR", SND_SOC_NOPM, 0, 0,
2090 rt5645_mono_adc_r_mix, ARRAY_SIZE(rt5645_mono_adc_r_mix),
2091 NULL, 0),
2092
2093 /* ADC PGA */
2094 SND_SOC_DAPM_PGA("Stereo1 ADC MIXL", SND_SOC_NOPM, 0, 0, NULL, 0),
2095 SND_SOC_DAPM_PGA("Stereo1 ADC MIXR", SND_SOC_NOPM, 0, 0, NULL, 0),
2096 SND_SOC_DAPM_PGA("Sto2 ADC LR MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2097 SND_SOC_DAPM_PGA("VAD_ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2098 SND_SOC_DAPM_PGA("IF_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2099 SND_SOC_DAPM_PGA("IF_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2100 SND_SOC_DAPM_PGA("IF1_ADC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2101 SND_SOC_DAPM_PGA("IF1_ADC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2102 SND_SOC_DAPM_PGA("IF1_ADC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2103 SND_SOC_DAPM_PGA("IF1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2104
2105 /* IF1 2 Mux */
2106 SND_SOC_DAPM_MUX("IF2 ADC Mux", SND_SOC_NOPM,
2107 0, 0, &rt5645_if2_adc_in_mux),
2108
2109 /* Digital Interface */
2110 SND_SOC_DAPM_SUPPLY("I2S1", RT5645_PWR_DIG1,
2111 RT5645_PWR_I2S1_BIT, 0, NULL, 0),
2112 SND_SOC_DAPM_PGA("IF1 DAC0", SND_SOC_NOPM, 0, 0, NULL, 0),
2113 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2114 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2115 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2116 SND_SOC_DAPM_PGA("IF1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2117 SND_SOC_DAPM_PGA("IF1 ADC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2118 SND_SOC_DAPM_PGA("IF1 ADC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2119 SND_SOC_DAPM_SUPPLY("I2S2", RT5645_PWR_DIG1,
2120 RT5645_PWR_I2S2_BIT, 0, NULL, 0),
2121 SND_SOC_DAPM_PGA("IF2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2122 SND_SOC_DAPM_PGA("IF2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2123 SND_SOC_DAPM_PGA("IF2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2124 SND_SOC_DAPM_PGA("IF2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2125
2126 /* Digital Interface Select */
2127 SND_SOC_DAPM_MUX("VAD ADC Mux", SND_SOC_NOPM,
2128 0, 0, &rt5645_vad_adc_mux),
2129
2130 /* Audio Interface */
2131 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
2132 SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
2133 SND_SOC_DAPM_AIF_IN("AIF2RX", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
2134 SND_SOC_DAPM_AIF_OUT("AIF2TX", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
2135
2136 /* Output Side */
2137 /* DAC mixer before sound effect */
2138 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
2139 rt5645_dac_l_mix, ARRAY_SIZE(rt5645_dac_l_mix)),
2140 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
2141 rt5645_dac_r_mix, ARRAY_SIZE(rt5645_dac_r_mix)),
2142
2143 /* DAC2 channel Mux */
2144 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_l2_mux),
2145 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
2146 SND_SOC_DAPM_PGA("DAC L2 Volume", RT5645_PWR_DIG1,
2147 RT5645_PWR_DAC_L2_BIT, 0, NULL, 0),
2148 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
2149 RT5645_PWR_DAC_R2_BIT, 0, NULL, 0),
2150
2151 SND_SOC_DAPM_MUX("DAC1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1l_mux),
2152 SND_SOC_DAPM_MUX("DAC1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac1r_mux),
2153
2154 /* DAC Mixer */
2155 SND_SOC_DAPM_SUPPLY_S("dac stereo1 filter", 1, RT5645_PWR_DIG2,
2156 RT5645_PWR_DAC_S1F_BIT, 0, NULL, 0),
2157 SND_SOC_DAPM_SUPPLY_S("dac mono left filter", 1, RT5645_PWR_DIG2,
2158 RT5645_PWR_DAC_MF_L_BIT, 0, NULL, 0),
2159 SND_SOC_DAPM_SUPPLY_S("dac mono right filter", 1, RT5645_PWR_DIG2,
2160 RT5645_PWR_DAC_MF_R_BIT, 0, NULL, 0),
2161 SND_SOC_DAPM_MIXER("Stereo DAC MIXL", SND_SOC_NOPM, 0, 0,
2162 rt5645_sto_dac_l_mix, ARRAY_SIZE(rt5645_sto_dac_l_mix)),
2163 SND_SOC_DAPM_MIXER("Stereo DAC MIXR", SND_SOC_NOPM, 0, 0,
2164 rt5645_sto_dac_r_mix, ARRAY_SIZE(rt5645_sto_dac_r_mix)),
2165 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
2166 rt5645_mono_dac_l_mix, ARRAY_SIZE(rt5645_mono_dac_l_mix)),
2167 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
2168 rt5645_mono_dac_r_mix, ARRAY_SIZE(rt5645_mono_dac_r_mix)),
2169 SND_SOC_DAPM_MIXER("DAC MIXL", SND_SOC_NOPM, 0, 0,
2170 rt5645_dig_l_mix, ARRAY_SIZE(rt5645_dig_l_mix)),
2171 SND_SOC_DAPM_MIXER("DAC MIXR", SND_SOC_NOPM, 0, 0,
2172 rt5645_dig_r_mix, ARRAY_SIZE(rt5645_dig_r_mix)),
2173
2174 /* DACs */
2175 SND_SOC_DAPM_DAC("DAC L1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L1_BIT,
2176 0),
2177 SND_SOC_DAPM_DAC("DAC L2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_L2_BIT,
2178 0),
2179 SND_SOC_DAPM_DAC("DAC R1", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R1_BIT,
2180 0),
2181 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
2182 0),
2183 /* OUT Mixer */
2184 SND_SOC_DAPM_MIXER("SPK MIXL", RT5645_PWR_MIXER, RT5645_PWR_SM_L_BIT,
2185 0, rt5645_spk_l_mix, ARRAY_SIZE(rt5645_spk_l_mix)),
2186 SND_SOC_DAPM_MIXER("SPK MIXR", RT5645_PWR_MIXER, RT5645_PWR_SM_R_BIT,
2187 0, rt5645_spk_r_mix, ARRAY_SIZE(rt5645_spk_r_mix)),
2188 SND_SOC_DAPM_MIXER("OUT MIXL", RT5645_PWR_MIXER, RT5645_PWR_OM_L_BIT,
2189 0, rt5645_out_l_mix, ARRAY_SIZE(rt5645_out_l_mix)),
2190 SND_SOC_DAPM_MIXER("OUT MIXR", RT5645_PWR_MIXER, RT5645_PWR_OM_R_BIT,
2191 0, rt5645_out_r_mix, ARRAY_SIZE(rt5645_out_r_mix)),
2192 /* Ouput Volume */
2193 SND_SOC_DAPM_SWITCH("SPKVOL L", RT5645_PWR_VOL, RT5645_PWR_SV_L_BIT, 0,
2194 &spk_l_vol_control),
2195 SND_SOC_DAPM_SWITCH("SPKVOL R", RT5645_PWR_VOL, RT5645_PWR_SV_R_BIT, 0,
2196 &spk_r_vol_control),
2197 SND_SOC_DAPM_MIXER("HPOVOL MIXL", RT5645_PWR_VOL, RT5645_PWR_HV_L_BIT,
2198 0, rt5645_hpvoll_mix, ARRAY_SIZE(rt5645_hpvoll_mix)),
2199 SND_SOC_DAPM_MIXER("HPOVOL MIXR", RT5645_PWR_VOL, RT5645_PWR_HV_R_BIT,
2200 0, rt5645_hpvolr_mix, ARRAY_SIZE(rt5645_hpvolr_mix)),
2201 SND_SOC_DAPM_SUPPLY("HPOVOL MIXL Power", RT5645_PWR_MIXER,
2202 RT5645_PWR_HM_L_BIT, 0, NULL, 0),
2203 SND_SOC_DAPM_SUPPLY("HPOVOL MIXR Power", RT5645_PWR_MIXER,
2204 RT5645_PWR_HM_R_BIT, 0, NULL, 0),
2205 SND_SOC_DAPM_PGA("DAC 1", SND_SOC_NOPM, 0, 0, NULL, 0),
2206 SND_SOC_DAPM_PGA("DAC 2", SND_SOC_NOPM, 0, 0, NULL, 0),
2207 SND_SOC_DAPM_PGA("HPOVOL", SND_SOC_NOPM, 0, 0, NULL, 0),
2208 SND_SOC_DAPM_SWITCH("HPOVOL L", SND_SOC_NOPM, 0, 0, &hp_l_vol_control),
2209 SND_SOC_DAPM_SWITCH("HPOVOL R", SND_SOC_NOPM, 0, 0, &hp_r_vol_control),
2210
2211 /* HPO/LOUT/Mono Mixer */
2212 SND_SOC_DAPM_MIXER("SPOL MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_l_mix,
2213 ARRAY_SIZE(rt5645_spo_l_mix)),
2214 SND_SOC_DAPM_MIXER("SPOR MIX", SND_SOC_NOPM, 0, 0, rt5645_spo_r_mix,
2215 ARRAY_SIZE(rt5645_spo_r_mix)),
2216 SND_SOC_DAPM_MIXER("HPO MIX", SND_SOC_NOPM, 0, 0, rt5645_hpo_mix,
2217 ARRAY_SIZE(rt5645_hpo_mix)),
2218 SND_SOC_DAPM_MIXER("LOUT MIX", SND_SOC_NOPM, 0, 0, rt5645_lout_mix,
2219 ARRAY_SIZE(rt5645_lout_mix)),
2220
2221 SND_SOC_DAPM_PGA_S("HP amp", 1, SND_SOC_NOPM, 0, 0, rt5645_hp_event,
2222 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2223 SND_SOC_DAPM_PGA_S("LOUT amp", 1, SND_SOC_NOPM, 0, 0, rt5645_lout_event,
2224 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2225 SND_SOC_DAPM_PGA_S("SPK amp", 2, SND_SOC_NOPM, 0, 0, rt5645_spk_event,
2226 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMU),
2227
2228 /* PDM */
2229 SND_SOC_DAPM_SUPPLY("PDM1 Power", RT5645_PWR_DIG2, RT5645_PWR_PDM1_BIT,
2230 0, NULL, 0),
2231 SND_SOC_DAPM_MUX("PDM1 L Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_l_mux),
2232 SND_SOC_DAPM_MUX("PDM1 R Mux", SND_SOC_NOPM, 0, 0, &rt5645_pdm1_r_mux),
2233
2234 SND_SOC_DAPM_SWITCH("PDM1 L", SND_SOC_NOPM, 0, 0, &pdm1_l_vol_control),
2235 SND_SOC_DAPM_SWITCH("PDM1 R", SND_SOC_NOPM, 0, 0, &pdm1_r_vol_control),
2236
2237 /* Output Lines */
2238 SND_SOC_DAPM_OUTPUT("HPOL"),
2239 SND_SOC_DAPM_OUTPUT("HPOR"),
2240 SND_SOC_DAPM_OUTPUT("LOUTL"),
2241 SND_SOC_DAPM_OUTPUT("LOUTR"),
2242 SND_SOC_DAPM_OUTPUT("PDM1L"),
2243 SND_SOC_DAPM_OUTPUT("PDM1R"),
2244 SND_SOC_DAPM_OUTPUT("SPOL"),
2245 SND_SOC_DAPM_OUTPUT("SPOR"),
2246 SND_SOC_DAPM_POST("DAPM_POST", rt5650_hp_event),
2247 };
2248
2249 static const struct snd_soc_dapm_widget rt5645_specific_dapm_widgets[] = {
2250 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2251 &rt5645_if1_dac0_tdm_sel_mux),
2252 SND_SOC_DAPM_MUX("RT5645 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2253 &rt5645_if1_dac1_tdm_sel_mux),
2254 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2255 &rt5645_if1_dac2_tdm_sel_mux),
2256 SND_SOC_DAPM_MUX("RT5645 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2257 &rt5645_if1_dac3_tdm_sel_mux),
2258 SND_SOC_DAPM_MUX("RT5645 IF1 ADC Mux", SND_SOC_NOPM,
2259 0, 0, &rt5645_if1_adc_in_mux),
2260 SND_SOC_DAPM_MUX("RT5645 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2261 0, 0, &rt5645_if1_adc1_in_mux),
2262 SND_SOC_DAPM_MUX("RT5645 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2263 0, 0, &rt5645_if1_adc2_in_mux),
2264 SND_SOC_DAPM_MUX("RT5645 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2265 0, 0, &rt5645_if1_adc3_in_mux),
2266 };
2267
2268 static const struct snd_soc_dapm_widget rt5650_specific_dapm_widgets[] = {
2269 SND_SOC_DAPM_MUX("A DAC1 L Mux", SND_SOC_NOPM,
2270 0, 0, &rt5650_a_dac1_l_mux),
2271 SND_SOC_DAPM_MUX("A DAC1 R Mux", SND_SOC_NOPM,
2272 0, 0, &rt5650_a_dac1_r_mux),
2273 SND_SOC_DAPM_MUX("A DAC2 L Mux", SND_SOC_NOPM,
2274 0, 0, &rt5650_a_dac2_l_mux),
2275 SND_SOC_DAPM_MUX("A DAC2 R Mux", SND_SOC_NOPM,
2276 0, 0, &rt5650_a_dac2_r_mux),
2277
2278 SND_SOC_DAPM_MUX("RT5650 IF1 ADC1 Swap Mux", SND_SOC_NOPM,
2279 0, 0, &rt5650_if1_adc1_in_mux),
2280 SND_SOC_DAPM_MUX("RT5650 IF1 ADC2 Swap Mux", SND_SOC_NOPM,
2281 0, 0, &rt5650_if1_adc2_in_mux),
2282 SND_SOC_DAPM_MUX("RT5650 IF1 ADC3 Swap Mux", SND_SOC_NOPM,
2283 0, 0, &rt5650_if1_adc3_in_mux),
2284 SND_SOC_DAPM_MUX("RT5650 IF1 ADC Mux", SND_SOC_NOPM,
2285 0, 0, &rt5650_if1_adc_in_mux),
2286
2287 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 L Mux", SND_SOC_NOPM, 0, 0,
2288 &rt5650_if1_dac0_tdm_sel_mux),
2289 SND_SOC_DAPM_MUX("RT5650 IF1 DAC1 R Mux", SND_SOC_NOPM, 0, 0,
2290 &rt5650_if1_dac1_tdm_sel_mux),
2291 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 L Mux", SND_SOC_NOPM, 0, 0,
2292 &rt5650_if1_dac2_tdm_sel_mux),
2293 SND_SOC_DAPM_MUX("RT5650 IF1 DAC2 R Mux", SND_SOC_NOPM, 0, 0,
2294 &rt5650_if1_dac3_tdm_sel_mux),
2295 };
2296
2297 static const struct snd_soc_dapm_route rt5645_dapm_routes[] = {
2298 { "adc stereo1 filter", NULL, "ADC STO1 ASRC", is_using_asrc },
2299 { "adc mono left filter", NULL, "ADC MONO L ASRC", is_using_asrc },
2300 { "adc mono right filter", NULL, "ADC MONO R ASRC", is_using_asrc },
2301 { "dac mono left filter", NULL, "DAC MONO L ASRC", is_using_asrc },
2302 { "dac mono right filter", NULL, "DAC MONO R ASRC", is_using_asrc },
2303 { "dac stereo1 filter", NULL, "DAC STO ASRC", is_using_asrc },
2304
2305 { "I2S1", NULL, "I2S1 ASRC" },
2306 { "I2S2", NULL, "I2S2 ASRC" },
2307
2308 { "IN1P", NULL, "LDO2" },
2309 { "IN2P", NULL, "LDO2" },
2310
2311 { "DMIC1", NULL, "DMIC L1" },
2312 { "DMIC1", NULL, "DMIC R1" },
2313 { "DMIC2", NULL, "DMIC L2" },
2314 { "DMIC2", NULL, "DMIC R2" },
2315
2316 { "BST1", NULL, "IN1P" },
2317 { "BST1", NULL, "IN1N" },
2318 { "BST1", NULL, "JD Power" },
2319 { "BST1", NULL, "Mic Det Power" },
2320 { "BST2", NULL, "IN2P" },
2321 { "BST2", NULL, "IN2N" },
2322
2323 { "INL VOL", NULL, "IN2P" },
2324 { "INR VOL", NULL, "IN2N" },
2325
2326 { "RECMIXL", "HPOL Switch", "HPOL" },
2327 { "RECMIXL", "INL Switch", "INL VOL" },
2328 { "RECMIXL", "BST2 Switch", "BST2" },
2329 { "RECMIXL", "BST1 Switch", "BST1" },
2330 { "RECMIXL", "OUT MIXL Switch", "OUT MIXL" },
2331
2332 { "RECMIXR", "HPOR Switch", "HPOR" },
2333 { "RECMIXR", "INR Switch", "INR VOL" },
2334 { "RECMIXR", "BST2 Switch", "BST2" },
2335 { "RECMIXR", "BST1 Switch", "BST1" },
2336 { "RECMIXR", "OUT MIXR Switch", "OUT MIXR" },
2337
2338 { "ADC L", NULL, "RECMIXL" },
2339 { "ADC L", NULL, "ADC L power" },
2340 { "ADC R", NULL, "RECMIXR" },
2341 { "ADC R", NULL, "ADC R power" },
2342
2343 {"DMIC L1", NULL, "DMIC CLK"},
2344 {"DMIC L1", NULL, "DMIC1 Power"},
2345 {"DMIC R1", NULL, "DMIC CLK"},
2346 {"DMIC R1", NULL, "DMIC1 Power"},
2347 {"DMIC L2", NULL, "DMIC CLK"},
2348 {"DMIC L2", NULL, "DMIC2 Power"},
2349 {"DMIC R2", NULL, "DMIC CLK"},
2350 {"DMIC R2", NULL, "DMIC2 Power"},
2351
2352 { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
2353 { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
2354 { "Stereo1 DMIC Mux", NULL, "DMIC STO1 ASRC" },
2355
2356 { "Mono DMIC L Mux", "DMIC1", "DMIC L1" },
2357 { "Mono DMIC L Mux", "DMIC2", "DMIC L2" },
2358 { "Mono DMIC L Mux", NULL, "DMIC MONO L ASRC" },
2359
2360 { "Mono DMIC R Mux", "DMIC1", "DMIC R1" },
2361 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
2362 { "Mono DMIC R Mux", NULL, "DMIC MONO R ASRC" },
2363
2364 { "Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2365 { "Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL" },
2366 { "Stereo1 ADC L1 Mux", "ADC", "ADC L" },
2367 { "Stereo1 ADC L1 Mux", "DAC MIX", "DAC MIXL" },
2368
2369 { "Stereo1 ADC R1 Mux", "ADC", "ADC R" },
2370 { "Stereo1 ADC R1 Mux", "DAC MIX", "DAC MIXR" },
2371 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2372 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2373
2374 { "Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux" },
2375 { "Mono ADC L2 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2376 { "Mono ADC L1 Mux", "Mono DAC MIXL", "Mono DAC MIXL" },
2377 { "Mono ADC L1 Mux", "ADC", "ADC L" },
2378
2379 { "Mono ADC R1 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2380 { "Mono ADC R1 Mux", "ADC", "ADC R" },
2381 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2382 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2383
2384 { "Sto1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux" },
2385 { "Sto1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux" },
2386 { "Sto1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux" },
2387 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2388
2389 { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
2390 { "Stereo1 ADC MIXL", NULL, "adc stereo1 filter" },
2391 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2392
2393 { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
2394 { "Stereo1 ADC MIXR", NULL, "adc stereo1 filter" },
2395 { "adc stereo1 filter", NULL, "PLL1", is_sys_clk_from_pll },
2396
2397 { "Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux" },
2398 { "Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux" },
2399 { "Mono ADC MIXL", NULL, "adc mono left filter" },
2400 { "adc mono left filter", NULL, "PLL1", is_sys_clk_from_pll },
2401
2402 { "Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux" },
2403 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2404 { "Mono ADC MIXR", NULL, "adc mono right filter" },
2405 { "adc mono right filter", NULL, "PLL1", is_sys_clk_from_pll },
2406
2407 { "VAD ADC Mux", "Sto1 ADC L", "Stereo1 ADC MIXL" },
2408 { "VAD ADC Mux", "Mono ADC L", "Mono ADC MIXL" },
2409 { "VAD ADC Mux", "Mono ADC R", "Mono ADC MIXR" },
2410
2411 { "IF_ADC1", NULL, "Stereo1 ADC MIXL" },
2412 { "IF_ADC1", NULL, "Stereo1 ADC MIXR" },
2413 { "IF_ADC2", NULL, "Mono ADC MIXL" },
2414 { "IF_ADC2", NULL, "Mono ADC MIXR" },
2415 { "VAD_ADC", NULL, "VAD ADC Mux" },
2416
2417 { "IF2 ADC Mux", "IF_ADC1", "IF_ADC1" },
2418 { "IF2 ADC Mux", "IF_ADC2", "IF_ADC2" },
2419 { "IF2 ADC Mux", "VAD_ADC", "VAD_ADC" },
2420
2421 { "IF1 ADC", NULL, "I2S1" },
2422 { "IF2 ADC", NULL, "I2S2" },
2423 { "IF2 ADC", NULL, "IF2 ADC Mux" },
2424
2425 { "AIF2TX", NULL, "IF2 ADC" },
2426
2427 { "IF1 DAC0", NULL, "AIF1RX" },
2428 { "IF1 DAC1", NULL, "AIF1RX" },
2429 { "IF1 DAC2", NULL, "AIF1RX" },
2430 { "IF1 DAC3", NULL, "AIF1RX" },
2431 { "IF2 DAC", NULL, "AIF2RX" },
2432
2433 { "IF1 DAC0", NULL, "I2S1" },
2434 { "IF1 DAC1", NULL, "I2S1" },
2435 { "IF1 DAC2", NULL, "I2S1" },
2436 { "IF1 DAC3", NULL, "I2S1" },
2437 { "IF2 DAC", NULL, "I2S2" },
2438
2439 { "IF2 DAC L", NULL, "IF2 DAC" },
2440 { "IF2 DAC R", NULL, "IF2 DAC" },
2441
2442 { "DAC1 L Mux", "IF2 DAC", "IF2 DAC L" },
2443 { "DAC1 R Mux", "IF2 DAC", "IF2 DAC R" },
2444
2445 { "DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL" },
2446 { "DAC1 MIXL", "DAC1 Switch", "DAC1 L Mux" },
2447 { "DAC1 MIXL", NULL, "dac stereo1 filter" },
2448 { "DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR" },
2449 { "DAC1 MIXR", "DAC1 Switch", "DAC1 R Mux" },
2450 { "DAC1 MIXR", NULL, "dac stereo1 filter" },
2451
2452 { "DAC L2 Mux", "IF2 DAC", "IF2 DAC L" },
2453 { "DAC L2 Mux", "Mono ADC", "Mono ADC MIXL" },
2454 { "DAC L2 Mux", "VAD_ADC", "VAD_ADC" },
2455 { "DAC L2 Volume", NULL, "DAC L2 Mux" },
2456 { "DAC L2 Volume", NULL, "dac mono left filter" },
2457
2458 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2459 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
2460 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
2461 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2462 { "DAC R2 Volume", NULL, "dac mono right filter" },
2463
2464 { "Stereo DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2465 { "Stereo DAC MIXL", "DAC R1 Switch", "DAC1 MIXR" },
2466 { "Stereo DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2467 { "Stereo DAC MIXL", NULL, "dac stereo1 filter" },
2468 { "Stereo DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2469 { "Stereo DAC MIXR", "DAC L1 Switch", "DAC1 MIXL" },
2470 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2471 { "Stereo DAC MIXR", NULL, "dac stereo1 filter" },
2472
2473 { "Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL" },
2474 { "Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2475 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2476 { "Mono DAC MIXL", NULL, "dac mono left filter" },
2477 { "Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR" },
2478 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2479 { "Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2480 { "Mono DAC MIXR", NULL, "dac mono right filter" },
2481
2482 { "DAC MIXL", "Sto DAC Mix L Switch", "Stereo DAC MIXL" },
2483 { "DAC MIXL", "DAC L2 Switch", "DAC L2 Volume" },
2484 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2485 { "DAC MIXR", "Sto DAC Mix R Switch", "Stereo DAC MIXR" },
2486 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2487 { "DAC MIXR", "DAC L2 Switch", "DAC L2 Volume" },
2488
2489 { "DAC L1", NULL, "PLL1", is_sys_clk_from_pll },
2490 { "DAC R1", NULL, "PLL1", is_sys_clk_from_pll },
2491 { "DAC L2", NULL, "PLL1", is_sys_clk_from_pll },
2492 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
2493
2494 { "SPK MIXL", "BST1 Switch", "BST1" },
2495 { "SPK MIXL", "INL Switch", "INL VOL" },
2496 { "SPK MIXL", "DAC L1 Switch", "DAC L1" },
2497 { "SPK MIXL", "DAC L2 Switch", "DAC L2" },
2498 { "SPK MIXR", "BST2 Switch", "BST2" },
2499 { "SPK MIXR", "INR Switch", "INR VOL" },
2500 { "SPK MIXR", "DAC R1 Switch", "DAC R1" },
2501 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
2502
2503 { "OUT MIXL", "BST1 Switch", "BST1" },
2504 { "OUT MIXL", "INL Switch", "INL VOL" },
2505 { "OUT MIXL", "DAC L2 Switch", "DAC L2" },
2506 { "OUT MIXL", "DAC L1 Switch", "DAC L1" },
2507
2508 { "OUT MIXR", "BST2 Switch", "BST2" },
2509 { "OUT MIXR", "INR Switch", "INR VOL" },
2510 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2511 { "OUT MIXR", "DAC R1 Switch", "DAC R1" },
2512
2513 { "HPOVOL MIXL", "DAC1 Switch", "DAC L1" },
2514 { "HPOVOL MIXL", "DAC2 Switch", "DAC L2" },
2515 { "HPOVOL MIXL", "INL Switch", "INL VOL" },
2516 { "HPOVOL MIXL", "BST1 Switch", "BST1" },
2517 { "HPOVOL MIXL", NULL, "HPOVOL MIXL Power" },
2518 { "HPOVOL MIXR", "DAC1 Switch", "DAC R1" },
2519 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
2520 { "HPOVOL MIXR", "INR Switch", "INR VOL" },
2521 { "HPOVOL MIXR", "BST2 Switch", "BST2" },
2522 { "HPOVOL MIXR", NULL, "HPOVOL MIXR Power" },
2523
2524 { "DAC 2", NULL, "DAC L2" },
2525 { "DAC 2", NULL, "DAC R2" },
2526 { "DAC 1", NULL, "DAC L1" },
2527 { "DAC 1", NULL, "DAC R1" },
2528 { "HPOVOL L", "Switch", "HPOVOL MIXL" },
2529 { "HPOVOL R", "Switch", "HPOVOL MIXR" },
2530 { "HPOVOL", NULL, "HPOVOL L" },
2531 { "HPOVOL", NULL, "HPOVOL R" },
2532 { "HPO MIX", "DAC1 Switch", "DAC 1" },
2533 { "HPO MIX", "HPVOL Switch", "HPOVOL" },
2534
2535 { "SPKVOL L", "Switch", "SPK MIXL" },
2536 { "SPKVOL R", "Switch", "SPK MIXR" },
2537
2538 { "SPOL MIX", "DAC L1 Switch", "DAC L1" },
2539 { "SPOL MIX", "SPKVOL L Switch", "SPKVOL L" },
2540 { "SPOR MIX", "DAC R1 Switch", "DAC R1" },
2541 { "SPOR MIX", "SPKVOL R Switch", "SPKVOL R" },
2542
2543 { "LOUT MIX", "DAC L1 Switch", "DAC L1" },
2544 { "LOUT MIX", "DAC R1 Switch", "DAC R1" },
2545 { "LOUT MIX", "OUTMIX L Switch", "OUT MIXL" },
2546 { "LOUT MIX", "OUTMIX R Switch", "OUT MIXR" },
2547
2548 { "PDM1 L Mux", "Stereo DAC", "Stereo DAC MIXL" },
2549 { "PDM1 L Mux", "Mono DAC", "Mono DAC MIXL" },
2550 { "PDM1 L Mux", NULL, "PDM1 Power" },
2551 { "PDM1 R Mux", "Stereo DAC", "Stereo DAC MIXR" },
2552 { "PDM1 R Mux", "Mono DAC", "Mono DAC MIXR" },
2553 { "PDM1 R Mux", NULL, "PDM1 Power" },
2554
2555 { "HP amp", NULL, "HPO MIX" },
2556 { "HP amp", NULL, "JD Power" },
2557 { "HP amp", NULL, "Mic Det Power" },
2558 { "HP amp", NULL, "LDO2" },
2559 { "HPOL", NULL, "HP amp" },
2560 { "HPOR", NULL, "HP amp" },
2561
2562 { "LOUT amp", NULL, "LOUT MIX" },
2563 { "LOUTL", NULL, "LOUT amp" },
2564 { "LOUTR", NULL, "LOUT amp" },
2565
2566 { "PDM1 L", "Switch", "PDM1 L Mux" },
2567 { "PDM1 R", "Switch", "PDM1 R Mux" },
2568
2569 { "PDM1L", NULL, "PDM1 L" },
2570 { "PDM1R", NULL, "PDM1 R" },
2571
2572 { "SPK amp", NULL, "SPOL MIX" },
2573 { "SPK amp", NULL, "SPOR MIX" },
2574 { "SPOL", NULL, "SPK amp" },
2575 { "SPOR", NULL, "SPK amp" },
2576 };
2577
2578 static const struct snd_soc_dapm_route rt5650_specific_dapm_routes[] = {
2579 { "A DAC1 L Mux", "DAC1", "DAC1 MIXL"},
2580 { "A DAC1 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2581 { "A DAC1 R Mux", "DAC1", "DAC1 MIXR"},
2582 { "A DAC1 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2583
2584 { "A DAC2 L Mux", "Stereo DAC Mixer", "Stereo DAC MIXL"},
2585 { "A DAC2 L Mux", "Mono DAC Mixer", "Mono DAC MIXL"},
2586 { "A DAC2 R Mux", "Stereo DAC Mixer", "Stereo DAC MIXR"},
2587 { "A DAC2 R Mux", "Mono DAC Mixer", "Mono DAC MIXR"},
2588
2589 { "DAC L1", NULL, "A DAC1 L Mux" },
2590 { "DAC R1", NULL, "A DAC1 R Mux" },
2591 { "DAC L2", NULL, "A DAC2 L Mux" },
2592 { "DAC R2", NULL, "A DAC2 R Mux" },
2593
2594 { "RT5650 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2595 { "RT5650 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2596 { "RT5650 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2597 { "RT5650 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2598
2599 { "RT5650 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2600 { "RT5650 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2601 { "RT5650 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2602 { "RT5650 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2603
2604 { "RT5650 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2605 { "RT5650 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2606 { "RT5650 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2607 { "RT5650 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2608
2609 { "IF1 ADC", NULL, "RT5650 IF1 ADC1 Swap Mux" },
2610 { "IF1 ADC", NULL, "RT5650 IF1 ADC2 Swap Mux" },
2611 { "IF1 ADC", NULL, "RT5650 IF1 ADC3 Swap Mux" },
2612
2613 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/DAC_REF/Null", "IF1 ADC" },
2614 { "RT5650 IF1 ADC Mux", "IF_ADC1/IF_ADC2/Null/DAC_REF", "IF1 ADC" },
2615 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/IF_ADC2/Null", "IF1 ADC" },
2616 { "RT5650 IF1 ADC Mux", "IF_ADC1/DAC_REF/Null/IF_ADC2", "IF1 ADC" },
2617 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/DAC_REF/IF_ADC2", "IF1 ADC" },
2618 { "RT5650 IF1 ADC Mux", "IF_ADC1/Null/IF_ADC2/DAC_REF", "IF1 ADC" },
2619
2620 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/DAC_REF/Null", "IF1 ADC" },
2621 { "RT5650 IF1 ADC Mux", "IF_ADC2/IF_ADC1/Null/DAC_REF", "IF1 ADC" },
2622 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/IF_ADC1/Null", "IF1 ADC" },
2623 { "RT5650 IF1 ADC Mux", "IF_ADC2/DAC_REF/Null/IF_ADC1", "IF1 ADC" },
2624 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/DAC_REF/IF_ADC1", "IF1 ADC" },
2625 { "RT5650 IF1 ADC Mux", "IF_ADC2/Null/IF_ADC1/DAC_REF", "IF1 ADC" },
2626
2627 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/IF_ADC2/Null", "IF1 ADC" },
2628 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC1/Null/IF_ADC2", "IF1 ADC" },
2629 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/IF_ADC1/Null", "IF1 ADC" },
2630 { "RT5650 IF1 ADC Mux", "DAC_REF/IF_ADC2/Null/IF_ADC1", "IF1 ADC" },
2631 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC1/IF_ADC2", "IF1 ADC" },
2632 { "RT5650 IF1 ADC Mux", "DAC_REF/Null/IF_ADC2/IF_ADC1", "IF1 ADC" },
2633
2634 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/IF_ADC2/DAC_REF", "IF1 ADC" },
2635 { "RT5650 IF1 ADC Mux", "Null/IF_ADC1/DAC_REF/IF_ADC2", "IF1 ADC" },
2636 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/IF_ADC1/DAC_REF", "IF1 ADC" },
2637 { "RT5650 IF1 ADC Mux", "Null/IF_ADC2/DAC_REF/IF_ADC1", "IF1 ADC" },
2638 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC1/IF_ADC2", "IF1 ADC" },
2639 { "RT5650 IF1 ADC Mux", "Null/DAC_REF/IF_ADC2/IF_ADC1", "IF1 ADC" },
2640 { "AIF1TX", NULL, "RT5650 IF1 ADC Mux" },
2641
2642 { "RT5650 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2643 { "RT5650 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2644 { "RT5650 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2645 { "RT5650 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2646
2647 { "RT5650 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2648 { "RT5650 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2649 { "RT5650 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2650 { "RT5650 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2651
2652 { "RT5650 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2653 { "RT5650 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2654 { "RT5650 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2655 { "RT5650 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2656
2657 { "RT5650 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2658 { "RT5650 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2659 { "RT5650 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2660 { "RT5650 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2661
2662 { "DAC1 L Mux", "IF1 DAC", "RT5650 IF1 DAC1 L Mux" },
2663 { "DAC1 R Mux", "IF1 DAC", "RT5650 IF1 DAC1 R Mux" },
2664
2665 { "DAC L2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 L Mux" },
2666 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
2667 };
2668
2669 static const struct snd_soc_dapm_route rt5645_specific_dapm_routes[] = {
2670 { "DAC L1", NULL, "Stereo DAC MIXL" },
2671 { "DAC R1", NULL, "Stereo DAC MIXR" },
2672 { "DAC L2", NULL, "Mono DAC MIXL" },
2673 { "DAC R2", NULL, "Mono DAC MIXR" },
2674
2675 { "RT5645 IF1 ADC1 Swap Mux", "L/R", "IF_ADC1" },
2676 { "RT5645 IF1 ADC1 Swap Mux", "R/L", "IF_ADC1" },
2677 { "RT5645 IF1 ADC1 Swap Mux", "L/L", "IF_ADC1" },
2678 { "RT5645 IF1 ADC1 Swap Mux", "R/R", "IF_ADC1" },
2679
2680 { "RT5645 IF1 ADC2 Swap Mux", "L/R", "IF_ADC2" },
2681 { "RT5645 IF1 ADC2 Swap Mux", "R/L", "IF_ADC2" },
2682 { "RT5645 IF1 ADC2 Swap Mux", "L/L", "IF_ADC2" },
2683 { "RT5645 IF1 ADC2 Swap Mux", "R/R", "IF_ADC2" },
2684
2685 { "RT5645 IF1 ADC3 Swap Mux", "L/R", "VAD_ADC" },
2686 { "RT5645 IF1 ADC3 Swap Mux", "R/L", "VAD_ADC" },
2687 { "RT5645 IF1 ADC3 Swap Mux", "L/L", "VAD_ADC" },
2688 { "RT5645 IF1 ADC3 Swap Mux", "R/R", "VAD_ADC" },
2689
2690 { "IF1 ADC", NULL, "RT5645 IF1 ADC1 Swap Mux" },
2691 { "IF1 ADC", NULL, "RT5645 IF1 ADC2 Swap Mux" },
2692 { "IF1 ADC", NULL, "RT5645 IF1 ADC3 Swap Mux" },
2693
2694 { "RT5645 IF1 ADC Mux", "IF_ADC1/IF_ADC2/VAD_ADC", "IF1 ADC" },
2695 { "RT5645 IF1 ADC Mux", "IF_ADC2/IF_ADC1/VAD_ADC", "IF1 ADC" },
2696 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC1/IF_ADC2", "IF1 ADC" },
2697 { "RT5645 IF1 ADC Mux", "VAD_ADC/IF_ADC2/IF_ADC1", "IF1 ADC" },
2698 { "AIF1TX", NULL, "RT5645 IF1 ADC Mux" },
2699
2700 { "RT5645 IF1 DAC1 L Mux", "Slot0", "IF1 DAC0" },
2701 { "RT5645 IF1 DAC1 L Mux", "Slot1", "IF1 DAC1" },
2702 { "RT5645 IF1 DAC1 L Mux", "Slot2", "IF1 DAC2" },
2703 { "RT5645 IF1 DAC1 L Mux", "Slot3", "IF1 DAC3" },
2704
2705 { "RT5645 IF1 DAC1 R Mux", "Slot0", "IF1 DAC0" },
2706 { "RT5645 IF1 DAC1 R Mux", "Slot1", "IF1 DAC1" },
2707 { "RT5645 IF1 DAC1 R Mux", "Slot2", "IF1 DAC2" },
2708 { "RT5645 IF1 DAC1 R Mux", "Slot3", "IF1 DAC3" },
2709
2710 { "RT5645 IF1 DAC2 L Mux", "Slot0", "IF1 DAC0" },
2711 { "RT5645 IF1 DAC2 L Mux", "Slot1", "IF1 DAC1" },
2712 { "RT5645 IF1 DAC2 L Mux", "Slot2", "IF1 DAC2" },
2713 { "RT5645 IF1 DAC2 L Mux", "Slot3", "IF1 DAC3" },
2714
2715 { "RT5645 IF1 DAC2 R Mux", "Slot0", "IF1 DAC0" },
2716 { "RT5645 IF1 DAC2 R Mux", "Slot1", "IF1 DAC1" },
2717 { "RT5645 IF1 DAC2 R Mux", "Slot2", "IF1 DAC2" },
2718 { "RT5645 IF1 DAC2 R Mux", "Slot3", "IF1 DAC3" },
2719
2720 { "DAC1 L Mux", "IF1 DAC", "RT5645 IF1 DAC1 L Mux" },
2721 { "DAC1 R Mux", "IF1 DAC", "RT5645 IF1 DAC1 R Mux" },
2722
2723 { "DAC L2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 L Mux" },
2724 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
2725 };
2726
2727 static const struct snd_soc_dapm_route rt5645_old_dapm_routes[] = {
2728 { "SPOL MIX", "DAC R1 Switch", "DAC R1" },
2729 { "SPOL MIX", "SPKVOL R Switch", "SPKVOL R" },
2730 };
2731
rt5645_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)2732 static int rt5645_hw_params(struct snd_pcm_substream *substream,
2733 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2734 {
2735 struct snd_soc_component *component = dai->component;
2736 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2737 unsigned int val_len = 0, val_clk, mask_clk, dl_sft;
2738 int pre_div, bclk_ms, frame_size;
2739
2740 rt5645->lrck[dai->id] = params_rate(params);
2741 pre_div = rl6231_get_clk_info(rt5645->sysclk, rt5645->lrck[dai->id]);
2742 if (pre_div < 0) {
2743 dev_err(component->dev, "Unsupported clock setting\n");
2744 return -EINVAL;
2745 }
2746 frame_size = snd_soc_params_to_frame_size(params);
2747 if (frame_size < 0) {
2748 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
2749 return -EINVAL;
2750 }
2751
2752 switch (rt5645->codec_type) {
2753 case CODEC_TYPE_RT5650:
2754 dl_sft = 4;
2755 break;
2756 default:
2757 dl_sft = 2;
2758 break;
2759 }
2760
2761 bclk_ms = frame_size > 32;
2762 rt5645->bclk[dai->id] = rt5645->lrck[dai->id] * (32 << bclk_ms);
2763
2764 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
2765 rt5645->bclk[dai->id], rt5645->lrck[dai->id]);
2766 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
2767 bclk_ms, pre_div, dai->id);
2768
2769 switch (params_width(params)) {
2770 case 16:
2771 break;
2772 case 20:
2773 val_len = 0x1;
2774 break;
2775 case 24:
2776 val_len = 0x2;
2777 break;
2778 case 8:
2779 val_len = 0x3;
2780 break;
2781 default:
2782 return -EINVAL;
2783 }
2784
2785 switch (dai->id) {
2786 case RT5645_AIF1:
2787 mask_clk = RT5645_I2S_PD1_MASK;
2788 val_clk = pre_div << RT5645_I2S_PD1_SFT;
2789 snd_soc_component_update_bits(component, RT5645_I2S1_SDP,
2790 (0x3 << dl_sft), (val_len << dl_sft));
2791 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);
2792 break;
2793 case RT5645_AIF2:
2794 mask_clk = RT5645_I2S_BCLK_MS2_MASK | RT5645_I2S_PD2_MASK;
2795 val_clk = bclk_ms << RT5645_I2S_BCLK_MS2_SFT |
2796 pre_div << RT5645_I2S_PD2_SFT;
2797 snd_soc_component_update_bits(component, RT5645_I2S2_SDP,
2798 (0x3 << dl_sft), (val_len << dl_sft));
2799 snd_soc_component_update_bits(component, RT5645_ADDA_CLK1, mask_clk, val_clk);
2800 break;
2801 default:
2802 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2803 return -EINVAL;
2804 }
2805
2806 return 0;
2807 }
2808
rt5645_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)2809 static int rt5645_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2810 {
2811 struct snd_soc_component *component = dai->component;
2812 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2813 unsigned int reg_val = 0, pol_sft;
2814
2815 switch (rt5645->codec_type) {
2816 case CODEC_TYPE_RT5650:
2817 pol_sft = 8;
2818 break;
2819 default:
2820 pol_sft = 7;
2821 break;
2822 }
2823
2824 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2825 case SND_SOC_DAIFMT_CBM_CFM:
2826 rt5645->master[dai->id] = 1;
2827 break;
2828 case SND_SOC_DAIFMT_CBS_CFS:
2829 reg_val |= RT5645_I2S_MS_S;
2830 rt5645->master[dai->id] = 0;
2831 break;
2832 default:
2833 return -EINVAL;
2834 }
2835
2836 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2837 case SND_SOC_DAIFMT_NB_NF:
2838 break;
2839 case SND_SOC_DAIFMT_IB_NF:
2840 reg_val |= (1 << pol_sft);
2841 break;
2842 default:
2843 return -EINVAL;
2844 }
2845
2846 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2847 case SND_SOC_DAIFMT_I2S:
2848 break;
2849 case SND_SOC_DAIFMT_LEFT_J:
2850 reg_val |= RT5645_I2S_DF_LEFT;
2851 break;
2852 case SND_SOC_DAIFMT_DSP_A:
2853 reg_val |= RT5645_I2S_DF_PCM_A;
2854 break;
2855 case SND_SOC_DAIFMT_DSP_B:
2856 reg_val |= RT5645_I2S_DF_PCM_B;
2857 break;
2858 default:
2859 return -EINVAL;
2860 }
2861 switch (dai->id) {
2862 case RT5645_AIF1:
2863 snd_soc_component_update_bits(component, RT5645_I2S1_SDP,
2864 RT5645_I2S_MS_MASK | (1 << pol_sft) |
2865 RT5645_I2S_DF_MASK, reg_val);
2866 break;
2867 case RT5645_AIF2:
2868 snd_soc_component_update_bits(component, RT5645_I2S2_SDP,
2869 RT5645_I2S_MS_MASK | (1 << pol_sft) |
2870 RT5645_I2S_DF_MASK, reg_val);
2871 break;
2872 default:
2873 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2874 return -EINVAL;
2875 }
2876 return 0;
2877 }
2878
rt5645_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)2879 static int rt5645_set_dai_sysclk(struct snd_soc_dai *dai,
2880 int clk_id, unsigned int freq, int dir)
2881 {
2882 struct snd_soc_component *component = dai->component;
2883 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2884 unsigned int reg_val = 0;
2885
2886 if (freq == rt5645->sysclk && clk_id == rt5645->sysclk_src)
2887 return 0;
2888
2889 switch (clk_id) {
2890 case RT5645_SCLK_S_MCLK:
2891 reg_val |= RT5645_SCLK_SRC_MCLK;
2892 break;
2893 case RT5645_SCLK_S_PLL1:
2894 reg_val |= RT5645_SCLK_SRC_PLL1;
2895 break;
2896 case RT5645_SCLK_S_RCCLK:
2897 reg_val |= RT5645_SCLK_SRC_RCCLK;
2898 break;
2899 default:
2900 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
2901 return -EINVAL;
2902 }
2903 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2904 RT5645_SCLK_SRC_MASK, reg_val);
2905 rt5645->sysclk = freq;
2906 rt5645->sysclk_src = clk_id;
2907
2908 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
2909
2910 return 0;
2911 }
2912
rt5645_set_dai_pll(struct snd_soc_dai * dai,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)2913 static int rt5645_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
2914 unsigned int freq_in, unsigned int freq_out)
2915 {
2916 struct snd_soc_component *component = dai->component;
2917 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2918 struct rl6231_pll_code pll_code;
2919 int ret;
2920
2921 if (source == rt5645->pll_src && freq_in == rt5645->pll_in &&
2922 freq_out == rt5645->pll_out)
2923 return 0;
2924
2925 if (!freq_in || !freq_out) {
2926 dev_dbg(component->dev, "PLL disabled\n");
2927
2928 rt5645->pll_in = 0;
2929 rt5645->pll_out = 0;
2930 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2931 RT5645_SCLK_SRC_MASK, RT5645_SCLK_SRC_MCLK);
2932 return 0;
2933 }
2934
2935 switch (source) {
2936 case RT5645_PLL1_S_MCLK:
2937 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2938 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_MCLK);
2939 break;
2940 case RT5645_PLL1_S_BCLK1:
2941 case RT5645_PLL1_S_BCLK2:
2942 switch (dai->id) {
2943 case RT5645_AIF1:
2944 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2945 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK1);
2946 break;
2947 case RT5645_AIF2:
2948 snd_soc_component_update_bits(component, RT5645_GLB_CLK,
2949 RT5645_PLL1_SRC_MASK, RT5645_PLL1_SRC_BCLK2);
2950 break;
2951 default:
2952 dev_err(component->dev, "Invalid dai->id: %d\n", dai->id);
2953 return -EINVAL;
2954 }
2955 break;
2956 default:
2957 dev_err(component->dev, "Unknown PLL source %d\n", source);
2958 return -EINVAL;
2959 }
2960
2961 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
2962 if (ret < 0) {
2963 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
2964 return ret;
2965 }
2966
2967 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
2968 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
2969 pll_code.n_code, pll_code.k_code);
2970
2971 snd_soc_component_write(component, RT5645_PLL_CTRL1,
2972 pll_code.n_code << RT5645_PLL_N_SFT | pll_code.k_code);
2973 snd_soc_component_write(component, RT5645_PLL_CTRL2,
2974 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5645_PLL_M_SFT |
2975 pll_code.m_bp << RT5645_PLL_M_BP_SFT);
2976
2977 rt5645->pll_in = freq_in;
2978 rt5645->pll_out = freq_out;
2979 rt5645->pll_src = source;
2980
2981 return 0;
2982 }
2983
rt5645_set_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)2984 static int rt5645_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
2985 unsigned int rx_mask, int slots, int slot_width)
2986 {
2987 struct snd_soc_component *component = dai->component;
2988 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
2989 unsigned int i_slot_sft, o_slot_sft, i_width_sht, o_width_sht, en_sft;
2990 unsigned int mask, val = 0;
2991
2992 switch (rt5645->codec_type) {
2993 case CODEC_TYPE_RT5650:
2994 en_sft = 15;
2995 i_slot_sft = 10;
2996 o_slot_sft = 8;
2997 i_width_sht = 6;
2998 o_width_sht = 4;
2999 mask = 0x8ff0;
3000 break;
3001 default:
3002 en_sft = 14;
3003 i_slot_sft = o_slot_sft = 12;
3004 i_width_sht = o_width_sht = 10;
3005 mask = 0x7c00;
3006 break;
3007 }
3008 if (rx_mask || tx_mask) {
3009 val |= (1 << en_sft);
3010 if (rt5645->codec_type == CODEC_TYPE_RT5645)
3011 snd_soc_component_update_bits(component, RT5645_BASS_BACK,
3012 RT5645_G_BB_BST_MASK, RT5645_G_BB_BST_25DB);
3013 }
3014
3015 switch (slots) {
3016 case 4:
3017 val |= (1 << i_slot_sft) | (1 << o_slot_sft);
3018 break;
3019 case 6:
3020 val |= (2 << i_slot_sft) | (2 << o_slot_sft);
3021 break;
3022 case 8:
3023 val |= (3 << i_slot_sft) | (3 << o_slot_sft);
3024 break;
3025 case 2:
3026 default:
3027 break;
3028 }
3029
3030 switch (slot_width) {
3031 case 20:
3032 val |= (1 << i_width_sht) | (1 << o_width_sht);
3033 break;
3034 case 24:
3035 val |= (2 << i_width_sht) | (2 << o_width_sht);
3036 break;
3037 case 32:
3038 val |= (3 << i_width_sht) | (3 << o_width_sht);
3039 break;
3040 case 16:
3041 default:
3042 break;
3043 }
3044
3045 snd_soc_component_update_bits(component, RT5645_TDM_CTRL_1, mask, val);
3046
3047 return 0;
3048 }
3049
rt5645_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)3050 static int rt5645_set_bias_level(struct snd_soc_component *component,
3051 enum snd_soc_bias_level level)
3052 {
3053 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3054
3055 switch (level) {
3056 case SND_SOC_BIAS_PREPARE:
3057 if (SND_SOC_BIAS_STANDBY == snd_soc_component_get_bias_level(component)) {
3058 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3059 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3060 RT5645_PWR_BG | RT5645_PWR_VREF2,
3061 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3062 RT5645_PWR_BG | RT5645_PWR_VREF2);
3063 mdelay(10);
3064 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3065 RT5645_PWR_FV1 | RT5645_PWR_FV2,
3066 RT5645_PWR_FV1 | RT5645_PWR_FV2);
3067 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,
3068 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3069 }
3070 break;
3071
3072 case SND_SOC_BIAS_STANDBY:
3073 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3074 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3075 RT5645_PWR_BG | RT5645_PWR_VREF2,
3076 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3077 RT5645_PWR_BG | RT5645_PWR_VREF2);
3078 mdelay(10);
3079 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3080 RT5645_PWR_FV1 | RT5645_PWR_FV2,
3081 RT5645_PWR_FV1 | RT5645_PWR_FV2);
3082 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
3083 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1140);
3084 msleep(40);
3085 if (rt5645->en_button_func)
3086 queue_delayed_work(system_power_efficient_wq,
3087 &rt5645->jack_detect_work,
3088 msecs_to_jiffies(0));
3089 }
3090 break;
3091
3092 case SND_SOC_BIAS_OFF:
3093 snd_soc_component_write(component, RT5645_DEPOP_M2, 0x1100);
3094 if (!rt5645->en_button_func)
3095 snd_soc_component_update_bits(component, RT5645_GEN_CTRL1,
3096 RT5645_DIG_GATE_CTRL, 0);
3097 snd_soc_component_update_bits(component, RT5645_PWR_ANLG1,
3098 RT5645_PWR_VREF1 | RT5645_PWR_MB |
3099 RT5645_PWR_BG | RT5645_PWR_VREF2 |
3100 RT5645_PWR_FV1 | RT5645_PWR_FV2, 0x0);
3101 break;
3102
3103 default:
3104 break;
3105 }
3106
3107 return 0;
3108 }
3109
rt5645_enable_push_button_irq(struct snd_soc_component * component,bool enable)3110 static void rt5645_enable_push_button_irq(struct snd_soc_component *component,
3111 bool enable)
3112 {
3113 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3114
3115 if (enable) {
3116 snd_soc_dapm_force_enable_pin(dapm, "ADC L power");
3117 snd_soc_dapm_force_enable_pin(dapm, "ADC R power");
3118 snd_soc_dapm_sync(dapm);
3119
3120 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD1, 0x3, 0x3);
3121 snd_soc_component_update_bits(component,
3122 RT5645_INT_IRQ_ST, 0x8, 0x8);
3123 snd_soc_component_update_bits(component,
3124 RT5650_4BTN_IL_CMD2, 0x8000, 0x8000);
3125 snd_soc_component_read(component, RT5650_4BTN_IL_CMD1);
3126 pr_debug("%s read %x = %x\n", __func__, RT5650_4BTN_IL_CMD1,
3127 snd_soc_component_read(component, RT5650_4BTN_IL_CMD1));
3128 } else {
3129 snd_soc_component_update_bits(component, RT5650_4BTN_IL_CMD2, 0x8000, 0x0);
3130 snd_soc_component_update_bits(component, RT5645_INT_IRQ_ST, 0x8, 0x0);
3131
3132 snd_soc_dapm_disable_pin(dapm, "ADC L power");
3133 snd_soc_dapm_disable_pin(dapm, "ADC R power");
3134 snd_soc_dapm_sync(dapm);
3135 }
3136 }
3137
rt5645_jack_detect(struct snd_soc_component * component,int jack_insert)3138 static int rt5645_jack_detect(struct snd_soc_component *component, int jack_insert)
3139 {
3140 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3141 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3142 unsigned int val;
3143
3144 if (jack_insert) {
3145 regmap_write(rt5645->regmap, RT5645_CHARGE_PUMP, 0x0e06);
3146
3147 /* for jack type detect */
3148 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3149 snd_soc_dapm_force_enable_pin(dapm, "Mic Det Power");
3150 snd_soc_dapm_sync(dapm);
3151 if (!dapm->card->instantiated) {
3152 /* Power up necessary bits for JD if dapm is
3153 not ready yet */
3154 regmap_update_bits(rt5645->regmap, RT5645_PWR_ANLG1,
3155 RT5645_PWR_MB | RT5645_PWR_VREF2,
3156 RT5645_PWR_MB | RT5645_PWR_VREF2);
3157 regmap_update_bits(rt5645->regmap, RT5645_PWR_MIXER,
3158 RT5645_PWR_LDO2, RT5645_PWR_LDO2);
3159 regmap_update_bits(rt5645->regmap, RT5645_PWR_VOL,
3160 RT5645_PWR_MIC_DET, RT5645_PWR_MIC_DET);
3161 }
3162
3163 regmap_write(rt5645->regmap, RT5645_JD_CTRL3, 0x00f0);
3164 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3165 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3166 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3167 RT5645_CBJ_BST1_EN, RT5645_CBJ_BST1_EN);
3168 msleep(100);
3169 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3170 RT5645_CBJ_MN_JD, 0);
3171
3172 msleep(600);
3173 regmap_read(rt5645->regmap, RT5645_IN1_CTRL3, &val);
3174 val &= 0x7;
3175 dev_dbg(component->dev, "val = %d\n", val);
3176
3177 if (val == 1 || val == 2) {
3178 rt5645->jack_type = SND_JACK_HEADSET;
3179 if (rt5645->en_button_func) {
3180 rt5645_enable_push_button_irq(component, true);
3181 }
3182 } else {
3183 if (rt5645->en_button_func)
3184 rt5645_enable_push_button_irq(component, false);
3185 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3186 snd_soc_dapm_sync(dapm);
3187 rt5645->jack_type = SND_JACK_HEADPHONE;
3188 }
3189 if (rt5645->pdata.level_trigger_irq)
3190 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3191 RT5645_JD_1_1_MASK, RT5645_JD_1_1_NOR);
3192 } else { /* jack out */
3193 rt5645->jack_type = 0;
3194
3195 regmap_update_bits(rt5645->regmap, RT5645_HP_VOL,
3196 RT5645_L_MUTE | RT5645_R_MUTE,
3197 RT5645_L_MUTE | RT5645_R_MUTE);
3198 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2,
3199 RT5645_CBJ_MN_JD, RT5645_CBJ_MN_JD);
3200 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1,
3201 RT5645_CBJ_BST1_EN, 0);
3202
3203 if (rt5645->en_button_func)
3204 rt5645_enable_push_button_irq(component, false);
3205
3206 if (rt5645->pdata.jd_mode == 0)
3207 snd_soc_dapm_disable_pin(dapm, "LDO2");
3208 snd_soc_dapm_disable_pin(dapm, "Mic Det Power");
3209 snd_soc_dapm_sync(dapm);
3210 if (rt5645->pdata.level_trigger_irq)
3211 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
3212 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
3213 }
3214
3215 return rt5645->jack_type;
3216 }
3217
rt5645_button_detect(struct snd_soc_component * component)3218 static int rt5645_button_detect(struct snd_soc_component *component)
3219 {
3220 int btn_type, val;
3221
3222 val = snd_soc_component_read(component, RT5650_4BTN_IL_CMD1);
3223 pr_debug("val=0x%x\n", val);
3224 btn_type = val & 0xfff0;
3225 snd_soc_component_write(component, RT5650_4BTN_IL_CMD1, val);
3226
3227 return btn_type;
3228 }
3229
3230 static irqreturn_t rt5645_irq(int irq, void *data);
3231
rt5645_set_jack_detect(struct snd_soc_component * component,struct snd_soc_jack * hp_jack,struct snd_soc_jack * mic_jack,struct snd_soc_jack * btn_jack)3232 int rt5645_set_jack_detect(struct snd_soc_component *component,
3233 struct snd_soc_jack *hp_jack, struct snd_soc_jack *mic_jack,
3234 struct snd_soc_jack *btn_jack)
3235 {
3236 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3237
3238 rt5645->hp_jack = hp_jack;
3239 rt5645->mic_jack = mic_jack;
3240 rt5645->btn_jack = btn_jack;
3241 if (rt5645->btn_jack && rt5645->codec_type == CODEC_TYPE_RT5650) {
3242 rt5645->en_button_func = true;
3243 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3244 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
3245 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL1,
3246 RT5645_DIG_GATE_CTRL, RT5645_DIG_GATE_CTRL);
3247 regmap_update_bits(rt5645->regmap, RT5645_DEPOP_M1,
3248 RT5645_HP_CB_MASK, RT5645_HP_CB_PU);
3249 }
3250 rt5645_irq(0, rt5645);
3251
3252 return 0;
3253 }
3254 EXPORT_SYMBOL_GPL(rt5645_set_jack_detect);
3255
rt5645_jack_detect_work(struct work_struct * work)3256 static void rt5645_jack_detect_work(struct work_struct *work)
3257 {
3258 struct rt5645_priv *rt5645 =
3259 container_of(work, struct rt5645_priv, jack_detect_work.work);
3260 int val, btn_type, gpio_state = 0, report = 0;
3261
3262 if (!rt5645->component)
3263 return;
3264
3265 mutex_lock(&rt5645->jd_mutex);
3266
3267 switch (rt5645->pdata.jd_mode) {
3268 case 0: /* Not using rt5645 JD */
3269 if (rt5645->gpiod_hp_det) {
3270 gpio_state = gpiod_get_value(rt5645->gpiod_hp_det);
3271 dev_dbg(rt5645->component->dev, "gpio_state = %d\n",
3272 gpio_state);
3273 report = rt5645_jack_detect(rt5645->component, gpio_state);
3274 }
3275 snd_soc_jack_report(rt5645->hp_jack,
3276 report, SND_JACK_HEADPHONE);
3277 snd_soc_jack_report(rt5645->mic_jack,
3278 report, SND_JACK_MICROPHONE);
3279 mutex_unlock(&rt5645->jd_mutex);
3280 return;
3281 case 4:
3282 val = snd_soc_component_read(rt5645->component, RT5645_A_JD_CTRL1) & 0x0020;
3283 break;
3284 default: /* read rt5645 jd1_1 status */
3285 val = snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x1000;
3286 break;
3287
3288 }
3289
3290 if (!val && (rt5645->jack_type == 0)) { /* jack in */
3291 report = rt5645_jack_detect(rt5645->component, 1);
3292 } else if (!val && rt5645->jack_type == SND_JACK_HEADSET) {
3293 /* for push button and jack out */
3294 btn_type = 0;
3295 if (snd_soc_component_read(rt5645->component, RT5645_INT_IRQ_ST) & 0x4) {
3296 /* button pressed */
3297 report = SND_JACK_HEADSET;
3298 btn_type = rt5645_button_detect(rt5645->component);
3299 /* rt5650 can report three kinds of button behavior,
3300 one click, double click and hold. However,
3301 currently we will report button pressed/released
3302 event. So all the three button behaviors are
3303 treated as button pressed. */
3304 switch (btn_type) {
3305 case 0x8000:
3306 case 0x4000:
3307 case 0x2000:
3308 report |= SND_JACK_BTN_0;
3309 break;
3310 case 0x1000:
3311 case 0x0800:
3312 case 0x0400:
3313 report |= SND_JACK_BTN_1;
3314 break;
3315 case 0x0200:
3316 case 0x0100:
3317 case 0x0080:
3318 report |= SND_JACK_BTN_2;
3319 break;
3320 case 0x0040:
3321 case 0x0020:
3322 case 0x0010:
3323 report |= SND_JACK_BTN_3;
3324 break;
3325 case 0x0000: /* unpressed */
3326 break;
3327 default:
3328 dev_err(rt5645->component->dev,
3329 "Unexpected button code 0x%04x\n",
3330 btn_type);
3331 break;
3332 }
3333 }
3334 if (btn_type == 0)/* button release */
3335 report = rt5645->jack_type;
3336 else {
3337 mod_timer(&rt5645->btn_check_timer,
3338 msecs_to_jiffies(100));
3339 }
3340 } else {
3341 /* jack out */
3342 report = 0;
3343 snd_soc_component_update_bits(rt5645->component,
3344 RT5645_INT_IRQ_ST, 0x1, 0x0);
3345 rt5645_jack_detect(rt5645->component, 0);
3346 }
3347
3348 mutex_unlock(&rt5645->jd_mutex);
3349
3350 snd_soc_jack_report(rt5645->hp_jack, report, SND_JACK_HEADPHONE);
3351 snd_soc_jack_report(rt5645->mic_jack, report, SND_JACK_MICROPHONE);
3352 if (rt5645->en_button_func)
3353 snd_soc_jack_report(rt5645->btn_jack,
3354 report, SND_JACK_BTN_0 | SND_JACK_BTN_1 |
3355 SND_JACK_BTN_2 | SND_JACK_BTN_3);
3356 }
3357
rt5645_rcclock_work(struct work_struct * work)3358 static void rt5645_rcclock_work(struct work_struct *work)
3359 {
3360 struct rt5645_priv *rt5645 =
3361 container_of(work, struct rt5645_priv, rcclock_work.work);
3362
3363 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
3364 RT5645_PWR_CLK25M_MASK, RT5645_PWR_CLK25M_PD);
3365 }
3366
rt5645_irq(int irq,void * data)3367 static irqreturn_t rt5645_irq(int irq, void *data)
3368 {
3369 struct rt5645_priv *rt5645 = data;
3370
3371 queue_delayed_work(system_power_efficient_wq,
3372 &rt5645->jack_detect_work, msecs_to_jiffies(250));
3373
3374 return IRQ_HANDLED;
3375 }
3376
rt5645_btn_check_callback(struct timer_list * t)3377 static void rt5645_btn_check_callback(struct timer_list *t)
3378 {
3379 struct rt5645_priv *rt5645 = from_timer(rt5645, t, btn_check_timer);
3380
3381 queue_delayed_work(system_power_efficient_wq,
3382 &rt5645->jack_detect_work, msecs_to_jiffies(5));
3383 }
3384
rt5645_probe(struct snd_soc_component * component)3385 static int rt5645_probe(struct snd_soc_component *component)
3386 {
3387 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
3388 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3389
3390 rt5645->component = component;
3391
3392 switch (rt5645->codec_type) {
3393 case CODEC_TYPE_RT5645:
3394 snd_soc_dapm_new_controls(dapm,
3395 rt5645_specific_dapm_widgets,
3396 ARRAY_SIZE(rt5645_specific_dapm_widgets));
3397 snd_soc_dapm_add_routes(dapm,
3398 rt5645_specific_dapm_routes,
3399 ARRAY_SIZE(rt5645_specific_dapm_routes));
3400 if (rt5645->v_id < 3) {
3401 snd_soc_dapm_add_routes(dapm,
3402 rt5645_old_dapm_routes,
3403 ARRAY_SIZE(rt5645_old_dapm_routes));
3404 }
3405 break;
3406 case CODEC_TYPE_RT5650:
3407 snd_soc_dapm_new_controls(dapm,
3408 rt5650_specific_dapm_widgets,
3409 ARRAY_SIZE(rt5650_specific_dapm_widgets));
3410 snd_soc_dapm_add_routes(dapm,
3411 rt5650_specific_dapm_routes,
3412 ARRAY_SIZE(rt5650_specific_dapm_routes));
3413 break;
3414 }
3415
3416 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
3417
3418 /* for JD function */
3419 if (rt5645->pdata.jd_mode) {
3420 snd_soc_dapm_force_enable_pin(dapm, "JD Power");
3421 snd_soc_dapm_force_enable_pin(dapm, "LDO2");
3422 snd_soc_dapm_sync(dapm);
3423 }
3424
3425 if (rt5645->pdata.long_name)
3426 component->card->long_name = rt5645->pdata.long_name;
3427
3428 rt5645->eq_param = devm_kcalloc(component->dev,
3429 RT5645_HWEQ_NUM, sizeof(struct rt5645_eq_param_s),
3430 GFP_KERNEL);
3431
3432 if (!rt5645->eq_param)
3433 return -ENOMEM;
3434
3435 return 0;
3436 }
3437
rt5645_remove(struct snd_soc_component * component)3438 static void rt5645_remove(struct snd_soc_component *component)
3439 {
3440 rt5645_reset(component);
3441 }
3442
3443 #ifdef CONFIG_PM
rt5645_suspend(struct snd_soc_component * component)3444 static int rt5645_suspend(struct snd_soc_component *component)
3445 {
3446 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3447
3448 regcache_cache_only(rt5645->regmap, true);
3449 regcache_mark_dirty(rt5645->regmap);
3450
3451 return 0;
3452 }
3453
rt5645_resume(struct snd_soc_component * component)3454 static int rt5645_resume(struct snd_soc_component *component)
3455 {
3456 struct rt5645_priv *rt5645 = snd_soc_component_get_drvdata(component);
3457
3458 regcache_cache_only(rt5645->regmap, false);
3459 regcache_sync(rt5645->regmap);
3460
3461 return 0;
3462 }
3463 #else
3464 #define rt5645_suspend NULL
3465 #define rt5645_resume NULL
3466 #endif
3467
3468 #define RT5645_STEREO_RATES SNDRV_PCM_RATE_8000_96000
3469 #define RT5645_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
3470 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
3471
3472 static const struct snd_soc_dai_ops rt5645_aif_dai_ops = {
3473 .hw_params = rt5645_hw_params,
3474 .set_fmt = rt5645_set_dai_fmt,
3475 .set_sysclk = rt5645_set_dai_sysclk,
3476 .set_tdm_slot = rt5645_set_tdm_slot,
3477 .set_pll = rt5645_set_dai_pll,
3478 };
3479
3480 static struct snd_soc_dai_driver rt5645_dai[] = {
3481 {
3482 .name = "rt5645-aif1",
3483 .id = RT5645_AIF1,
3484 .playback = {
3485 .stream_name = "AIF1 Playback",
3486 .channels_min = 1,
3487 .channels_max = 2,
3488 .rates = RT5645_STEREO_RATES,
3489 .formats = RT5645_FORMATS,
3490 },
3491 .capture = {
3492 .stream_name = "AIF1 Capture",
3493 .channels_min = 1,
3494 .channels_max = 4,
3495 .rates = RT5645_STEREO_RATES,
3496 .formats = RT5645_FORMATS,
3497 },
3498 .ops = &rt5645_aif_dai_ops,
3499 },
3500 {
3501 .name = "rt5645-aif2",
3502 .id = RT5645_AIF2,
3503 .playback = {
3504 .stream_name = "AIF2 Playback",
3505 .channels_min = 1,
3506 .channels_max = 2,
3507 .rates = RT5645_STEREO_RATES,
3508 .formats = RT5645_FORMATS,
3509 },
3510 .capture = {
3511 .stream_name = "AIF2 Capture",
3512 .channels_min = 1,
3513 .channels_max = 2,
3514 .rates = RT5645_STEREO_RATES,
3515 .formats = RT5645_FORMATS,
3516 },
3517 .ops = &rt5645_aif_dai_ops,
3518 },
3519 };
3520
3521 static const struct snd_soc_component_driver soc_component_dev_rt5645 = {
3522 .probe = rt5645_probe,
3523 .remove = rt5645_remove,
3524 .suspend = rt5645_suspend,
3525 .resume = rt5645_resume,
3526 .set_bias_level = rt5645_set_bias_level,
3527 .controls = rt5645_snd_controls,
3528 .num_controls = ARRAY_SIZE(rt5645_snd_controls),
3529 .dapm_widgets = rt5645_dapm_widgets,
3530 .num_dapm_widgets = ARRAY_SIZE(rt5645_dapm_widgets),
3531 .dapm_routes = rt5645_dapm_routes,
3532 .num_dapm_routes = ARRAY_SIZE(rt5645_dapm_routes),
3533 .use_pmdown_time = 1,
3534 .endianness = 1,
3535 .non_legacy_dai_naming = 1,
3536 };
3537
3538 static const struct regmap_config rt5645_regmap = {
3539 .reg_bits = 8,
3540 .val_bits = 16,
3541 .use_single_read = true,
3542 .use_single_write = true,
3543 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3544 RT5645_PR_SPACING),
3545 .volatile_reg = rt5645_volatile_register,
3546 .readable_reg = rt5645_readable_register,
3547
3548 .cache_type = REGCACHE_RBTREE,
3549 .reg_defaults = rt5645_reg,
3550 .num_reg_defaults = ARRAY_SIZE(rt5645_reg),
3551 .ranges = rt5645_ranges,
3552 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3553 };
3554
3555 static const struct regmap_config rt5650_regmap = {
3556 .reg_bits = 8,
3557 .val_bits = 16,
3558 .use_single_read = true,
3559 .use_single_write = true,
3560 .max_register = RT5645_VENDOR_ID2 + 1 + (ARRAY_SIZE(rt5645_ranges) *
3561 RT5645_PR_SPACING),
3562 .volatile_reg = rt5645_volatile_register,
3563 .readable_reg = rt5645_readable_register,
3564
3565 .cache_type = REGCACHE_RBTREE,
3566 .reg_defaults = rt5650_reg,
3567 .num_reg_defaults = ARRAY_SIZE(rt5650_reg),
3568 .ranges = rt5645_ranges,
3569 .num_ranges = ARRAY_SIZE(rt5645_ranges),
3570 };
3571
3572 static const struct regmap_config temp_regmap = {
3573 .name="nocache",
3574 .reg_bits = 8,
3575 .val_bits = 16,
3576 .use_single_read = true,
3577 .use_single_write = true,
3578 .max_register = RT5645_VENDOR_ID2 + 1,
3579 .cache_type = REGCACHE_NONE,
3580 };
3581
3582 static const struct i2c_device_id rt5645_i2c_id[] = {
3583 { "rt5645", 0 },
3584 { "rt5650", 0 },
3585 { }
3586 };
3587 MODULE_DEVICE_TABLE(i2c, rt5645_i2c_id);
3588
3589 #ifdef CONFIG_OF
3590 static const struct of_device_id rt5645_of_match[] = {
3591 { .compatible = "realtek,rt5645", },
3592 { .compatible = "realtek,rt5650", },
3593 { }
3594 };
3595 MODULE_DEVICE_TABLE(of, rt5645_of_match);
3596 #endif
3597
3598 #ifdef CONFIG_ACPI
3599 static const struct acpi_device_id rt5645_acpi_match[] = {
3600 { "10EC5645", 0 },
3601 { "10EC5648", 0 },
3602 { "10EC5650", 0 },
3603 { "10EC5640", 0 },
3604 { "10EC3270", 0 },
3605 {},
3606 };
3607 MODULE_DEVICE_TABLE(acpi, rt5645_acpi_match);
3608 #endif
3609
3610 static const struct rt5645_platform_data intel_braswell_platform_data = {
3611 .dmic1_data_pin = RT5645_DMIC1_DISABLE,
3612 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3613 .jd_mode = 3,
3614 };
3615
3616 static const struct rt5645_platform_data buddy_platform_data = {
3617 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
3618 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3619 .jd_mode = 4,
3620 .level_trigger_irq = true,
3621 };
3622
3623 static const struct rt5645_platform_data gpd_win_platform_data = {
3624 .jd_mode = 3,
3625 .inv_jd1_1 = true,
3626 .long_name = "gpd-win-pocket-rt5645",
3627 /* The GPD pocket has a diff. mic, for the win this does not matter. */
3628 .in2_diff = true,
3629 };
3630
3631 static const struct rt5645_platform_data asus_t100ha_platform_data = {
3632 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N,
3633 .dmic2_data_pin = RT5645_DMIC2_DISABLE,
3634 .jd_mode = 3,
3635 .inv_jd1_1 = true,
3636 };
3637
3638 static const struct rt5645_platform_data asus_t101ha_platform_data = {
3639 .dmic1_data_pin = RT5645_DMIC_DATA_IN2N,
3640 .dmic2_data_pin = RT5645_DMIC2_DISABLE,
3641 .jd_mode = 3,
3642 };
3643
3644 static const struct rt5645_platform_data lenovo_ideapad_miix_310_pdata = {
3645 .jd_mode = 3,
3646 .in2_diff = true,
3647 };
3648
3649 static const struct rt5645_platform_data jd_mode3_platform_data = {
3650 .jd_mode = 3,
3651 };
3652
3653 static const struct rt5645_platform_data lattepanda_board_platform_data = {
3654 .jd_mode = 2,
3655 .inv_jd1_1 = true
3656 };
3657
3658 static const struct rt5645_platform_data kahlee_platform_data = {
3659 .dmic1_data_pin = RT5645_DMIC_DATA_GPIO5,
3660 .dmic2_data_pin = RT5645_DMIC_DATA_IN2P,
3661 .jd_mode = 3,
3662 };
3663
3664 static const struct dmi_system_id dmi_platform_data[] = {
3665 {
3666 .ident = "Chrome Buddy",
3667 .matches = {
3668 DMI_MATCH(DMI_PRODUCT_NAME, "Buddy"),
3669 },
3670 .driver_data = (void *)&buddy_platform_data,
3671 },
3672 {
3673 .ident = "Intel Strago",
3674 .matches = {
3675 DMI_MATCH(DMI_PRODUCT_NAME, "Strago"),
3676 },
3677 .driver_data = (void *)&intel_braswell_platform_data,
3678 },
3679 {
3680 .ident = "Google Chrome",
3681 .matches = {
3682 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
3683 },
3684 .driver_data = (void *)&intel_braswell_platform_data,
3685 },
3686 {
3687 .ident = "Google Setzer",
3688 .matches = {
3689 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"),
3690 },
3691 .driver_data = (void *)&intel_braswell_platform_data,
3692 },
3693 {
3694 .ident = "Microsoft Surface 3",
3695 .matches = {
3696 DMI_MATCH(DMI_PRODUCT_NAME, "Surface 3"),
3697 },
3698 .driver_data = (void *)&intel_braswell_platform_data,
3699 },
3700 {
3701 /*
3702 * Match for the GPDwin which unfortunately uses somewhat
3703 * generic dmi strings, which is why we test for 4 strings.
3704 * Comparing against 23 other byt/cht boards, board_vendor
3705 * and board_name are unique to the GPDwin, where as only one
3706 * other board has the same board_serial and 3 others have
3707 * the same default product_name. Also the GPDwin is the
3708 * only device to have both board_ and product_name not set.
3709 */
3710 .ident = "GPD Win / Pocket",
3711 .matches = {
3712 DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
3713 DMI_MATCH(DMI_BOARD_NAME, "Default string"),
3714 DMI_MATCH(DMI_BOARD_SERIAL, "Default string"),
3715 DMI_MATCH(DMI_PRODUCT_NAME, "Default string"),
3716 },
3717 .driver_data = (void *)&gpd_win_platform_data,
3718 },
3719 {
3720 .ident = "ASUS T100HAN",
3721 .matches = {
3722 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
3723 DMI_MATCH(DMI_PRODUCT_NAME, "T100HAN"),
3724 },
3725 .driver_data = (void *)&asus_t100ha_platform_data,
3726 },
3727 {
3728 .ident = "ASUS T101HA",
3729 .matches = {
3730 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK COMPUTER INC."),
3731 DMI_MATCH(DMI_PRODUCT_NAME, "T101HA"),
3732 },
3733 .driver_data = (void *)&asus_t101ha_platform_data,
3734 },
3735 {
3736 .ident = "MINIX Z83-4",
3737 .matches = {
3738 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MINIX"),
3739 DMI_MATCH(DMI_PRODUCT_NAME, "Z83-4"),
3740 },
3741 .driver_data = (void *)&jd_mode3_platform_data,
3742 },
3743 {
3744 .ident = "Teclast X80 Pro",
3745 .matches = {
3746 DMI_MATCH(DMI_SYS_VENDOR, "TECLAST"),
3747 DMI_MATCH(DMI_PRODUCT_NAME, "X80 Pro"),
3748 },
3749 .driver_data = (void *)&jd_mode3_platform_data,
3750 },
3751 {
3752 .ident = "Lenovo Ideapad Miix 310",
3753 .matches = {
3754 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),
3755 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80SG"),
3756 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "MIIX 310-10ICR"),
3757 },
3758 .driver_data = (void *)&lenovo_ideapad_miix_310_pdata,
3759 },
3760 {
3761 .ident = "Lenovo Ideapad Miix 320",
3762 .matches = {
3763 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "LENOVO"),
3764 DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "80XF"),
3765 DMI_EXACT_MATCH(DMI_PRODUCT_VERSION, "Lenovo MIIX 320-10ICR"),
3766 },
3767 .driver_data = (void *)&intel_braswell_platform_data,
3768 },
3769 {
3770 .ident = "LattePanda board",
3771 .matches = {
3772 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
3773 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
3774 DMI_EXACT_MATCH(DMI_BOARD_VERSION, "Default string"),
3775 },
3776 .driver_data = (void *)&lattepanda_board_platform_data,
3777 },
3778 {
3779 .ident = "Chrome Kahlee",
3780 .matches = {
3781 DMI_MATCH(DMI_PRODUCT_NAME, "Kahlee"),
3782 },
3783 .driver_data = (void *)&kahlee_platform_data,
3784 },
3785 {
3786 .ident = "Medion E1239T",
3787 .matches = {
3788 DMI_EXACT_MATCH(DMI_SYS_VENDOR, "MEDION"),
3789 DMI_MATCH(DMI_PRODUCT_NAME, "E1239T MD60568"),
3790 },
3791 .driver_data = (void *)&intel_braswell_platform_data,
3792 },
3793 { }
3794 };
3795
rt5645_check_dp(struct device * dev)3796 static bool rt5645_check_dp(struct device *dev)
3797 {
3798 if (device_property_present(dev, "realtek,in2-differential") ||
3799 device_property_present(dev, "realtek,dmic1-data-pin") ||
3800 device_property_present(dev, "realtek,dmic2-data-pin") ||
3801 device_property_present(dev, "realtek,jd-mode"))
3802 return true;
3803
3804 return false;
3805 }
3806
rt5645_parse_dt(struct rt5645_priv * rt5645,struct device * dev)3807 static int rt5645_parse_dt(struct rt5645_priv *rt5645, struct device *dev)
3808 {
3809 rt5645->pdata.in2_diff = device_property_read_bool(dev,
3810 "realtek,in2-differential");
3811 device_property_read_u32(dev,
3812 "realtek,dmic1-data-pin", &rt5645->pdata.dmic1_data_pin);
3813 device_property_read_u32(dev,
3814 "realtek,dmic2-data-pin", &rt5645->pdata.dmic2_data_pin);
3815 device_property_read_u32(dev,
3816 "realtek,jd-mode", &rt5645->pdata.jd_mode);
3817
3818 return 0;
3819 }
3820
rt5645_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)3821 static int rt5645_i2c_probe(struct i2c_client *i2c,
3822 const struct i2c_device_id *id)
3823 {
3824 struct rt5645_platform_data *pdata = dev_get_platdata(&i2c->dev);
3825 const struct dmi_system_id *dmi_data;
3826 struct rt5645_priv *rt5645;
3827 int ret, i;
3828 unsigned int val;
3829 struct regmap *regmap;
3830
3831 rt5645 = devm_kzalloc(&i2c->dev, sizeof(struct rt5645_priv),
3832 GFP_KERNEL);
3833 if (rt5645 == NULL)
3834 return -ENOMEM;
3835
3836 rt5645->i2c = i2c;
3837 i2c_set_clientdata(i2c, rt5645);
3838
3839 dmi_data = dmi_first_match(dmi_platform_data);
3840 if (dmi_data) {
3841 dev_info(&i2c->dev, "Detected %s platform\n", dmi_data->ident);
3842 pdata = dmi_data->driver_data;
3843 }
3844
3845 if (pdata)
3846 rt5645->pdata = *pdata;
3847 else if (rt5645_check_dp(&i2c->dev))
3848 rt5645_parse_dt(rt5645, &i2c->dev);
3849 else
3850 rt5645->pdata = jd_mode3_platform_data;
3851
3852 if (quirk != -1) {
3853 rt5645->pdata.in2_diff = QUIRK_IN2_DIFF(quirk);
3854 rt5645->pdata.level_trigger_irq = QUIRK_LEVEL_IRQ(quirk);
3855 rt5645->pdata.inv_jd1_1 = QUIRK_INV_JD1_1(quirk);
3856 rt5645->pdata.jd_mode = QUIRK_JD_MODE(quirk);
3857 rt5645->pdata.dmic1_data_pin = QUIRK_DMIC1_DATA_PIN(quirk);
3858 rt5645->pdata.dmic2_data_pin = QUIRK_DMIC2_DATA_PIN(quirk);
3859 }
3860
3861 rt5645->gpiod_hp_det = devm_gpiod_get_optional(&i2c->dev, "hp-detect",
3862 GPIOD_IN);
3863
3864 if (IS_ERR(rt5645->gpiod_hp_det)) {
3865 dev_info(&i2c->dev, "failed to initialize gpiod\n");
3866 ret = PTR_ERR(rt5645->gpiod_hp_det);
3867 /*
3868 * Continue if optional gpiod is missing, bail for all other
3869 * errors, including -EPROBE_DEFER
3870 */
3871 if (ret != -ENOENT)
3872 return ret;
3873 }
3874
3875 for (i = 0; i < ARRAY_SIZE(rt5645->supplies); i++)
3876 rt5645->supplies[i].supply = rt5645_supply_names[i];
3877
3878 ret = devm_regulator_bulk_get(&i2c->dev,
3879 ARRAY_SIZE(rt5645->supplies),
3880 rt5645->supplies);
3881 if (ret) {
3882 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3883 return ret;
3884 }
3885
3886 ret = regulator_bulk_enable(ARRAY_SIZE(rt5645->supplies),
3887 rt5645->supplies);
3888 if (ret) {
3889 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3890 return ret;
3891 }
3892
3893 regmap = devm_regmap_init_i2c(i2c, &temp_regmap);
3894 if (IS_ERR(regmap)) {
3895 ret = PTR_ERR(regmap);
3896 dev_err(&i2c->dev, "Failed to allocate temp register map: %d\n",
3897 ret);
3898 return ret;
3899 }
3900
3901 /*
3902 * Read after 400msec, as it is the interval required between
3903 * read and power On.
3904 */
3905 msleep(TIME_TO_POWER_MS);
3906 regmap_read(regmap, RT5645_VENDOR_ID2, &val);
3907
3908 switch (val) {
3909 case RT5645_DEVICE_ID:
3910 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5645_regmap);
3911 rt5645->codec_type = CODEC_TYPE_RT5645;
3912 break;
3913 case RT5650_DEVICE_ID:
3914 rt5645->regmap = devm_regmap_init_i2c(i2c, &rt5650_regmap);
3915 rt5645->codec_type = CODEC_TYPE_RT5650;
3916 break;
3917 default:
3918 dev_err(&i2c->dev,
3919 "Device with ID register %#x is not rt5645 or rt5650\n",
3920 val);
3921 ret = -ENODEV;
3922 goto err_enable;
3923 }
3924
3925 if (IS_ERR(rt5645->regmap)) {
3926 ret = PTR_ERR(rt5645->regmap);
3927 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
3928 ret);
3929 return ret;
3930 }
3931
3932 regmap_write(rt5645->regmap, RT5645_RESET, 0);
3933
3934 regmap_read(regmap, RT5645_VENDOR_ID, &val);
3935 rt5645->v_id = val & 0xff;
3936
3937 regmap_write(rt5645->regmap, RT5645_AD_DA_MIXER, 0x8080);
3938
3939 ret = regmap_register_patch(rt5645->regmap, init_list,
3940 ARRAY_SIZE(init_list));
3941 if (ret != 0)
3942 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
3943
3944 if (rt5645->codec_type == CODEC_TYPE_RT5650) {
3945 ret = regmap_register_patch(rt5645->regmap, rt5650_init_list,
3946 ARRAY_SIZE(rt5650_init_list));
3947 if (ret != 0)
3948 dev_warn(&i2c->dev, "Apply rt5650 patch failed: %d\n",
3949 ret);
3950 }
3951
3952 regmap_update_bits(rt5645->regmap, RT5645_CLSD_OUT_CTRL, 0xc0, 0xc0);
3953
3954 if (rt5645->pdata.in2_diff)
3955 regmap_update_bits(rt5645->regmap, RT5645_IN2_CTRL,
3956 RT5645_IN_DF2, RT5645_IN_DF2);
3957
3958 if (rt5645->pdata.dmic1_data_pin || rt5645->pdata.dmic2_data_pin) {
3959 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3960 RT5645_GP2_PIN_MASK, RT5645_GP2_PIN_DMIC1_SCL);
3961 }
3962 switch (rt5645->pdata.dmic1_data_pin) {
3963 case RT5645_DMIC_DATA_IN2N:
3964 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3965 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_IN2N);
3966 break;
3967
3968 case RT5645_DMIC_DATA_GPIO5:
3969 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3970 RT5645_I2S2_DAC_PIN_MASK, RT5645_I2S2_DAC_PIN_GPIO);
3971 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3972 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO5);
3973 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3974 RT5645_GP5_PIN_MASK, RT5645_GP5_PIN_DMIC1_SDA);
3975 break;
3976
3977 case RT5645_DMIC_DATA_GPIO11:
3978 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3979 RT5645_DMIC_1_DP_MASK, RT5645_DMIC_1_DP_GPIO11);
3980 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3981 RT5645_GP11_PIN_MASK,
3982 RT5645_GP11_PIN_DMIC1_SDA);
3983 break;
3984
3985 default:
3986 break;
3987 }
3988
3989 switch (rt5645->pdata.dmic2_data_pin) {
3990 case RT5645_DMIC_DATA_IN2P:
3991 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3992 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_IN2P);
3993 break;
3994
3995 case RT5645_DMIC_DATA_GPIO6:
3996 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
3997 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO6);
3998 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
3999 RT5645_GP6_PIN_MASK, RT5645_GP6_PIN_DMIC2_SDA);
4000 break;
4001
4002 case RT5645_DMIC_DATA_GPIO10:
4003 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4004 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO10);
4005 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4006 RT5645_GP10_PIN_MASK,
4007 RT5645_GP10_PIN_DMIC2_SDA);
4008 break;
4009
4010 case RT5645_DMIC_DATA_GPIO12:
4011 regmap_update_bits(rt5645->regmap, RT5645_DMIC_CTRL1,
4012 RT5645_DMIC_2_DP_MASK, RT5645_DMIC_2_DP_GPIO12);
4013 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4014 RT5645_GP12_PIN_MASK,
4015 RT5645_GP12_PIN_DMIC2_SDA);
4016 break;
4017
4018 default:
4019 break;
4020 }
4021
4022 if (rt5645->pdata.jd_mode) {
4023 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4024 RT5645_IRQ_CLK_GATE_CTRL,
4025 RT5645_IRQ_CLK_GATE_CTRL);
4026 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
4027 RT5645_IRQ_CLK_INT, RT5645_IRQ_CLK_INT);
4028 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4029 RT5645_IRQ_JD_1_1_EN, RT5645_IRQ_JD_1_1_EN);
4030 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4031 RT5645_JD_PSV_MODE, RT5645_JD_PSV_MODE);
4032 regmap_update_bits(rt5645->regmap, RT5645_HPO_MIXER,
4033 RT5645_IRQ_PSV_MODE, RT5645_IRQ_PSV_MODE);
4034 regmap_update_bits(rt5645->regmap, RT5645_MICBIAS,
4035 RT5645_MIC2_OVCD_EN, RT5645_MIC2_OVCD_EN);
4036 regmap_update_bits(rt5645->regmap, RT5645_GPIO_CTRL1,
4037 RT5645_GP1_PIN_IRQ, RT5645_GP1_PIN_IRQ);
4038 switch (rt5645->pdata.jd_mode) {
4039 case 1:
4040 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4041 RT5645_JD1_MODE_MASK,
4042 RT5645_JD1_MODE_0);
4043 break;
4044 case 2:
4045 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4046 RT5645_JD1_MODE_MASK,
4047 RT5645_JD1_MODE_1);
4048 break;
4049 case 3:
4050 case 4:
4051 regmap_update_bits(rt5645->regmap, RT5645_A_JD_CTRL1,
4052 RT5645_JD1_MODE_MASK,
4053 RT5645_JD1_MODE_2);
4054 break;
4055 default:
4056 break;
4057 }
4058 if (rt5645->pdata.inv_jd1_1) {
4059 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4060 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
4061 }
4062 }
4063
4064 regmap_update_bits(rt5645->regmap, RT5645_ADDA_CLK1,
4065 RT5645_I2S_PD1_MASK, RT5645_I2S_PD1_2);
4066
4067 if (rt5645->pdata.level_trigger_irq) {
4068 regmap_update_bits(rt5645->regmap, RT5645_IRQ_CTRL2,
4069 RT5645_JD_1_1_MASK, RT5645_JD_1_1_INV);
4070 }
4071 timer_setup(&rt5645->btn_check_timer, rt5645_btn_check_callback, 0);
4072
4073 mutex_init(&rt5645->jd_mutex);
4074 INIT_DELAYED_WORK(&rt5645->jack_detect_work, rt5645_jack_detect_work);
4075 INIT_DELAYED_WORK(&rt5645->rcclock_work, rt5645_rcclock_work);
4076
4077 if (rt5645->i2c->irq) {
4078 ret = request_threaded_irq(rt5645->i2c->irq, NULL, rt5645_irq,
4079 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4080 | IRQF_ONESHOT, "rt5645", rt5645);
4081 if (ret) {
4082 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4083 goto err_enable;
4084 }
4085 }
4086
4087 ret = devm_snd_soc_register_component(&i2c->dev, &soc_component_dev_rt5645,
4088 rt5645_dai, ARRAY_SIZE(rt5645_dai));
4089 if (ret)
4090 goto err_irq;
4091
4092 return 0;
4093
4094 err_irq:
4095 if (rt5645->i2c->irq)
4096 free_irq(rt5645->i2c->irq, rt5645);
4097 err_enable:
4098 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
4099 return ret;
4100 }
4101
rt5645_i2c_remove(struct i2c_client * i2c)4102 static int rt5645_i2c_remove(struct i2c_client *i2c)
4103 {
4104 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
4105
4106 if (i2c->irq)
4107 free_irq(i2c->irq, rt5645);
4108
4109 /*
4110 * Since the rt5645_btn_check_callback() can queue jack_detect_work,
4111 * the timer need to be delted first
4112 */
4113 del_timer_sync(&rt5645->btn_check_timer);
4114
4115 cancel_delayed_work_sync(&rt5645->jack_detect_work);
4116 cancel_delayed_work_sync(&rt5645->rcclock_work);
4117
4118 regulator_bulk_disable(ARRAY_SIZE(rt5645->supplies), rt5645->supplies);
4119
4120 return 0;
4121 }
4122
rt5645_i2c_shutdown(struct i2c_client * i2c)4123 static void rt5645_i2c_shutdown(struct i2c_client *i2c)
4124 {
4125 struct rt5645_priv *rt5645 = i2c_get_clientdata(i2c);
4126
4127 regmap_update_bits(rt5645->regmap, RT5645_GEN_CTRL3,
4128 RT5645_RING2_SLEEVE_GND, RT5645_RING2_SLEEVE_GND);
4129 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL2, RT5645_CBJ_MN_JD,
4130 RT5645_CBJ_MN_JD);
4131 regmap_update_bits(rt5645->regmap, RT5645_IN1_CTRL1, RT5645_CBJ_BST1_EN,
4132 0);
4133 msleep(20);
4134 regmap_write(rt5645->regmap, RT5645_RESET, 0);
4135 }
4136
4137 static struct i2c_driver rt5645_i2c_driver = {
4138 .driver = {
4139 .name = "rt5645",
4140 .of_match_table = of_match_ptr(rt5645_of_match),
4141 .acpi_match_table = ACPI_PTR(rt5645_acpi_match),
4142 },
4143 .probe = rt5645_i2c_probe,
4144 .remove = rt5645_i2c_remove,
4145 .shutdown = rt5645_i2c_shutdown,
4146 .id_table = rt5645_i2c_id,
4147 };
4148 module_i2c_driver(rt5645_i2c_driver);
4149
4150 MODULE_DESCRIPTION("ASoC RT5645 driver");
4151 MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4152 MODULE_LICENSE("GPL v2");
4153