| /drivers/clk/meson/ |
| D | sclk-div.c | 31 static int sclk_div_maxval(struct meson_sclk_div_data *sclk) in sclk_div_maxval()
36 static int sclk_div_maxdiv(struct meson_sclk_div_data *sclk) in sclk_div_maxdiv()
51 struct meson_sclk_div_data *sclk) in sclk_div_bestdiv()
103 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); in sclk_div_round_rate() local
112 struct meson_sclk_div_data *sclk) in sclk_apply_ratio()
128 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); in sclk_div_set_duty_cycle() local
142 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); in sclk_div_get_duty_cycle() local
158 struct meson_sclk_div_data *sclk) in sclk_apply_divider()
170 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); in sclk_div_set_rate() local
185 struct meson_sclk_div_data *sclk = meson_sclk_div_data(clk); in sclk_div_recalc_rate() local
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| /drivers/clk/hisilicon/ |
| D | clkgate-separated.c | 34 struct clkgate_separated *sclk; in clkgate_separated_enable() local
51 struct clkgate_separated *sclk; in clkgate_separated_disable() local
67 struct clkgate_separated *sclk; in clkgate_separated_is_enabled() local
89 struct clkgate_separated *sclk; in hisi_register_clkgate_sep() local
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| /drivers/clk/ |
| D | clk-u300.c | 455 static void syscon_block_reset_enable(struct clk_syscon *sclk) in syscon_block_reset_enable()
471 static void syscon_block_reset_disable(struct clk_syscon *sclk) in syscon_block_reset_disable()
489 struct clk_syscon *sclk = to_syscon(hw); in syscon_clk_prepare() local
499 struct clk_syscon *sclk = to_syscon(hw); in syscon_clk_unprepare() local
511 struct clk_syscon *sclk = to_syscon(hw); in syscon_clk_enable() local
526 struct clk_syscon *sclk = to_syscon(hw); in syscon_clk_disable() local
542 struct clk_syscon *sclk = to_syscon(hw); in syscon_clk_is_enabled() local
568 struct clk_syscon *sclk = to_syscon(hw); in syscon_clk_recalc_rate() local
636 struct clk_syscon *sclk = to_syscon(hw); in syscon_clk_round_rate() local
653 struct clk_syscon *sclk = to_syscon(hw); in syscon_clk_set_rate() local
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| D | clk-nomadik.c | 302 struct clk_src *sclk = to_src(hw); in src_clk_enable() local
315 struct clk_src *sclk = to_src(hw); in src_clk_disable() local
327 struct clk_src *sclk = to_src(hw); in src_clk_is_enabled() local
353 struct clk_src *sclk; in src_clk_register() local
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| D | clk-scpi.c | 140 struct scpi_clk *sclk, const char *name) in scpi_clk_ops_init()
178 struct scpi_clk *sclk; in scpi_of_clk_src_get() local
214 struct scpi_clk *sclk; in scpi_clk_add() local
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| D | clk-scmi.c | 105 static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk) in scmi_clk_ops_init()
171 struct scmi_clk *sclk; in scmi_clocks_probe() local
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| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | gf100.c | 67 u32 sclk; in read_pll() local
102 u32 sclk, sctl, sdiv = 2; in read_div() local
138 u32 sclk, sdiv; in read_clk() local
223 u32 sclk; in calc_src() local
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| D | gk104.c | 68 u32 sclk; in read_pll() local
121 u32 sclk = read_vco(clk, dsrc + (doff * 4)); in read_div() local
149 u32 sclk, sdiv; in read_clk() local
236 u32 sclk; in calc_src() local
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| D | gt215.c | 64 u32 sctl, sdiv, sclk; in read_clk() local
112 u32 sclk = 0, P = 1, N = 1, M = 1; in read_pll() local
191 u32 oclk, sclk, sdiv; in gt215_clk_info() local
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| /drivers/clk/microchip/ |
| D | clk-core.c | 774 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_get_rate() local
792 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_set_rate() local
821 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_get_parent() local
837 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_set_parent() local
887 struct pic32_sys_clk *sclk = clkhw_to_sys_clk(hw); in sclk_init() local
930 struct pic32_sys_clk *sclk; in pic32_sys_clk_register() local
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| /drivers/gpu/drm/radeon/ |
| D | kv_dpm.c | 535 u32 index, u32 sclk) in kv_set_divider_value()
2081 u32 sclk, u32 min_sclk_in_sr) in kv_get_sleep_divider_id_from_clock()
2145 u32 sclk, mclk = 0; in kv_apply_state_adjust_rules() local
2617 u32 sclk; in kv_parse_pplib_clock_info() local
2709 u32 sclk; in kv_parse_power_table() local
2808 u32 sclk, tmp; in kv_dpm_debugfs_print_current_performance_level() local
2831 u32 sclk; in kv_dpm_get_current_sclk() local
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| D | rs690.c | 269 fixed20_12 sclk; member
281 fixed20_12 sclk, core_bandwidth, max_bandwidth; in rs690_crtc_bandwidth_compute() local
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| D | rs780_dpm.c | 753 u32 sclk; in rs780_parse_pplib_clock_info() local
992 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_debugfs_print_current_performance_level() local
1014 u32 sclk = (rdev->clock.spll.reference_freq * current_fb_div) / in rs780_dpm_get_current_sclk() local
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| D | rv515.c | 952 fixed20_12 sclk; member
964 fixed20_12 sclk; in rv515_crtc_bandwidth_compute() local
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| D | ci_dpm.c | 787 u32 sclk, mclk; in ci_apply_state_adjust_rules() local
2366 u32 sclk, in ci_populate_phase_value_based_on_sclk()
2438 u32 sclk, u32 min_sclk_in_sr) in ci_get_sleep_divider_id_from_clock()
2508 u32 sclk, in ci_populate_memory_timing_parameters()
3146 SMU7_Discrete_GraphicsLevel *sclk) in ci_calculate_sclk_params()
3846 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; in ci_find_dpm_states_clocks_in_dpm_table() local
3887 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk; in ci_populate_and_upload_sclk_mclk_dpm_levels() local
5609 u32 sclk, mclk; in ci_parse_power_table() local
5943 u32 sclk = ci_get_average_sclk_freq(rdev); in ci_dpm_debugfs_print_current_performance_level() local
5972 u32 sclk = ci_get_average_sclk_freq(rdev); in ci_dpm_get_current_sclk() local
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| D | trinity_dpm.c | 584 u32 index, u32 sclk) in trinity_set_divider_value()
1334 static u8 trinity_calculate_vce_wm(struct radeon_device *rdev, u32 sclk) in trinity_calculate_vce_wm()
1358 u32 sclk, u32 min_sclk_in_sr) in trinity_get_sleep_divider_id_from_clock()
1714 u32 sclk; in trinity_parse_pplib_clock_info() local
1808 u32 sclk; in trinity_parse_power_table() local
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| D | radeon_clocks.c | 43 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
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| /drivers/gpu/drm/amd/pm/powerplay/ |
| D | kv_dpm.c | 662 u32 index, u32 sclk) in kv_set_divider_value()
2136 u32 sclk, u32 min_sclk_in_sr) in kv_get_sleep_divider_id_from_clock()
2199 u32 sclk, mclk = 0; in kv_apply_state_adjust_rules() local
2674 u32 sclk; in kv_parse_pplib_clock_info() local
2764 u32 sclk; in kv_parse_power_table() local
2859 u32 sclk, tmp; in kv_dpm_debugfs_print_current_performance_level() local
3271 uint32_t sclk; in kv_dpm_read_sensor() local
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| /drivers/tty/serial/8250/ |
| D | 8250_em.c | 24 struct clk *sclk; member
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| /drivers/gpu/drm/armada/ |
| D | armada_510.c | 101 const struct drm_display_mode *mode, uint32_t *sclk) in armada510_crtc_compute_clock()
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| /drivers/clocksource/ |
| D | timer-atmel-st.c | 185 struct clk *sclk; in atmel_st_timer_init() local
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| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | smu_helper.c | 462 uint16_t virtual_voltage_id, int32_t *sclk) in phm_get_sclk_for_voltage_evv()
572 uint32_t sclk, uint16_t id, uint16_t *voltage) in phm_get_voltage_evv_on_sclk()
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| D | ppatomctrl.c | 643 uint32_t sclk, in atomctrl_calculate_voltage_evv_on_sclk()
1087 uint32_t sclk, uint16_t virtual_voltage_Id, in atomctrl_get_voltage_evv_on_sclk()
1339 uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage) in atomctrl_get_voltage_evv_on_sclk_ai()
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| /drivers/power/reset/ |
| D | at91-poweroff.c | 55 struct clk *sclk; member
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| D | at91-reset.c | 56 struct clk *sclk; member
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