1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Local APIC handling, local APIC timers
4 *
5 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 *
7 * Fixes
8 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
9 * thanks to Eric Gilmore
10 * and Rolf G. Tews
11 * for testing these extensively.
12 * Maciej W. Rozycki : Various updates and fixes.
13 * Mikael Pettersson : Power Management for UP-APIC.
14 * Pavel Machek and
15 * Mikael Pettersson : PM converted to driver model.
16 */
17
18 #include <linux/perf_event.h>
19 #include <linux/kernel_stat.h>
20 #include <linux/mc146818rtc.h>
21 #include <linux/acpi_pmtmr.h>
22 #include <linux/clockchips.h>
23 #include <linux/interrupt.h>
24 #include <linux/memblock.h>
25 #include <linux/ftrace.h>
26 #include <linux/ioport.h>
27 #include <linux/export.h>
28 #include <linux/syscore_ops.h>
29 #include <linux/delay.h>
30 #include <linux/timex.h>
31 #include <linux/i8253.h>
32 #include <linux/dmar.h>
33 #include <linux/init.h>
34 #include <linux/cpu.h>
35 #include <linux/dmi.h>
36 #include <linux/smp.h>
37 #include <linux/mm.h>
38
39 #include <asm/trace/irq_vectors.h>
40 #include <asm/irq_remapping.h>
41 #include <asm/perf_event.h>
42 #include <asm/x86_init.h>
43 #include <linux/atomic.h>
44 #include <asm/barrier.h>
45 #include <asm/mpspec.h>
46 #include <asm/i8259.h>
47 #include <asm/proto.h>
48 #include <asm/traps.h>
49 #include <asm/apic.h>
50 #include <asm/acpi.h>
51 #include <asm/io_apic.h>
52 #include <asm/desc.h>
53 #include <asm/hpet.h>
54 #include <asm/mtrr.h>
55 #include <asm/time.h>
56 #include <asm/smp.h>
57 #include <asm/mce.h>
58 #include <asm/tsc.h>
59 #include <asm/hypervisor.h>
60 #include <asm/cpu_device_id.h>
61 #include <asm/intel-family.h>
62 #include <asm/irq_regs.h>
63
64 unsigned int num_processors;
65
66 unsigned disabled_cpus;
67
68 /* Processor that is doing the boot up */
69 unsigned int boot_cpu_physical_apicid __ro_after_init = -1U;
70 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
71
72 u8 boot_cpu_apic_version __ro_after_init;
73
74 /*
75 * The highest APIC ID seen during enumeration.
76 */
77 static unsigned int max_physical_apicid;
78
79 /*
80 * Bitmask of physically existing CPUs:
81 */
82 physid_mask_t phys_cpu_present_map;
83
84 /*
85 * Processor to be disabled specified by kernel parameter
86 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
87 * avoid undefined behaviour caused by sending INIT from AP to BSP.
88 */
89 static unsigned int disabled_cpu_apicid __ro_after_init = BAD_APICID;
90
91 /*
92 * This variable controls which CPUs receive external NMIs. By default,
93 * external NMIs are delivered only to the BSP.
94 */
95 static int apic_extnmi __ro_after_init = APIC_EXTNMI_BSP;
96
97 /*
98 * Map cpu index to physical APIC ID
99 */
100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
101 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
102 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
104 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
105 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
106
107 #ifdef CONFIG_X86_32
108
109 /*
110 * On x86_32, the mapping between cpu and logical apicid may vary
111 * depending on apic in use. The following early percpu variable is
112 * used for the mapping. This is where the behaviors of x86_64 and 32
113 * actually diverge. Let's keep it ugly for now.
114 */
115 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
116
117 /* Local APIC was disabled by the BIOS and enabled by the kernel */
118 static int enabled_via_apicbase __ro_after_init;
119
120 /*
121 * Handle interrupt mode configuration register (IMCR).
122 * This register controls whether the interrupt signals
123 * that reach the BSP come from the master PIC or from the
124 * local APIC. Before entering Symmetric I/O Mode, either
125 * the BIOS or the operating system must switch out of
126 * PIC Mode by changing the IMCR.
127 */
imcr_pic_to_apic(void)128 static inline void imcr_pic_to_apic(void)
129 {
130 /* select IMCR register */
131 outb(0x70, 0x22);
132 /* NMI and 8259 INTR go through APIC */
133 outb(0x01, 0x23);
134 }
135
imcr_apic_to_pic(void)136 static inline void imcr_apic_to_pic(void)
137 {
138 /* select IMCR register */
139 outb(0x70, 0x22);
140 /* NMI and 8259 INTR go directly to BSP */
141 outb(0x00, 0x23);
142 }
143 #endif
144
145 /*
146 * Knob to control our willingness to enable the local APIC.
147 *
148 * +1=force-enable
149 */
150 static int force_enable_local_apic __initdata;
151
152 /*
153 * APIC command line parameters
154 */
parse_lapic(char * arg)155 static int __init parse_lapic(char *arg)
156 {
157 if (IS_ENABLED(CONFIG_X86_32) && !arg)
158 force_enable_local_apic = 1;
159 else if (arg && !strncmp(arg, "notscdeadline", 13))
160 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
161 return 0;
162 }
163 early_param("lapic", parse_lapic);
164
165 #ifdef CONFIG_X86_64
166 static int apic_calibrate_pmtmr __initdata;
setup_apicpmtimer(char * s)167 static __init int setup_apicpmtimer(char *s)
168 {
169 apic_calibrate_pmtmr = 1;
170 notsc_setup(NULL);
171 return 1;
172 }
173 __setup("apicpmtimer", setup_apicpmtimer);
174 #endif
175
176 unsigned long mp_lapic_addr __ro_after_init;
177 int disable_apic __ro_after_init;
178 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
179 static int disable_apic_timer __initdata;
180 /* Local APIC timer works in C2 */
181 int local_apic_timer_c2_ok __ro_after_init;
182 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
183
184 /*
185 * Debug level, exported for io_apic.c
186 */
187 int apic_verbosity __ro_after_init;
188
189 int pic_mode __ro_after_init;
190
191 /* Have we found an MP table */
192 int smp_found_config __ro_after_init;
193
194 static struct resource lapic_resource = {
195 .name = "Local APIC",
196 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
197 };
198
199 unsigned int lapic_timer_period = 0;
200
201 static void apic_pm_activate(void);
202
203 static unsigned long apic_phys __ro_after_init;
204
205 /*
206 * Get the LAPIC version
207 */
lapic_get_version(void)208 static inline int lapic_get_version(void)
209 {
210 return GET_APIC_VERSION(apic_read(APIC_LVR));
211 }
212
213 /*
214 * Check, if the APIC is integrated or a separate chip
215 */
lapic_is_integrated(void)216 static inline int lapic_is_integrated(void)
217 {
218 return APIC_INTEGRATED(lapic_get_version());
219 }
220
221 /*
222 * Check, whether this is a modern or a first generation APIC
223 */
modern_apic(void)224 static int modern_apic(void)
225 {
226 /* AMD systems use old APIC versions, so check the CPU */
227 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
228 boot_cpu_data.x86 >= 0xf)
229 return 1;
230
231 /* Hygon systems use modern APIC */
232 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
233 return 1;
234
235 return lapic_get_version() >= 0x14;
236 }
237
238 /*
239 * right after this call apic become NOOP driven
240 * so apic->write/read doesn't do anything
241 */
apic_disable(void)242 static void __init apic_disable(void)
243 {
244 pr_info("APIC: switched to apic NOOP\n");
245 apic = &apic_noop;
246 }
247
native_apic_wait_icr_idle(void)248 void native_apic_wait_icr_idle(void)
249 {
250 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
251 cpu_relax();
252 }
253
native_safe_apic_wait_icr_idle(void)254 u32 native_safe_apic_wait_icr_idle(void)
255 {
256 u32 send_status;
257 int timeout;
258
259 timeout = 0;
260 do {
261 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
262 if (!send_status)
263 break;
264 inc_irq_stat(icr_read_retry_count);
265 udelay(100);
266 } while (timeout++ < 1000);
267
268 return send_status;
269 }
270
native_apic_icr_write(u32 low,u32 id)271 void native_apic_icr_write(u32 low, u32 id)
272 {
273 unsigned long flags;
274
275 local_irq_save(flags);
276 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
277 apic_write(APIC_ICR, low);
278 local_irq_restore(flags);
279 }
280
native_apic_icr_read(void)281 u64 native_apic_icr_read(void)
282 {
283 u32 icr1, icr2;
284
285 icr2 = apic_read(APIC_ICR2);
286 icr1 = apic_read(APIC_ICR);
287
288 return icr1 | ((u64)icr2 << 32);
289 }
290
291 #ifdef CONFIG_X86_32
292 /**
293 * get_physical_broadcast - Get number of physical broadcast IDs
294 */
get_physical_broadcast(void)295 int get_physical_broadcast(void)
296 {
297 return modern_apic() ? 0xff : 0xf;
298 }
299 #endif
300
301 /**
302 * lapic_get_maxlvt - get the maximum number of local vector table entries
303 */
lapic_get_maxlvt(void)304 int lapic_get_maxlvt(void)
305 {
306 /*
307 * - we always have APIC integrated on 64bit mode
308 * - 82489DXs do not report # of LVT entries
309 */
310 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2;
311 }
312
313 /*
314 * Local APIC timer
315 */
316
317 /* Clock divisor */
318 #define APIC_DIVISOR 16
319 #define TSC_DIVISOR 8
320
321 /*
322 * This function sets up the local APIC timer, with a timeout of
323 * 'clocks' APIC bus clock. During calibration we actually call
324 * this function twice on the boot CPU, once with a bogus timeout
325 * value, second time for real. The other (noncalibrating) CPUs
326 * call this function only once, with the real, calibrated value.
327 *
328 * We do reads before writes even if unnecessary, to get around the
329 * P5 APIC double write bug.
330 */
__setup_APIC_LVTT(unsigned int clocks,int oneshot,int irqen)331 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
332 {
333 unsigned int lvtt_value, tmp_value;
334
335 lvtt_value = LOCAL_TIMER_VECTOR;
336 if (!oneshot)
337 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
338 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
339 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
340
341 if (!lapic_is_integrated())
342 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
343
344 if (!irqen)
345 lvtt_value |= APIC_LVT_MASKED;
346
347 apic_write(APIC_LVTT, lvtt_value);
348
349 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
350 /*
351 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
352 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
353 * According to Intel, MFENCE can do the serialization here.
354 */
355 asm volatile("mfence" : : : "memory");
356 return;
357 }
358
359 /*
360 * Divide PICLK by 16
361 */
362 tmp_value = apic_read(APIC_TDCR);
363 apic_write(APIC_TDCR,
364 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
365 APIC_TDR_DIV_16);
366
367 if (!oneshot)
368 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
369 }
370
371 /*
372 * Setup extended LVT, AMD specific
373 *
374 * Software should use the LVT offsets the BIOS provides. The offsets
375 * are determined by the subsystems using it like those for MCE
376 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts
377 * are supported. Beginning with family 10h at least 4 offsets are
378 * available.
379 *
380 * Since the offsets must be consistent for all cores, we keep track
381 * of the LVT offsets in software and reserve the offset for the same
382 * vector also to be used on other cores. An offset is freed by
383 * setting the entry to APIC_EILVT_MASKED.
384 *
385 * If the BIOS is right, there should be no conflicts. Otherwise a
386 * "[Firmware Bug]: ..." error message is generated. However, if
387 * software does not properly determines the offsets, it is not
388 * necessarily a BIOS bug.
389 */
390
391 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
392
eilvt_entry_is_changeable(unsigned int old,unsigned int new)393 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
394 {
395 return (old & APIC_EILVT_MASKED)
396 || (new == APIC_EILVT_MASKED)
397 || ((new & ~APIC_EILVT_MASKED) == old);
398 }
399
reserve_eilvt_offset(int offset,unsigned int new)400 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
401 {
402 unsigned int rsvd, vector;
403
404 if (offset >= APIC_EILVT_NR_MAX)
405 return ~0;
406
407 rsvd = atomic_read(&eilvt_offsets[offset]);
408 do {
409 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */
410 if (vector && !eilvt_entry_is_changeable(vector, new))
411 /* may not change if vectors are different */
412 return rsvd;
413 } while (!atomic_try_cmpxchg(&eilvt_offsets[offset], &rsvd, new));
414
415 rsvd = new & ~APIC_EILVT_MASKED;
416 if (rsvd && rsvd != vector)
417 pr_info("LVT offset %d assigned for vector 0x%02x\n",
418 offset, rsvd);
419
420 return new;
421 }
422
423 /*
424 * If mask=1, the LVT entry does not generate interrupts while mask=0
425 * enables the vector. See also the BKDGs. Must be called with
426 * preemption disabled.
427 */
428
setup_APIC_eilvt(u8 offset,u8 vector,u8 msg_type,u8 mask)429 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
430 {
431 unsigned long reg = APIC_EILVTn(offset);
432 unsigned int new, old, reserved;
433
434 new = (mask << 16) | (msg_type << 8) | vector;
435 old = apic_read(reg);
436 reserved = reserve_eilvt_offset(offset, new);
437
438 if (reserved != new) {
439 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
440 "vector 0x%x, but the register is already in use for "
441 "vector 0x%x on another cpu\n",
442 smp_processor_id(), reg, offset, new, reserved);
443 return -EINVAL;
444 }
445
446 if (!eilvt_entry_is_changeable(old, new)) {
447 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
448 "vector 0x%x, but the register is already in use for "
449 "vector 0x%x on this cpu\n",
450 smp_processor_id(), reg, offset, new, old);
451 return -EBUSY;
452 }
453
454 apic_write(reg, new);
455
456 return 0;
457 }
458 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
459
460 /*
461 * Program the next event, relative to now
462 */
lapic_next_event(unsigned long delta,struct clock_event_device * evt)463 static int lapic_next_event(unsigned long delta,
464 struct clock_event_device *evt)
465 {
466 apic_write(APIC_TMICT, delta);
467 return 0;
468 }
469
lapic_next_deadline(unsigned long delta,struct clock_event_device * evt)470 static int lapic_next_deadline(unsigned long delta,
471 struct clock_event_device *evt)
472 {
473 u64 tsc;
474
475 /* This MSR is special and need a special fence: */
476 weak_wrmsr_fence();
477
478 tsc = rdtsc();
479 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
480 return 0;
481 }
482
lapic_timer_shutdown(struct clock_event_device * evt)483 static int lapic_timer_shutdown(struct clock_event_device *evt)
484 {
485 unsigned int v;
486
487 /* Lapic used as dummy for broadcast ? */
488 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
489 return 0;
490
491 v = apic_read(APIC_LVTT);
492 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
493 apic_write(APIC_LVTT, v);
494 apic_write(APIC_TMICT, 0);
495 return 0;
496 }
497
498 static inline int
lapic_timer_set_periodic_oneshot(struct clock_event_device * evt,bool oneshot)499 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
500 {
501 /* Lapic used as dummy for broadcast ? */
502 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
503 return 0;
504
505 __setup_APIC_LVTT(lapic_timer_period, oneshot, 1);
506 return 0;
507 }
508
lapic_timer_set_periodic(struct clock_event_device * evt)509 static int lapic_timer_set_periodic(struct clock_event_device *evt)
510 {
511 return lapic_timer_set_periodic_oneshot(evt, false);
512 }
513
lapic_timer_set_oneshot(struct clock_event_device * evt)514 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
515 {
516 return lapic_timer_set_periodic_oneshot(evt, true);
517 }
518
519 /*
520 * Local APIC timer broadcast function
521 */
lapic_timer_broadcast(const struct cpumask * mask)522 static void lapic_timer_broadcast(const struct cpumask *mask)
523 {
524 #ifdef CONFIG_SMP
525 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
526 #endif
527 }
528
529
530 /*
531 * The local apic timer can be used for any function which is CPU local.
532 */
533 static struct clock_event_device lapic_clockevent = {
534 .name = "lapic",
535 .features = CLOCK_EVT_FEAT_PERIODIC |
536 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
537 | CLOCK_EVT_FEAT_DUMMY,
538 .shift = 32,
539 .set_state_shutdown = lapic_timer_shutdown,
540 .set_state_periodic = lapic_timer_set_periodic,
541 .set_state_oneshot = lapic_timer_set_oneshot,
542 .set_state_oneshot_stopped = lapic_timer_shutdown,
543 .set_next_event = lapic_next_event,
544 .broadcast = lapic_timer_broadcast,
545 .rating = 100,
546 .irq = -1,
547 };
548 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
549
550 static const struct x86_cpu_id deadline_match[] __initconst = {
551 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x2, 0x2), 0x3a), /* EP */
552 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(HASWELL_X, X86_STEPPINGS(0x4, 0x4), 0x0f), /* EX */
553
554 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_X, 0x0b000020),
555
556 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x2, 0x2), 0x00000011),
557 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x3, 0x3), 0x0700000e),
558 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x4, 0x4), 0x0f00000c),
559 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(BROADWELL_D, X86_STEPPINGS(0x5, 0x5), 0x0e000003),
560
561 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x3, 0x3), 0x01000136),
562 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x4, 0x4), 0x02000014),
563 X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x5, 0xf), 0),
564
565 X86_MATCH_INTEL_FAM6_MODEL( HASWELL, 0x22),
566 X86_MATCH_INTEL_FAM6_MODEL( HASWELL_L, 0x20),
567 X86_MATCH_INTEL_FAM6_MODEL( HASWELL_G, 0x17),
568
569 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL, 0x25),
570 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_G, 0x17),
571
572 X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE_L, 0xb2),
573 X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE, 0xb2),
574
575 X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE_L, 0x52),
576 X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE, 0x52),
577
578 {},
579 };
580
apic_validate_deadline_timer(void)581 static __init bool apic_validate_deadline_timer(void)
582 {
583 const struct x86_cpu_id *m;
584 u32 rev;
585
586 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
587 return false;
588 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
589 return true;
590
591 m = x86_match_cpu(deadline_match);
592 if (!m)
593 return true;
594
595 rev = (u32)m->driver_data;
596
597 if (boot_cpu_data.microcode >= rev)
598 return true;
599
600 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
601 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
602 "please update microcode to version: 0x%x (or later)\n", rev);
603 return false;
604 }
605
606 /*
607 * Setup the local APIC timer for this CPU. Copy the initialized values
608 * of the boot CPU and register the clock event in the framework.
609 */
setup_APIC_timer(void)610 static void setup_APIC_timer(void)
611 {
612 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
613
614 if (this_cpu_has(X86_FEATURE_ARAT)) {
615 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
616 /* Make LAPIC timer preferrable over percpu HPET */
617 lapic_clockevent.rating = 150;
618 }
619
620 memcpy(levt, &lapic_clockevent, sizeof(*levt));
621 levt->cpumask = cpumask_of(smp_processor_id());
622
623 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
624 levt->name = "lapic-deadline";
625 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
626 CLOCK_EVT_FEAT_DUMMY);
627 levt->set_next_event = lapic_next_deadline;
628 clockevents_config_and_register(levt,
629 tsc_khz * (1000 / TSC_DIVISOR),
630 0xF, ~0UL);
631 } else
632 clockevents_register_device(levt);
633 }
634
635 /*
636 * Install the updated TSC frequency from recalibration at the TSC
637 * deadline clockevent devices.
638 */
__lapic_update_tsc_freq(void * info)639 static void __lapic_update_tsc_freq(void *info)
640 {
641 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
642
643 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
644 return;
645
646 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
647 }
648
lapic_update_tsc_freq(void)649 void lapic_update_tsc_freq(void)
650 {
651 /*
652 * The clockevent device's ->mult and ->shift can both be
653 * changed. In order to avoid races, schedule the frequency
654 * update code on each CPU.
655 */
656 on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
657 }
658
659 /*
660 * In this functions we calibrate APIC bus clocks to the external timer.
661 *
662 * We want to do the calibration only once since we want to have local timer
663 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
664 * frequency.
665 *
666 * This was previously done by reading the PIT/HPET and waiting for a wrap
667 * around to find out, that a tick has elapsed. I have a box, where the PIT
668 * readout is broken, so it never gets out of the wait loop again. This was
669 * also reported by others.
670 *
671 * Monitoring the jiffies value is inaccurate and the clockevents
672 * infrastructure allows us to do a simple substitution of the interrupt
673 * handler.
674 *
675 * The calibration routine also uses the pm_timer when possible, as the PIT
676 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
677 * back to normal later in the boot process).
678 */
679
680 #define LAPIC_CAL_LOOPS (HZ/10)
681
682 static __initdata int lapic_cal_loops = -1;
683 static __initdata long lapic_cal_t1, lapic_cal_t2;
684 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
685 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
686 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
687
688 /*
689 * Temporary interrupt handler and polled calibration function.
690 */
lapic_cal_handler(struct clock_event_device * dev)691 static void __init lapic_cal_handler(struct clock_event_device *dev)
692 {
693 unsigned long long tsc = 0;
694 long tapic = apic_read(APIC_TMCCT);
695 unsigned long pm = acpi_pm_read_early();
696
697 if (boot_cpu_has(X86_FEATURE_TSC))
698 tsc = rdtsc();
699
700 switch (lapic_cal_loops++) {
701 case 0:
702 lapic_cal_t1 = tapic;
703 lapic_cal_tsc1 = tsc;
704 lapic_cal_pm1 = pm;
705 lapic_cal_j1 = jiffies;
706 break;
707
708 case LAPIC_CAL_LOOPS:
709 lapic_cal_t2 = tapic;
710 lapic_cal_tsc2 = tsc;
711 if (pm < lapic_cal_pm1)
712 pm += ACPI_PM_OVRRUN;
713 lapic_cal_pm2 = pm;
714 lapic_cal_j2 = jiffies;
715 break;
716 }
717 }
718
719 static int __init
calibrate_by_pmtimer(long deltapm,long * delta,long * deltatsc)720 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
721 {
722 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
723 const long pm_thresh = pm_100ms / 100;
724 unsigned long mult;
725 u64 res;
726
727 #ifndef CONFIG_X86_PM_TIMER
728 return -1;
729 #endif
730
731 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
732
733 /* Check, if the PM timer is available */
734 if (!deltapm)
735 return -1;
736
737 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
738
739 if (deltapm > (pm_100ms - pm_thresh) &&
740 deltapm < (pm_100ms + pm_thresh)) {
741 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
742 return 0;
743 }
744
745 res = (((u64)deltapm) * mult) >> 22;
746 do_div(res, 1000000);
747 pr_warn("APIC calibration not consistent "
748 "with PM-Timer: %ldms instead of 100ms\n", (long)res);
749
750 /* Correct the lapic counter value */
751 res = (((u64)(*delta)) * pm_100ms);
752 do_div(res, deltapm);
753 pr_info("APIC delta adjusted to PM-Timer: "
754 "%lu (%ld)\n", (unsigned long)res, *delta);
755 *delta = (long)res;
756
757 /* Correct the tsc counter value */
758 if (boot_cpu_has(X86_FEATURE_TSC)) {
759 res = (((u64)(*deltatsc)) * pm_100ms);
760 do_div(res, deltapm);
761 apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
762 "PM-Timer: %lu (%ld)\n",
763 (unsigned long)res, *deltatsc);
764 *deltatsc = (long)res;
765 }
766
767 return 0;
768 }
769
lapic_init_clockevent(void)770 static int __init lapic_init_clockevent(void)
771 {
772 if (!lapic_timer_period)
773 return -1;
774
775 /* Calculate the scaled math multiplication factor */
776 lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR,
777 TICK_NSEC, lapic_clockevent.shift);
778 lapic_clockevent.max_delta_ns =
779 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
780 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF;
781 lapic_clockevent.min_delta_ns =
782 clockevent_delta2ns(0xF, &lapic_clockevent);
783 lapic_clockevent.min_delta_ticks = 0xF;
784
785 return 0;
786 }
787
apic_needs_pit(void)788 bool __init apic_needs_pit(void)
789 {
790 /*
791 * If the frequencies are not known, PIT is required for both TSC
792 * and apic timer calibration.
793 */
794 if (!tsc_khz || !cpu_khz)
795 return true;
796
797 /* Is there an APIC at all or is it disabled? */
798 if (!boot_cpu_has(X86_FEATURE_APIC) || disable_apic)
799 return true;
800
801 /*
802 * If interrupt delivery mode is legacy PIC or virtual wire without
803 * configuration, the local APIC timer wont be set up. Make sure
804 * that the PIT is initialized.
805 */
806 if (apic_intr_mode == APIC_PIC ||
807 apic_intr_mode == APIC_VIRTUAL_WIRE_NO_CONFIG)
808 return true;
809
810 /* Virt guests may lack ARAT, but still have DEADLINE */
811 if (!boot_cpu_has(X86_FEATURE_ARAT))
812 return true;
813
814 /* Deadline timer is based on TSC so no further PIT action required */
815 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
816 return false;
817
818 /* APIC timer disabled? */
819 if (disable_apic_timer)
820 return true;
821 /*
822 * The APIC timer frequency is known already, no PIT calibration
823 * required. If unknown, let the PIT be initialized.
824 */
825 return lapic_timer_period == 0;
826 }
827
calibrate_APIC_clock(void)828 static int __init calibrate_APIC_clock(void)
829 {
830 struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
831 u64 tsc_perj = 0, tsc_start = 0;
832 unsigned long jif_start;
833 unsigned long deltaj;
834 long delta, deltatsc;
835 int pm_referenced = 0;
836
837 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
838 return 0;
839
840 /*
841 * Check if lapic timer has already been calibrated by platform
842 * specific routine, such as tsc calibration code. If so just fill
843 * in the clockevent structure and return.
844 */
845 if (!lapic_init_clockevent()) {
846 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
847 lapic_timer_period);
848 /*
849 * Direct calibration methods must have an always running
850 * local APIC timer, no need for broadcast timer.
851 */
852 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
853 return 0;
854 }
855
856 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
857 "calibrating APIC timer ...\n");
858
859 /*
860 * There are platforms w/o global clockevent devices. Instead of
861 * making the calibration conditional on that, use a polling based
862 * approach everywhere.
863 */
864 local_irq_disable();
865
866 /*
867 * Setup the APIC counter to maximum. There is no way the lapic
868 * can underflow in the 100ms detection time frame
869 */
870 __setup_APIC_LVTT(0xffffffff, 0, 0);
871
872 /*
873 * Methods to terminate the calibration loop:
874 * 1) Global clockevent if available (jiffies)
875 * 2) TSC if available and frequency is known
876 */
877 jif_start = READ_ONCE(jiffies);
878
879 if (tsc_khz) {
880 tsc_start = rdtsc();
881 tsc_perj = div_u64((u64)tsc_khz * 1000, HZ);
882 }
883
884 /*
885 * Enable interrupts so the tick can fire, if a global
886 * clockevent device is available
887 */
888 local_irq_enable();
889
890 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) {
891 /* Wait for a tick to elapse */
892 while (1) {
893 if (tsc_khz) {
894 u64 tsc_now = rdtsc();
895 if ((tsc_now - tsc_start) >= tsc_perj) {
896 tsc_start += tsc_perj;
897 break;
898 }
899 } else {
900 unsigned long jif_now = READ_ONCE(jiffies);
901
902 if (time_after(jif_now, jif_start)) {
903 jif_start = jif_now;
904 break;
905 }
906 }
907 cpu_relax();
908 }
909
910 /* Invoke the calibration routine */
911 local_irq_disable();
912 lapic_cal_handler(NULL);
913 local_irq_enable();
914 }
915
916 local_irq_disable();
917
918 /* Build delta t1-t2 as apic timer counts down */
919 delta = lapic_cal_t1 - lapic_cal_t2;
920 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
921
922 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
923
924 /* we trust the PM based calibration if possible */
925 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
926 &delta, &deltatsc);
927
928 lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
929 lapic_init_clockevent();
930
931 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
932 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
933 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
934 lapic_timer_period);
935
936 if (boot_cpu_has(X86_FEATURE_TSC)) {
937 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
938 "%ld.%04ld MHz.\n",
939 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
940 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
941 }
942
943 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
944 "%u.%04u MHz.\n",
945 lapic_timer_period / (1000000 / HZ),
946 lapic_timer_period % (1000000 / HZ));
947
948 /*
949 * Do a sanity check on the APIC calibration result
950 */
951 if (lapic_timer_period < (1000000 / HZ)) {
952 local_irq_enable();
953 pr_warn("APIC frequency too slow, disabling apic timer\n");
954 return -1;
955 }
956
957 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
958
959 /*
960 * PM timer calibration failed or not turned on so lets try APIC
961 * timer based calibration, if a global clockevent device is
962 * available.
963 */
964 if (!pm_referenced && global_clock_event) {
965 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
966
967 /*
968 * Setup the apic timer manually
969 */
970 levt->event_handler = lapic_cal_handler;
971 lapic_timer_set_periodic(levt);
972 lapic_cal_loops = -1;
973
974 /* Let the interrupts run */
975 local_irq_enable();
976
977 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
978 cpu_relax();
979
980 /* Stop the lapic timer */
981 local_irq_disable();
982 lapic_timer_shutdown(levt);
983
984 /* Jiffies delta */
985 deltaj = lapic_cal_j2 - lapic_cal_j1;
986 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
987
988 /* Check, if the jiffies result is consistent */
989 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
990 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
991 else
992 levt->features |= CLOCK_EVT_FEAT_DUMMY;
993 }
994 local_irq_enable();
995
996 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
997 pr_warn("APIC timer disabled due to verification failure\n");
998 return -1;
999 }
1000
1001 return 0;
1002 }
1003
1004 /*
1005 * Setup the boot APIC
1006 *
1007 * Calibrate and verify the result.
1008 */
setup_boot_APIC_clock(void)1009 void __init setup_boot_APIC_clock(void)
1010 {
1011 /*
1012 * The local apic timer can be disabled via the kernel
1013 * commandline or from the CPU detection code. Register the lapic
1014 * timer as a dummy clock event source on SMP systems, so the
1015 * broadcast mechanism is used. On UP systems simply ignore it.
1016 */
1017 if (disable_apic_timer) {
1018 pr_info("Disabling APIC timer\n");
1019 /* No broadcast on UP ! */
1020 if (num_possible_cpus() > 1) {
1021 lapic_clockevent.mult = 1;
1022 setup_APIC_timer();
1023 }
1024 return;
1025 }
1026
1027 if (calibrate_APIC_clock()) {
1028 /* No broadcast on UP ! */
1029 if (num_possible_cpus() > 1)
1030 setup_APIC_timer();
1031 return;
1032 }
1033
1034 /*
1035 * If nmi_watchdog is set to IO_APIC, we need the
1036 * PIT/HPET going. Otherwise register lapic as a dummy
1037 * device.
1038 */
1039 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
1040
1041 /* Setup the lapic or request the broadcast */
1042 setup_APIC_timer();
1043 amd_e400_c1e_apic_setup();
1044 }
1045
setup_secondary_APIC_clock(void)1046 void setup_secondary_APIC_clock(void)
1047 {
1048 setup_APIC_timer();
1049 amd_e400_c1e_apic_setup();
1050 }
1051
1052 /*
1053 * The guts of the apic timer interrupt
1054 */
local_apic_timer_interrupt(void)1055 static void local_apic_timer_interrupt(void)
1056 {
1057 struct clock_event_device *evt = this_cpu_ptr(&lapic_events);
1058
1059 /*
1060 * Normally we should not be here till LAPIC has been initialized but
1061 * in some cases like kdump, its possible that there is a pending LAPIC
1062 * timer interrupt from previous kernel's context and is delivered in
1063 * new kernel the moment interrupts are enabled.
1064 *
1065 * Interrupts are enabled early and LAPIC is setup much later, hence
1066 * its possible that when we get here evt->event_handler is NULL.
1067 * Check for event_handler being NULL and discard the interrupt as
1068 * spurious.
1069 */
1070 if (!evt->event_handler) {
1071 pr_warn("Spurious LAPIC timer interrupt on cpu %d\n",
1072 smp_processor_id());
1073 /* Switch it off */
1074 lapic_timer_shutdown(evt);
1075 return;
1076 }
1077
1078 /*
1079 * the NMI deadlock-detector uses this.
1080 */
1081 inc_irq_stat(apic_timer_irqs);
1082
1083 evt->event_handler(evt);
1084 }
1085
1086 /*
1087 * Local APIC timer interrupt. This is the most natural way for doing
1088 * local interrupts, but local timer interrupts can be emulated by
1089 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1090 *
1091 * [ if a single-CPU system runs an SMP kernel then we call the local
1092 * interrupt as well. Thus we cannot inline the local irq ... ]
1093 */
DEFINE_IDTENTRY_SYSVEC(sysvec_apic_timer_interrupt)1094 DEFINE_IDTENTRY_SYSVEC(sysvec_apic_timer_interrupt)
1095 {
1096 struct pt_regs *old_regs = set_irq_regs(regs);
1097
1098 ack_APIC_irq();
1099 trace_local_timer_entry(LOCAL_TIMER_VECTOR);
1100 local_apic_timer_interrupt();
1101 trace_local_timer_exit(LOCAL_TIMER_VECTOR);
1102
1103 set_irq_regs(old_regs);
1104 }
1105
setup_profiling_timer(unsigned int multiplier)1106 int setup_profiling_timer(unsigned int multiplier)
1107 {
1108 return -EINVAL;
1109 }
1110
1111 /*
1112 * Local APIC start and shutdown
1113 */
1114
1115 /**
1116 * clear_local_APIC - shutdown the local APIC
1117 *
1118 * This is called, when a CPU is disabled and before rebooting, so the state of
1119 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1120 * leftovers during boot.
1121 */
clear_local_APIC(void)1122 void clear_local_APIC(void)
1123 {
1124 int maxlvt;
1125 u32 v;
1126
1127 /* APIC hasn't been mapped yet */
1128 if (!x2apic_mode && !apic_phys)
1129 return;
1130
1131 maxlvt = lapic_get_maxlvt();
1132 /*
1133 * Masking an LVT entry can trigger a local APIC error
1134 * if the vector is zero. Mask LVTERR first to prevent this.
1135 */
1136 if (maxlvt >= 3) {
1137 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1138 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1139 }
1140 /*
1141 * Careful: we have to set masks only first to deassert
1142 * any level-triggered sources.
1143 */
1144 v = apic_read(APIC_LVTT);
1145 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1146 v = apic_read(APIC_LVT0);
1147 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1148 v = apic_read(APIC_LVT1);
1149 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1150 if (maxlvt >= 4) {
1151 v = apic_read(APIC_LVTPC);
1152 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1153 }
1154
1155 /* lets not touch this if we didn't frob it */
1156 #ifdef CONFIG_X86_THERMAL_VECTOR
1157 if (maxlvt >= 5) {
1158 v = apic_read(APIC_LVTTHMR);
1159 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1160 }
1161 #endif
1162 #ifdef CONFIG_X86_MCE_INTEL
1163 if (maxlvt >= 6) {
1164 v = apic_read(APIC_LVTCMCI);
1165 if (!(v & APIC_LVT_MASKED))
1166 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1167 }
1168 #endif
1169
1170 /*
1171 * Clean APIC state for other OSs:
1172 */
1173 apic_write(APIC_LVTT, APIC_LVT_MASKED);
1174 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1175 apic_write(APIC_LVT1, APIC_LVT_MASKED);
1176 if (maxlvt >= 3)
1177 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1178 if (maxlvt >= 4)
1179 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1180
1181 /* Integrated APIC (!82489DX) ? */
1182 if (lapic_is_integrated()) {
1183 if (maxlvt > 3)
1184 /* Clear ESR due to Pentium errata 3AP and 11AP */
1185 apic_write(APIC_ESR, 0);
1186 apic_read(APIC_ESR);
1187 }
1188 }
1189
1190 /**
1191 * apic_soft_disable - Clears and software disables the local APIC on hotplug
1192 *
1193 * Contrary to disable_local_APIC() this does not touch the enable bit in
1194 * MSR_IA32_APICBASE. Clearing that bit on systems based on the 3 wire APIC
1195 * bus would require a hardware reset as the APIC would lose track of bus
1196 * arbitration. On systems with FSB delivery APICBASE could be disabled,
1197 * but it has to be guaranteed that no interrupt is sent to the APIC while
1198 * in that state and it's not clear from the SDM whether it still responds
1199 * to INIT/SIPI messages. Stay on the safe side and use software disable.
1200 */
apic_soft_disable(void)1201 void apic_soft_disable(void)
1202 {
1203 u32 value;
1204
1205 clear_local_APIC();
1206
1207 /* Soft disable APIC (implies clearing of registers for 82489DX!). */
1208 value = apic_read(APIC_SPIV);
1209 value &= ~APIC_SPIV_APIC_ENABLED;
1210 apic_write(APIC_SPIV, value);
1211 }
1212
1213 /**
1214 * disable_local_APIC - clear and disable the local APIC
1215 */
disable_local_APIC(void)1216 void disable_local_APIC(void)
1217 {
1218 /* APIC hasn't been mapped yet */
1219 if (!x2apic_mode && !apic_phys)
1220 return;
1221
1222 apic_soft_disable();
1223
1224 #ifdef CONFIG_X86_32
1225 /*
1226 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1227 * restore the disabled state.
1228 */
1229 if (enabled_via_apicbase) {
1230 unsigned int l, h;
1231
1232 rdmsr(MSR_IA32_APICBASE, l, h);
1233 l &= ~MSR_IA32_APICBASE_ENABLE;
1234 wrmsr(MSR_IA32_APICBASE, l, h);
1235 }
1236 #endif
1237 }
1238
1239 /*
1240 * If Linux enabled the LAPIC against the BIOS default disable it down before
1241 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1242 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1243 * for the case where Linux didn't enable the LAPIC.
1244 */
lapic_shutdown(void)1245 void lapic_shutdown(void)
1246 {
1247 unsigned long flags;
1248
1249 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1250 return;
1251
1252 local_irq_save(flags);
1253
1254 #ifdef CONFIG_X86_32
1255 if (!enabled_via_apicbase)
1256 clear_local_APIC();
1257 else
1258 #endif
1259 disable_local_APIC();
1260
1261
1262 local_irq_restore(flags);
1263 }
1264
1265 /**
1266 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1267 */
sync_Arb_IDs(void)1268 void __init sync_Arb_IDs(void)
1269 {
1270 /*
1271 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1272 * needed on AMD.
1273 */
1274 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1275 return;
1276
1277 /*
1278 * Wait for idle.
1279 */
1280 apic_wait_icr_idle();
1281
1282 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1283 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1284 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1285 }
1286
1287 enum apic_intr_mode_id apic_intr_mode __ro_after_init;
1288
__apic_intr_mode_select(void)1289 static int __init __apic_intr_mode_select(void)
1290 {
1291 /* Check kernel option */
1292 if (disable_apic) {
1293 pr_info("APIC disabled via kernel command line\n");
1294 return APIC_PIC;
1295 }
1296
1297 /* Check BIOS */
1298 #ifdef CONFIG_X86_64
1299 /* On 64-bit, the APIC must be integrated, Check local APIC only */
1300 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1301 disable_apic = 1;
1302 pr_info("APIC disabled by BIOS\n");
1303 return APIC_PIC;
1304 }
1305 #else
1306 /* On 32-bit, the APIC may be integrated APIC or 82489DX */
1307
1308 /* Neither 82489DX nor integrated APIC ? */
1309 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) {
1310 disable_apic = 1;
1311 return APIC_PIC;
1312 }
1313
1314 /* If the BIOS pretends there is an integrated APIC ? */
1315 if (!boot_cpu_has(X86_FEATURE_APIC) &&
1316 APIC_INTEGRATED(boot_cpu_apic_version)) {
1317 disable_apic = 1;
1318 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n",
1319 boot_cpu_physical_apicid);
1320 return APIC_PIC;
1321 }
1322 #endif
1323
1324 /* Check MP table or ACPI MADT configuration */
1325 if (!smp_found_config) {
1326 disable_ioapic_support();
1327 if (!acpi_lapic) {
1328 pr_info("APIC: ACPI MADT or MP tables are not detected\n");
1329 return APIC_VIRTUAL_WIRE_NO_CONFIG;
1330 }
1331 return APIC_VIRTUAL_WIRE;
1332 }
1333
1334 #ifdef CONFIG_SMP
1335 /* If SMP should be disabled, then really disable it! */
1336 if (!setup_max_cpus) {
1337 pr_info("APIC: SMP mode deactivated\n");
1338 return APIC_SYMMETRIC_IO_NO_ROUTING;
1339 }
1340
1341 if (read_apic_id() != boot_cpu_physical_apicid) {
1342 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1343 read_apic_id(), boot_cpu_physical_apicid);
1344 /* Or can we switch back to PIC here? */
1345 }
1346 #endif
1347
1348 return APIC_SYMMETRIC_IO;
1349 }
1350
1351 /* Select the interrupt delivery mode for the BSP */
apic_intr_mode_select(void)1352 void __init apic_intr_mode_select(void)
1353 {
1354 apic_intr_mode = __apic_intr_mode_select();
1355 }
1356
1357 /*
1358 * An initial setup of the virtual wire mode.
1359 */
init_bsp_APIC(void)1360 void __init init_bsp_APIC(void)
1361 {
1362 unsigned int value;
1363
1364 /*
1365 * Don't do the setup now if we have a SMP BIOS as the
1366 * through-I/O-APIC virtual wire mode might be active.
1367 */
1368 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1369 return;
1370
1371 /*
1372 * Do not trust the local APIC being empty at bootup.
1373 */
1374 clear_local_APIC();
1375
1376 /*
1377 * Enable APIC.
1378 */
1379 value = apic_read(APIC_SPIV);
1380 value &= ~APIC_VECTOR_MASK;
1381 value |= APIC_SPIV_APIC_ENABLED;
1382
1383 #ifdef CONFIG_X86_32
1384 /* This bit is reserved on P4/Xeon and should be cleared */
1385 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1386 (boot_cpu_data.x86 == 15))
1387 value &= ~APIC_SPIV_FOCUS_DISABLED;
1388 else
1389 #endif
1390 value |= APIC_SPIV_FOCUS_DISABLED;
1391 value |= SPURIOUS_APIC_VECTOR;
1392 apic_write(APIC_SPIV, value);
1393
1394 /*
1395 * Set up the virtual wire mode.
1396 */
1397 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1398 value = APIC_DM_NMI;
1399 if (!lapic_is_integrated()) /* 82489DX */
1400 value |= APIC_LVT_LEVEL_TRIGGER;
1401 if (apic_extnmi == APIC_EXTNMI_NONE)
1402 value |= APIC_LVT_MASKED;
1403 apic_write(APIC_LVT1, value);
1404 }
1405
1406 static void __init apic_bsp_setup(bool upmode);
1407
1408 /* Init the interrupt delivery mode for the BSP */
apic_intr_mode_init(void)1409 void __init apic_intr_mode_init(void)
1410 {
1411 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT);
1412
1413 switch (apic_intr_mode) {
1414 case APIC_PIC:
1415 pr_info("APIC: Keep in PIC mode(8259)\n");
1416 return;
1417 case APIC_VIRTUAL_WIRE:
1418 pr_info("APIC: Switch to virtual wire mode setup\n");
1419 default_setup_apic_routing();
1420 break;
1421 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1422 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n");
1423 upmode = true;
1424 default_setup_apic_routing();
1425 break;
1426 case APIC_SYMMETRIC_IO:
1427 pr_info("APIC: Switch to symmetric I/O mode setup\n");
1428 default_setup_apic_routing();
1429 break;
1430 case APIC_SYMMETRIC_IO_NO_ROUTING:
1431 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n");
1432 break;
1433 }
1434
1435 if (x86_platform.apic_post_init)
1436 x86_platform.apic_post_init();
1437
1438 apic_bsp_setup(upmode);
1439 }
1440
lapic_setup_esr(void)1441 static void lapic_setup_esr(void)
1442 {
1443 unsigned int oldvalue, value, maxlvt;
1444
1445 if (!lapic_is_integrated()) {
1446 pr_info("No ESR for 82489DX.\n");
1447 return;
1448 }
1449
1450 if (apic->disable_esr) {
1451 /*
1452 * Something untraceable is creating bad interrupts on
1453 * secondary quads ... for the moment, just leave the
1454 * ESR disabled - we can't do anything useful with the
1455 * errors anyway - mbligh
1456 */
1457 pr_info("Leaving ESR disabled.\n");
1458 return;
1459 }
1460
1461 maxlvt = lapic_get_maxlvt();
1462 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1463 apic_write(APIC_ESR, 0);
1464 oldvalue = apic_read(APIC_ESR);
1465
1466 /* enables sending errors */
1467 value = ERROR_APIC_VECTOR;
1468 apic_write(APIC_LVTERR, value);
1469
1470 /*
1471 * spec says clear errors after enabling vector.
1472 */
1473 if (maxlvt > 3)
1474 apic_write(APIC_ESR, 0);
1475 value = apic_read(APIC_ESR);
1476 if (value != oldvalue)
1477 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1478 "vector: 0x%08x after: 0x%08x\n",
1479 oldvalue, value);
1480 }
1481
1482 #define APIC_IR_REGS APIC_ISR_NR
1483 #define APIC_IR_BITS (APIC_IR_REGS * 32)
1484 #define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG)
1485
1486 union apic_ir {
1487 unsigned long map[APIC_IR_MAPSIZE];
1488 u32 regs[APIC_IR_REGS];
1489 };
1490
apic_check_and_ack(union apic_ir * irr,union apic_ir * isr)1491 static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr)
1492 {
1493 int i, bit;
1494
1495 /* Read the IRRs */
1496 for (i = 0; i < APIC_IR_REGS; i++)
1497 irr->regs[i] = apic_read(APIC_IRR + i * 0x10);
1498
1499 /* Read the ISRs */
1500 for (i = 0; i < APIC_IR_REGS; i++)
1501 isr->regs[i] = apic_read(APIC_ISR + i * 0x10);
1502
1503 /*
1504 * If the ISR map is not empty. ACK the APIC and run another round
1505 * to verify whether a pending IRR has been unblocked and turned
1506 * into a ISR.
1507 */
1508 if (!bitmap_empty(isr->map, APIC_IR_BITS)) {
1509 /*
1510 * There can be multiple ISR bits set when a high priority
1511 * interrupt preempted a lower priority one. Issue an ACK
1512 * per set bit.
1513 */
1514 for_each_set_bit(bit, isr->map, APIC_IR_BITS)
1515 ack_APIC_irq();
1516 return true;
1517 }
1518
1519 return !bitmap_empty(irr->map, APIC_IR_BITS);
1520 }
1521
1522 /*
1523 * After a crash, we no longer service the interrupts and a pending
1524 * interrupt from previous kernel might still have ISR bit set.
1525 *
1526 * Most probably by now the CPU has serviced that pending interrupt and it
1527 * might not have done the ack_APIC_irq() because it thought, interrupt
1528 * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear
1529 * the ISR bit and cpu thinks it has already serivced the interrupt. Hence
1530 * a vector might get locked. It was noticed for timer irq (vector
1531 * 0x31). Issue an extra EOI to clear ISR.
1532 *
1533 * If there are pending IRR bits they turn into ISR bits after a higher
1534 * priority ISR bit has been acked.
1535 */
apic_pending_intr_clear(void)1536 static void apic_pending_intr_clear(void)
1537 {
1538 union apic_ir irr, isr;
1539 unsigned int i;
1540
1541 /* 512 loops are way oversized and give the APIC a chance to obey. */
1542 for (i = 0; i < 512; i++) {
1543 if (!apic_check_and_ack(&irr, &isr))
1544 return;
1545 }
1546 /* Dump the IRR/ISR content if that failed */
1547 pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map);
1548 }
1549
1550 /**
1551 * setup_local_APIC - setup the local APIC
1552 *
1553 * Used to setup local APIC while initializing BSP or bringing up APs.
1554 * Always called with preemption disabled.
1555 */
setup_local_APIC(void)1556 static void setup_local_APIC(void)
1557 {
1558 int cpu = smp_processor_id();
1559 unsigned int value;
1560
1561 if (disable_apic) {
1562 disable_ioapic_support();
1563 return;
1564 }
1565
1566 /*
1567 * If this comes from kexec/kcrash the APIC might be enabled in
1568 * SPIV. Soft disable it before doing further initialization.
1569 */
1570 value = apic_read(APIC_SPIV);
1571 value &= ~APIC_SPIV_APIC_ENABLED;
1572 apic_write(APIC_SPIV, value);
1573
1574 #ifdef CONFIG_X86_32
1575 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1576 if (lapic_is_integrated() && apic->disable_esr) {
1577 apic_write(APIC_ESR, 0);
1578 apic_write(APIC_ESR, 0);
1579 apic_write(APIC_ESR, 0);
1580 apic_write(APIC_ESR, 0);
1581 }
1582 #endif
1583 /*
1584 * Double-check whether this APIC is really registered.
1585 * This is meaningless in clustered apic mode, so we skip it.
1586 */
1587 BUG_ON(!apic->apic_id_registered());
1588
1589 /*
1590 * Intel recommends to set DFR, LDR and TPR before enabling
1591 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1592 * document number 292116). So here it goes...
1593 */
1594 apic->init_apic_ldr();
1595
1596 #ifdef CONFIG_X86_32
1597 if (apic->dest_logical) {
1598 int logical_apicid, ldr_apicid;
1599
1600 /*
1601 * APIC LDR is initialized. If logical_apicid mapping was
1602 * initialized during get_smp_config(), make sure it matches
1603 * the actual value.
1604 */
1605 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1606 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1607 if (logical_apicid != BAD_APICID)
1608 WARN_ON(logical_apicid != ldr_apicid);
1609 /* Always use the value from LDR. */
1610 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid;
1611 }
1612 #endif
1613
1614 /*
1615 * Set Task Priority to 'accept all except vectors 0-31'. An APIC
1616 * vector in the 16-31 range could be delivered if TPR == 0, but we
1617 * would think it's an exception and terrible things will happen. We
1618 * never change this later on.
1619 */
1620 value = apic_read(APIC_TASKPRI);
1621 value &= ~APIC_TPRI_MASK;
1622 value |= 0x10;
1623 apic_write(APIC_TASKPRI, value);
1624
1625 /* Clear eventually stale ISR/IRR bits */
1626 apic_pending_intr_clear();
1627
1628 /*
1629 * Now that we are all set up, enable the APIC
1630 */
1631 value = apic_read(APIC_SPIV);
1632 value &= ~APIC_VECTOR_MASK;
1633 /*
1634 * Enable APIC
1635 */
1636 value |= APIC_SPIV_APIC_ENABLED;
1637
1638 #ifdef CONFIG_X86_32
1639 /*
1640 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1641 * certain networking cards. If high frequency interrupts are
1642 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1643 * entry is masked/unmasked at a high rate as well then sooner or
1644 * later IOAPIC line gets 'stuck', no more interrupts are received
1645 * from the device. If focus CPU is disabled then the hang goes
1646 * away, oh well :-(
1647 *
1648 * [ This bug can be reproduced easily with a level-triggered
1649 * PCI Ne2000 networking cards and PII/PIII processors, dual
1650 * BX chipset. ]
1651 */
1652 /*
1653 * Actually disabling the focus CPU check just makes the hang less
1654 * frequent as it makes the interrupt distributon model be more
1655 * like LRU than MRU (the short-term load is more even across CPUs).
1656 */
1657
1658 /*
1659 * - enable focus processor (bit==0)
1660 * - 64bit mode always use processor focus
1661 * so no need to set it
1662 */
1663 value &= ~APIC_SPIV_FOCUS_DISABLED;
1664 #endif
1665
1666 /*
1667 * Set spurious IRQ vector
1668 */
1669 value |= SPURIOUS_APIC_VECTOR;
1670 apic_write(APIC_SPIV, value);
1671
1672 perf_events_lapic_init();
1673
1674 /*
1675 * Set up LVT0, LVT1:
1676 *
1677 * set up through-local-APIC on the boot CPU's LINT0. This is not
1678 * strictly necessary in pure symmetric-IO mode, but sometimes
1679 * we delegate interrupts to the 8259A.
1680 */
1681 /*
1682 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1683 */
1684 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1685 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) {
1686 value = APIC_DM_EXTINT;
1687 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1688 } else {
1689 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1690 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1691 }
1692 apic_write(APIC_LVT0, value);
1693
1694 /*
1695 * Only the BSP sees the LINT1 NMI signal by default. This can be
1696 * modified by apic_extnmi= boot option.
1697 */
1698 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1699 apic_extnmi == APIC_EXTNMI_ALL)
1700 value = APIC_DM_NMI;
1701 else
1702 value = APIC_DM_NMI | APIC_LVT_MASKED;
1703
1704 /* Is 82489DX ? */
1705 if (!lapic_is_integrated())
1706 value |= APIC_LVT_LEVEL_TRIGGER;
1707 apic_write(APIC_LVT1, value);
1708
1709 #ifdef CONFIG_X86_MCE_INTEL
1710 /* Recheck CMCI information after local APIC is up on CPU #0 */
1711 if (!cpu)
1712 cmci_recheck();
1713 #endif
1714 }
1715
end_local_APIC_setup(void)1716 static void end_local_APIC_setup(void)
1717 {
1718 lapic_setup_esr();
1719
1720 #ifdef CONFIG_X86_32
1721 {
1722 unsigned int value;
1723 /* Disable the local apic timer */
1724 value = apic_read(APIC_LVTT);
1725 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1726 apic_write(APIC_LVTT, value);
1727 }
1728 #endif
1729
1730 apic_pm_activate();
1731 }
1732
1733 /*
1734 * APIC setup function for application processors. Called from smpboot.c
1735 */
apic_ap_setup(void)1736 void apic_ap_setup(void)
1737 {
1738 setup_local_APIC();
1739 end_local_APIC_setup();
1740 }
1741
1742 #ifdef CONFIG_X86_X2APIC
1743 int x2apic_mode;
1744
1745 enum {
1746 X2APIC_OFF,
1747 X2APIC_ON,
1748 X2APIC_DISABLED,
1749 };
1750 static int x2apic_state;
1751
__x2apic_disable(void)1752 static void __x2apic_disable(void)
1753 {
1754 u64 msr;
1755
1756 if (!boot_cpu_has(X86_FEATURE_APIC))
1757 return;
1758
1759 rdmsrl(MSR_IA32_APICBASE, msr);
1760 if (!(msr & X2APIC_ENABLE))
1761 return;
1762 /* Disable xapic and x2apic first and then reenable xapic mode */
1763 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1764 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1765 printk_once(KERN_INFO "x2apic disabled\n");
1766 }
1767
__x2apic_enable(void)1768 static void __x2apic_enable(void)
1769 {
1770 u64 msr;
1771
1772 rdmsrl(MSR_IA32_APICBASE, msr);
1773 if (msr & X2APIC_ENABLE)
1774 return;
1775 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1776 printk_once(KERN_INFO "x2apic enabled\n");
1777 }
1778
setup_nox2apic(char * str)1779 static int __init setup_nox2apic(char *str)
1780 {
1781 if (x2apic_enabled()) {
1782 int apicid = native_apic_msr_read(APIC_ID);
1783
1784 if (apicid >= 255) {
1785 pr_warn("Apicid: %08x, cannot enforce nox2apic\n",
1786 apicid);
1787 return 0;
1788 }
1789 pr_warn("x2apic already enabled.\n");
1790 __x2apic_disable();
1791 }
1792 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1793 x2apic_state = X2APIC_DISABLED;
1794 x2apic_mode = 0;
1795 return 0;
1796 }
1797 early_param("nox2apic", setup_nox2apic);
1798
1799 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
x2apic_setup(void)1800 void x2apic_setup(void)
1801 {
1802 /*
1803 * If x2apic is not in ON state, disable it if already enabled
1804 * from BIOS.
1805 */
1806 if (x2apic_state != X2APIC_ON) {
1807 __x2apic_disable();
1808 return;
1809 }
1810 __x2apic_enable();
1811 }
1812
x2apic_disable(void)1813 static __init void x2apic_disable(void)
1814 {
1815 u32 x2apic_id, state = x2apic_state;
1816
1817 x2apic_mode = 0;
1818 x2apic_state = X2APIC_DISABLED;
1819
1820 if (state != X2APIC_ON)
1821 return;
1822
1823 x2apic_id = read_apic_id();
1824 if (x2apic_id >= 255)
1825 panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1826
1827 __x2apic_disable();
1828 register_lapic_address(mp_lapic_addr);
1829 }
1830
x2apic_enable(void)1831 static __init void x2apic_enable(void)
1832 {
1833 if (x2apic_state != X2APIC_OFF)
1834 return;
1835
1836 x2apic_mode = 1;
1837 x2apic_state = X2APIC_ON;
1838 __x2apic_enable();
1839 }
1840
try_to_enable_x2apic(int remap_mode)1841 static __init void try_to_enable_x2apic(int remap_mode)
1842 {
1843 if (x2apic_state == X2APIC_DISABLED)
1844 return;
1845
1846 if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1847 /*
1848 * Using X2APIC without IR is not architecturally supported
1849 * on bare metal but may be supported in guests.
1850 */
1851 if (!x86_init.hyper.x2apic_available()) {
1852 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1853 x2apic_disable();
1854 return;
1855 }
1856
1857 /*
1858 * Without IR, all CPUs can be addressed by IOAPIC/MSI only
1859 * in physical mode, and CPUs with an APIC ID that cannnot
1860 * be addressed must not be brought online.
1861 */
1862 x2apic_set_max_apicid(255);
1863 x2apic_phys = 1;
1864 }
1865 x2apic_enable();
1866 }
1867
check_x2apic(void)1868 void __init check_x2apic(void)
1869 {
1870 if (x2apic_enabled()) {
1871 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1872 x2apic_mode = 1;
1873 x2apic_state = X2APIC_ON;
1874 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1875 x2apic_state = X2APIC_DISABLED;
1876 }
1877 }
1878 #else /* CONFIG_X86_X2APIC */
validate_x2apic(void)1879 static int __init validate_x2apic(void)
1880 {
1881 if (!apic_is_x2apic_enabled())
1882 return 0;
1883 /*
1884 * Checkme: Can we simply turn off x2apic here instead of panic?
1885 */
1886 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1887 }
1888 early_initcall(validate_x2apic);
1889
try_to_enable_x2apic(int remap_mode)1890 static inline void try_to_enable_x2apic(int remap_mode) { }
__x2apic_enable(void)1891 static inline void __x2apic_enable(void) { }
1892 #endif /* !CONFIG_X86_X2APIC */
1893
enable_IR_x2apic(void)1894 void __init enable_IR_x2apic(void)
1895 {
1896 unsigned long flags;
1897 int ret, ir_stat;
1898
1899 if (skip_ioapic_setup) {
1900 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1901 return;
1902 }
1903
1904 ir_stat = irq_remapping_prepare();
1905 if (ir_stat < 0 && !x2apic_supported())
1906 return;
1907
1908 ret = save_ioapic_entries();
1909 if (ret) {
1910 pr_info("Saving IO-APIC state failed: %d\n", ret);
1911 return;
1912 }
1913
1914 local_irq_save(flags);
1915 legacy_pic->mask_all();
1916 mask_ioapic_entries();
1917
1918 /* If irq_remapping_prepare() succeeded, try to enable it */
1919 if (ir_stat >= 0)
1920 ir_stat = irq_remapping_enable();
1921 /* ir_stat contains the remap mode or an error code */
1922 try_to_enable_x2apic(ir_stat);
1923
1924 if (ir_stat < 0)
1925 restore_ioapic_entries();
1926 legacy_pic->restore_mask();
1927 local_irq_restore(flags);
1928 }
1929
1930 #ifdef CONFIG_X86_64
1931 /*
1932 * Detect and enable local APICs on non-SMP boards.
1933 * Original code written by Keir Fraser.
1934 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1935 * not correctly set up (usually the APIC timer won't work etc.)
1936 */
detect_init_APIC(void)1937 static int __init detect_init_APIC(void)
1938 {
1939 if (!boot_cpu_has(X86_FEATURE_APIC)) {
1940 pr_info("No local APIC present\n");
1941 return -1;
1942 }
1943
1944 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1945 return 0;
1946 }
1947 #else
1948
apic_verify(void)1949 static int __init apic_verify(void)
1950 {
1951 u32 features, h, l;
1952
1953 /*
1954 * The APIC feature bit should now be enabled
1955 * in `cpuid'
1956 */
1957 features = cpuid_edx(1);
1958 if (!(features & (1 << X86_FEATURE_APIC))) {
1959 pr_warn("Could not enable APIC!\n");
1960 return -1;
1961 }
1962 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1963 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1964
1965 /* The BIOS may have set up the APIC at some other address */
1966 if (boot_cpu_data.x86 >= 6) {
1967 rdmsr(MSR_IA32_APICBASE, l, h);
1968 if (l & MSR_IA32_APICBASE_ENABLE)
1969 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1970 }
1971
1972 pr_info("Found and enabled local APIC!\n");
1973 return 0;
1974 }
1975
apic_force_enable(unsigned long addr)1976 int __init apic_force_enable(unsigned long addr)
1977 {
1978 u32 h, l;
1979
1980 if (disable_apic)
1981 return -1;
1982
1983 /*
1984 * Some BIOSes disable the local APIC in the APIC_BASE
1985 * MSR. This can only be done in software for Intel P6 or later
1986 * and AMD K7 (Model > 1) or later.
1987 */
1988 if (boot_cpu_data.x86 >= 6) {
1989 rdmsr(MSR_IA32_APICBASE, l, h);
1990 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1991 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1992 l &= ~MSR_IA32_APICBASE_BASE;
1993 l |= MSR_IA32_APICBASE_ENABLE | addr;
1994 wrmsr(MSR_IA32_APICBASE, l, h);
1995 enabled_via_apicbase = 1;
1996 }
1997 }
1998 return apic_verify();
1999 }
2000
2001 /*
2002 * Detect and initialize APIC
2003 */
detect_init_APIC(void)2004 static int __init detect_init_APIC(void)
2005 {
2006 /* Disabled by kernel option? */
2007 if (disable_apic)
2008 return -1;
2009
2010 switch (boot_cpu_data.x86_vendor) {
2011 case X86_VENDOR_AMD:
2012 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
2013 (boot_cpu_data.x86 >= 15))
2014 break;
2015 goto no_apic;
2016 case X86_VENDOR_HYGON:
2017 break;
2018 case X86_VENDOR_INTEL:
2019 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
2020 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
2021 break;
2022 goto no_apic;
2023 default:
2024 goto no_apic;
2025 }
2026
2027 if (!boot_cpu_has(X86_FEATURE_APIC)) {
2028 /*
2029 * Over-ride BIOS and try to enable the local APIC only if
2030 * "lapic" specified.
2031 */
2032 if (!force_enable_local_apic) {
2033 pr_info("Local APIC disabled by BIOS -- "
2034 "you can enable it with \"lapic\"\n");
2035 return -1;
2036 }
2037 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
2038 return -1;
2039 } else {
2040 if (apic_verify())
2041 return -1;
2042 }
2043
2044 apic_pm_activate();
2045
2046 return 0;
2047
2048 no_apic:
2049 pr_info("No local APIC present or hardware disabled\n");
2050 return -1;
2051 }
2052 #endif
2053
2054 /**
2055 * init_apic_mappings - initialize APIC mappings
2056 */
init_apic_mappings(void)2057 void __init init_apic_mappings(void)
2058 {
2059 unsigned int new_apicid;
2060
2061 if (apic_validate_deadline_timer())
2062 pr_info("TSC deadline timer available\n");
2063
2064 if (x2apic_mode) {
2065 boot_cpu_physical_apicid = read_apic_id();
2066 return;
2067 }
2068
2069 /* If no local APIC can be found return early */
2070 if (!smp_found_config && detect_init_APIC()) {
2071 /* lets NOP'ify apic operations */
2072 pr_info("APIC: disable apic facility\n");
2073 apic_disable();
2074 } else {
2075 apic_phys = mp_lapic_addr;
2076
2077 /*
2078 * If the system has ACPI MADT tables or MP info, the LAPIC
2079 * address is already registered.
2080 */
2081 if (!acpi_lapic && !smp_found_config)
2082 register_lapic_address(apic_phys);
2083 }
2084
2085 /*
2086 * Fetch the APIC ID of the BSP in case we have a
2087 * default configuration (or the MP table is broken).
2088 */
2089 new_apicid = read_apic_id();
2090 if (boot_cpu_physical_apicid != new_apicid) {
2091 boot_cpu_physical_apicid = new_apicid;
2092 /*
2093 * yeah -- we lie about apic_version
2094 * in case if apic was disabled via boot option
2095 * but it's not a problem for SMP compiled kernel
2096 * since apic_intr_mode_select is prepared for such
2097 * a case and disable smp mode
2098 */
2099 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2100 }
2101 }
2102
register_lapic_address(unsigned long address)2103 void __init register_lapic_address(unsigned long address)
2104 {
2105 mp_lapic_addr = address;
2106
2107 if (!x2apic_mode) {
2108 set_fixmap_nocache(FIX_APIC_BASE, address);
2109 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
2110 APIC_BASE, address);
2111 }
2112 if (boot_cpu_physical_apicid == -1U) {
2113 boot_cpu_physical_apicid = read_apic_id();
2114 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
2115 }
2116 }
2117
2118 /*
2119 * Local APIC interrupts
2120 */
2121
2122 /**
2123 * spurious_interrupt - Catch all for interrupts raised on unused vectors
2124 * @regs: Pointer to pt_regs on stack
2125 * @vector: The vector number
2126 *
2127 * This is invoked from ASM entry code to catch all interrupts which
2128 * trigger on an entry which is routed to the common_spurious idtentry
2129 * point.
2130 *
2131 * Also called from sysvec_spurious_apic_interrupt().
2132 */
DEFINE_IDTENTRY_IRQ(spurious_interrupt)2133 DEFINE_IDTENTRY_IRQ(spurious_interrupt)
2134 {
2135 u32 v;
2136
2137 trace_spurious_apic_entry(vector);
2138
2139 inc_irq_stat(irq_spurious_count);
2140
2141 /*
2142 * If this is a spurious interrupt then do not acknowledge
2143 */
2144 if (vector == SPURIOUS_APIC_VECTOR) {
2145 /* See SDM vol 3 */
2146 pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n",
2147 smp_processor_id());
2148 goto out;
2149 }
2150
2151 /*
2152 * If it is a vectored one, verify it's set in the ISR. If set,
2153 * acknowledge it.
2154 */
2155 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
2156 if (v & (1 << (vector & 0x1f))) {
2157 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n",
2158 vector, smp_processor_id());
2159 ack_APIC_irq();
2160 } else {
2161 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n",
2162 vector, smp_processor_id());
2163 }
2164 out:
2165 trace_spurious_apic_exit(vector);
2166 }
2167
DEFINE_IDTENTRY_SYSVEC(sysvec_spurious_apic_interrupt)2168 DEFINE_IDTENTRY_SYSVEC(sysvec_spurious_apic_interrupt)
2169 {
2170 __spurious_interrupt(regs, SPURIOUS_APIC_VECTOR);
2171 }
2172
2173 /*
2174 * This interrupt should never happen with our APIC/SMP architecture
2175 */
DEFINE_IDTENTRY_SYSVEC(sysvec_error_interrupt)2176 DEFINE_IDTENTRY_SYSVEC(sysvec_error_interrupt)
2177 {
2178 static const char * const error_interrupt_reason[] = {
2179 "Send CS error", /* APIC Error Bit 0 */
2180 "Receive CS error", /* APIC Error Bit 1 */
2181 "Send accept error", /* APIC Error Bit 2 */
2182 "Receive accept error", /* APIC Error Bit 3 */
2183 "Redirectable IPI", /* APIC Error Bit 4 */
2184 "Send illegal vector", /* APIC Error Bit 5 */
2185 "Received illegal vector", /* APIC Error Bit 6 */
2186 "Illegal register address", /* APIC Error Bit 7 */
2187 };
2188 u32 v, i = 0;
2189
2190 trace_error_apic_entry(ERROR_APIC_VECTOR);
2191
2192 /* First tickle the hardware, only then report what went on. -- REW */
2193 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */
2194 apic_write(APIC_ESR, 0);
2195 v = apic_read(APIC_ESR);
2196 ack_APIC_irq();
2197 atomic_inc(&irq_err_count);
2198
2199 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
2200 smp_processor_id(), v);
2201
2202 v &= 0xff;
2203 while (v) {
2204 if (v & 0x1)
2205 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
2206 i++;
2207 v >>= 1;
2208 }
2209
2210 apic_printk(APIC_DEBUG, KERN_CONT "\n");
2211
2212 trace_error_apic_exit(ERROR_APIC_VECTOR);
2213 }
2214
2215 /**
2216 * connect_bsp_APIC - attach the APIC to the interrupt system
2217 */
connect_bsp_APIC(void)2218 static void __init connect_bsp_APIC(void)
2219 {
2220 #ifdef CONFIG_X86_32
2221 if (pic_mode) {
2222 /*
2223 * Do not trust the local APIC being empty at bootup.
2224 */
2225 clear_local_APIC();
2226 /*
2227 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
2228 * local APIC to INT and NMI lines.
2229 */
2230 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
2231 "enabling APIC mode.\n");
2232 imcr_pic_to_apic();
2233 }
2234 #endif
2235 }
2236
2237 /**
2238 * disconnect_bsp_APIC - detach the APIC from the interrupt system
2239 * @virt_wire_setup: indicates, whether virtual wire mode is selected
2240 *
2241 * Virtual wire mode is necessary to deliver legacy interrupts even when the
2242 * APIC is disabled.
2243 */
disconnect_bsp_APIC(int virt_wire_setup)2244 void disconnect_bsp_APIC(int virt_wire_setup)
2245 {
2246 unsigned int value;
2247
2248 #ifdef CONFIG_X86_32
2249 if (pic_mode) {
2250 /*
2251 * Put the board back into PIC mode (has an effect only on
2252 * certain older boards). Note that APIC interrupts, including
2253 * IPIs, won't work beyond this point! The only exception are
2254 * INIT IPIs.
2255 */
2256 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
2257 "entering PIC mode.\n");
2258 imcr_apic_to_pic();
2259 return;
2260 }
2261 #endif
2262
2263 /* Go back to Virtual Wire compatibility mode */
2264
2265 /* For the spurious interrupt use vector F, and enable it */
2266 value = apic_read(APIC_SPIV);
2267 value &= ~APIC_VECTOR_MASK;
2268 value |= APIC_SPIV_APIC_ENABLED;
2269 value |= 0xf;
2270 apic_write(APIC_SPIV, value);
2271
2272 if (!virt_wire_setup) {
2273 /*
2274 * For LVT0 make it edge triggered, active high,
2275 * external and enabled
2276 */
2277 value = apic_read(APIC_LVT0);
2278 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2279 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2280 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2281 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2282 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2283 apic_write(APIC_LVT0, value);
2284 } else {
2285 /* Disable LVT0 */
2286 apic_write(APIC_LVT0, APIC_LVT_MASKED);
2287 }
2288
2289 /*
2290 * For LVT1 make it edge triggered, active high,
2291 * nmi and enabled
2292 */
2293 value = apic_read(APIC_LVT1);
2294 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2295 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2296 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2297 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2298 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2299 apic_write(APIC_LVT1, value);
2300 }
2301
2302 /*
2303 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2304 * contiguously, it equals to current allocated max logical CPU ID plus 1.
2305 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range,
2306 * so the maximum of nr_logical_cpuids is nr_cpu_ids.
2307 *
2308 * NOTE: Reserve 0 for BSP.
2309 */
2310 static int nr_logical_cpuids = 1;
2311
2312 /*
2313 * Used to store mapping between logical CPU IDs and APIC IDs.
2314 */
2315 static int cpuid_to_apicid[] = {
2316 [0 ... NR_CPUS - 1] = -1,
2317 };
2318
arch_match_cpu_phys_id(int cpu,u64 phys_id)2319 bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
2320 {
2321 return phys_id == cpuid_to_apicid[cpu];
2322 }
2323
2324 #ifdef CONFIG_SMP
2325 /**
2326 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread
2327 * @apicid: APIC ID to check
2328 */
apic_id_is_primary_thread(unsigned int apicid)2329 bool apic_id_is_primary_thread(unsigned int apicid)
2330 {
2331 u32 mask;
2332
2333 if (smp_num_siblings == 1)
2334 return true;
2335 /* Isolate the SMT bit(s) in the APICID and check for 0 */
2336 mask = (1U << (fls(smp_num_siblings) - 1)) - 1;
2337 return !(apicid & mask);
2338 }
2339 #endif
2340
2341 /*
2342 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2343 * and cpuid_to_apicid[] synchronized.
2344 */
allocate_logical_cpuid(int apicid)2345 static int allocate_logical_cpuid(int apicid)
2346 {
2347 int i;
2348
2349 /*
2350 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2351 * check if the kernel has allocated a cpuid for it.
2352 */
2353 for (i = 0; i < nr_logical_cpuids; i++) {
2354 if (cpuid_to_apicid[i] == apicid)
2355 return i;
2356 }
2357
2358 /* Allocate a new cpuid. */
2359 if (nr_logical_cpuids >= nr_cpu_ids) {
2360 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. "
2361 "Processor %d/0x%x and the rest are ignored.\n",
2362 nr_cpu_ids, nr_logical_cpuids, apicid);
2363 return -EINVAL;
2364 }
2365
2366 cpuid_to_apicid[nr_logical_cpuids] = apicid;
2367 return nr_logical_cpuids++;
2368 }
2369
generic_processor_info(int apicid,int version)2370 int generic_processor_info(int apicid, int version)
2371 {
2372 int cpu, max = nr_cpu_ids;
2373 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2374 phys_cpu_present_map);
2375
2376 /*
2377 * boot_cpu_physical_apicid is designed to have the apicid
2378 * returned by read_apic_id(), i.e, the apicid of the
2379 * currently booting-up processor. However, on some platforms,
2380 * it is temporarily modified by the apicid reported as BSP
2381 * through MP table. Concretely:
2382 *
2383 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2384 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2385 *
2386 * This function is executed with the modified
2387 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2388 * parameter doesn't work to disable APs on kdump 2nd kernel.
2389 *
2390 * Since fixing handling of boot_cpu_physical_apicid requires
2391 * another discussion and tests on each platform, we leave it
2392 * for now and here we use read_apic_id() directly in this
2393 * function, generic_processor_info().
2394 */
2395 if (disabled_cpu_apicid != BAD_APICID &&
2396 disabled_cpu_apicid != read_apic_id() &&
2397 disabled_cpu_apicid == apicid) {
2398 int thiscpu = num_processors + disabled_cpus;
2399
2400 pr_warn("APIC: Disabling requested cpu."
2401 " Processor %d/0x%x ignored.\n", thiscpu, apicid);
2402
2403 disabled_cpus++;
2404 return -ENODEV;
2405 }
2406
2407 /*
2408 * If boot cpu has not been detected yet, then only allow upto
2409 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2410 */
2411 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2412 apicid != boot_cpu_physical_apicid) {
2413 int thiscpu = max + disabled_cpus - 1;
2414
2415 pr_warn("APIC: NR_CPUS/possible_cpus limit of %i almost"
2416 " reached. Keeping one slot for boot cpu."
2417 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2418
2419 disabled_cpus++;
2420 return -ENODEV;
2421 }
2422
2423 if (num_processors >= nr_cpu_ids) {
2424 int thiscpu = max + disabled_cpus;
2425
2426 pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. "
2427 "Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2428
2429 disabled_cpus++;
2430 return -EINVAL;
2431 }
2432
2433 if (apicid == boot_cpu_physical_apicid) {
2434 /*
2435 * x86_bios_cpu_apicid is required to have processors listed
2436 * in same order as logical cpu numbers. Hence the first
2437 * entry is BSP, and so on.
2438 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2439 * for BSP.
2440 */
2441 cpu = 0;
2442
2443 /* Logical cpuid 0 is reserved for BSP. */
2444 cpuid_to_apicid[0] = apicid;
2445 } else {
2446 cpu = allocate_logical_cpuid(apicid);
2447 if (cpu < 0) {
2448 disabled_cpus++;
2449 return -EINVAL;
2450 }
2451 }
2452
2453 /*
2454 * Validate version
2455 */
2456 if (version == 0x0) {
2457 pr_warn("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2458 cpu, apicid);
2459 version = 0x10;
2460 }
2461
2462 if (version != boot_cpu_apic_version) {
2463 pr_warn("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2464 boot_cpu_apic_version, cpu, version);
2465 }
2466
2467 if (apicid > max_physical_apicid)
2468 max_physical_apicid = apicid;
2469
2470 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2471 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2472 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2473 #endif
2474 #ifdef CONFIG_X86_32
2475 early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2476 apic->x86_32_early_logical_apicid(cpu);
2477 #endif
2478 set_cpu_possible(cpu, true);
2479 physid_set(apicid, phys_cpu_present_map);
2480 set_cpu_present(cpu, true);
2481 num_processors++;
2482
2483 return cpu;
2484 }
2485
hard_smp_processor_id(void)2486 int hard_smp_processor_id(void)
2487 {
2488 return read_apic_id();
2489 }
2490
2491 /*
2492 * Override the generic EOI implementation with an optimized version.
2493 * Only called during early boot when only one CPU is active and with
2494 * interrupts disabled, so we know this does not race with actual APIC driver
2495 * use.
2496 */
apic_set_eoi_write(void (* eoi_write)(u32 reg,u32 v))2497 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2498 {
2499 struct apic **drv;
2500
2501 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2502 /* Should happen once for each apic */
2503 WARN_ON((*drv)->eoi_write == eoi_write);
2504 (*drv)->native_eoi_write = (*drv)->eoi_write;
2505 (*drv)->eoi_write = eoi_write;
2506 }
2507 }
2508
apic_bsp_up_setup(void)2509 static void __init apic_bsp_up_setup(void)
2510 {
2511 #ifdef CONFIG_X86_64
2512 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid));
2513 #else
2514 /*
2515 * Hack: In case of kdump, after a crash, kernel might be booting
2516 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2517 * might be zero if read from MP tables. Get it from LAPIC.
2518 */
2519 # ifdef CONFIG_CRASH_DUMP
2520 boot_cpu_physical_apicid = read_apic_id();
2521 # endif
2522 #endif
2523 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2524 }
2525
2526 /**
2527 * apic_bsp_setup - Setup function for local apic and io-apic
2528 * @upmode: Force UP mode (for APIC_init_uniprocessor)
2529 */
apic_bsp_setup(bool upmode)2530 static void __init apic_bsp_setup(bool upmode)
2531 {
2532 connect_bsp_APIC();
2533 if (upmode)
2534 apic_bsp_up_setup();
2535 setup_local_APIC();
2536
2537 enable_IO_APIC();
2538 end_local_APIC_setup();
2539 irq_remap_enable_fault_handling();
2540 setup_IO_APIC();
2541 lapic_update_legacy_vectors();
2542 }
2543
2544 #ifdef CONFIG_UP_LATE_INIT
up_late_init(void)2545 void __init up_late_init(void)
2546 {
2547 if (apic_intr_mode == APIC_PIC)
2548 return;
2549
2550 /* Setup local timer */
2551 x86_init.timers.setup_percpu_clockev();
2552 }
2553 #endif
2554
2555 /*
2556 * Power management
2557 */
2558 #ifdef CONFIG_PM
2559
2560 static struct {
2561 /*
2562 * 'active' is true if the local APIC was enabled by us and
2563 * not the BIOS; this signifies that we are also responsible
2564 * for disabling it before entering apm/acpi suspend
2565 */
2566 int active;
2567 /* r/w apic fields */
2568 unsigned int apic_id;
2569 unsigned int apic_taskpri;
2570 unsigned int apic_ldr;
2571 unsigned int apic_dfr;
2572 unsigned int apic_spiv;
2573 unsigned int apic_lvtt;
2574 unsigned int apic_lvtpc;
2575 unsigned int apic_lvt0;
2576 unsigned int apic_lvt1;
2577 unsigned int apic_lvterr;
2578 unsigned int apic_tmict;
2579 unsigned int apic_tdcr;
2580 unsigned int apic_thmr;
2581 unsigned int apic_cmci;
2582 } apic_pm_state;
2583
lapic_suspend(void)2584 static int lapic_suspend(void)
2585 {
2586 unsigned long flags;
2587 int maxlvt;
2588
2589 if (!apic_pm_state.active)
2590 return 0;
2591
2592 maxlvt = lapic_get_maxlvt();
2593
2594 apic_pm_state.apic_id = apic_read(APIC_ID);
2595 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2596 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2597 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2598 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2599 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2600 if (maxlvt >= 4)
2601 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2602 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2603 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2604 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2605 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2606 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2607 #ifdef CONFIG_X86_THERMAL_VECTOR
2608 if (maxlvt >= 5)
2609 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2610 #endif
2611 #ifdef CONFIG_X86_MCE_INTEL
2612 if (maxlvt >= 6)
2613 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2614 #endif
2615
2616 local_irq_save(flags);
2617
2618 /*
2619 * Mask IOAPIC before disabling the local APIC to prevent stale IRR
2620 * entries on some implementations.
2621 */
2622 mask_ioapic_entries();
2623
2624 disable_local_APIC();
2625
2626 irq_remapping_disable();
2627
2628 local_irq_restore(flags);
2629 return 0;
2630 }
2631
lapic_resume(void)2632 static void lapic_resume(void)
2633 {
2634 unsigned int l, h;
2635 unsigned long flags;
2636 int maxlvt;
2637
2638 if (!apic_pm_state.active)
2639 return;
2640
2641 local_irq_save(flags);
2642
2643 /*
2644 * IO-APIC and PIC have their own resume routines.
2645 * We just mask them here to make sure the interrupt
2646 * subsystem is completely quiet while we enable x2apic
2647 * and interrupt-remapping.
2648 */
2649 mask_ioapic_entries();
2650 legacy_pic->mask_all();
2651
2652 if (x2apic_mode) {
2653 __x2apic_enable();
2654 } else {
2655 /*
2656 * Make sure the APICBASE points to the right address
2657 *
2658 * FIXME! This will be wrong if we ever support suspend on
2659 * SMP! We'll need to do this as part of the CPU restore!
2660 */
2661 if (boot_cpu_data.x86 >= 6) {
2662 rdmsr(MSR_IA32_APICBASE, l, h);
2663 l &= ~MSR_IA32_APICBASE_BASE;
2664 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2665 wrmsr(MSR_IA32_APICBASE, l, h);
2666 }
2667 }
2668
2669 maxlvt = lapic_get_maxlvt();
2670 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2671 apic_write(APIC_ID, apic_pm_state.apic_id);
2672 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2673 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2674 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2675 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2676 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2677 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2678 #ifdef CONFIG_X86_THERMAL_VECTOR
2679 if (maxlvt >= 5)
2680 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2681 #endif
2682 #ifdef CONFIG_X86_MCE_INTEL
2683 if (maxlvt >= 6)
2684 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2685 #endif
2686 if (maxlvt >= 4)
2687 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2688 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2689 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2690 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2691 apic_write(APIC_ESR, 0);
2692 apic_read(APIC_ESR);
2693 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2694 apic_write(APIC_ESR, 0);
2695 apic_read(APIC_ESR);
2696
2697 irq_remapping_reenable(x2apic_mode);
2698
2699 local_irq_restore(flags);
2700 }
2701
2702 /*
2703 * This device has no shutdown method - fully functioning local APICs
2704 * are needed on every CPU up until machine_halt/restart/poweroff.
2705 */
2706
2707 static struct syscore_ops lapic_syscore_ops = {
2708 .resume = lapic_resume,
2709 .suspend = lapic_suspend,
2710 };
2711
apic_pm_activate(void)2712 static void apic_pm_activate(void)
2713 {
2714 apic_pm_state.active = 1;
2715 }
2716
init_lapic_sysfs(void)2717 static int __init init_lapic_sysfs(void)
2718 {
2719 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2720 if (boot_cpu_has(X86_FEATURE_APIC))
2721 register_syscore_ops(&lapic_syscore_ops);
2722
2723 return 0;
2724 }
2725
2726 /* local apic needs to resume before other devices access its registers. */
2727 core_initcall(init_lapic_sysfs);
2728
2729 #else /* CONFIG_PM */
2730
apic_pm_activate(void)2731 static void apic_pm_activate(void) { }
2732
2733 #endif /* CONFIG_PM */
2734
2735 #ifdef CONFIG_X86_64
2736
2737 static int multi_checked;
2738 static int multi;
2739
set_multi(const struct dmi_system_id * d)2740 static int set_multi(const struct dmi_system_id *d)
2741 {
2742 if (multi)
2743 return 0;
2744 pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2745 multi = 1;
2746 return 0;
2747 }
2748
2749 static const struct dmi_system_id multi_dmi_table[] = {
2750 {
2751 .callback = set_multi,
2752 .ident = "IBM System Summit2",
2753 .matches = {
2754 DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2755 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2756 },
2757 },
2758 {}
2759 };
2760
dmi_check_multi(void)2761 static void dmi_check_multi(void)
2762 {
2763 if (multi_checked)
2764 return;
2765
2766 dmi_check_system(multi_dmi_table);
2767 multi_checked = 1;
2768 }
2769
2770 /*
2771 * apic_is_clustered_box() -- Check if we can expect good TSC
2772 *
2773 * Thus far, the major user of this is IBM's Summit2 series:
2774 * Clustered boxes may have unsynced TSC problems if they are
2775 * multi-chassis.
2776 * Use DMI to check them
2777 */
apic_is_clustered_box(void)2778 int apic_is_clustered_box(void)
2779 {
2780 dmi_check_multi();
2781 return multi;
2782 }
2783 #endif
2784
2785 /*
2786 * APIC command line parameters
2787 */
setup_disableapic(char * arg)2788 static int __init setup_disableapic(char *arg)
2789 {
2790 disable_apic = 1;
2791 setup_clear_cpu_cap(X86_FEATURE_APIC);
2792 return 0;
2793 }
2794 early_param("disableapic", setup_disableapic);
2795
2796 /* same as disableapic, for compatibility */
setup_nolapic(char * arg)2797 static int __init setup_nolapic(char *arg)
2798 {
2799 return setup_disableapic(arg);
2800 }
2801 early_param("nolapic", setup_nolapic);
2802
parse_lapic_timer_c2_ok(char * arg)2803 static int __init parse_lapic_timer_c2_ok(char *arg)
2804 {
2805 local_apic_timer_c2_ok = 1;
2806 return 0;
2807 }
2808 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2809
parse_disable_apic_timer(char * arg)2810 static int __init parse_disable_apic_timer(char *arg)
2811 {
2812 disable_apic_timer = 1;
2813 return 0;
2814 }
2815 early_param("noapictimer", parse_disable_apic_timer);
2816
parse_nolapic_timer(char * arg)2817 static int __init parse_nolapic_timer(char *arg)
2818 {
2819 disable_apic_timer = 1;
2820 return 0;
2821 }
2822 early_param("nolapic_timer", parse_nolapic_timer);
2823
apic_set_verbosity(char * arg)2824 static int __init apic_set_verbosity(char *arg)
2825 {
2826 if (!arg) {
2827 #ifdef CONFIG_X86_64
2828 skip_ioapic_setup = 0;
2829 return 0;
2830 #endif
2831 return -EINVAL;
2832 }
2833
2834 if (strcmp("debug", arg) == 0)
2835 apic_verbosity = APIC_DEBUG;
2836 else if (strcmp("verbose", arg) == 0)
2837 apic_verbosity = APIC_VERBOSE;
2838 #ifdef CONFIG_X86_64
2839 else {
2840 pr_warn("APIC Verbosity level %s not recognised"
2841 " use apic=verbose or apic=debug\n", arg);
2842 return -EINVAL;
2843 }
2844 #endif
2845
2846 return 0;
2847 }
2848 early_param("apic", apic_set_verbosity);
2849
lapic_insert_resource(void)2850 static int __init lapic_insert_resource(void)
2851 {
2852 if (!apic_phys)
2853 return -1;
2854
2855 /* Put local APIC into the resource map. */
2856 lapic_resource.start = apic_phys;
2857 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2858 insert_resource(&iomem_resource, &lapic_resource);
2859
2860 return 0;
2861 }
2862
2863 /*
2864 * need call insert after e820__reserve_resources()
2865 * that is using request_resource
2866 */
2867 late_initcall(lapic_insert_resource);
2868
apic_set_disabled_cpu_apicid(char * arg)2869 static int __init apic_set_disabled_cpu_apicid(char *arg)
2870 {
2871 if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2872 return -EINVAL;
2873
2874 return 0;
2875 }
2876 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2877
apic_set_extnmi(char * arg)2878 static int __init apic_set_extnmi(char *arg)
2879 {
2880 if (!arg)
2881 return -EINVAL;
2882
2883 if (!strncmp("all", arg, 3))
2884 apic_extnmi = APIC_EXTNMI_ALL;
2885 else if (!strncmp("none", arg, 4))
2886 apic_extnmi = APIC_EXTNMI_NONE;
2887 else if (!strncmp("bsp", arg, 3))
2888 apic_extnmi = APIC_EXTNMI_BSP;
2889 else {
2890 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2891 return -EINVAL;
2892 }
2893
2894 return 0;
2895 }
2896 early_param("apic_extnmi", apic_set_extnmi);
2897