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1#include <dt-bindings/interrupt-controller/mips-gic.h>
2#include <dt-bindings/gpio/gpio.h>
3
4/ {
5	#address-cells = <1>;
6	#size-cells = <1>;
7	compatible = "mediatek,mt7621-soc";
8
9	cpus {
10		cpu@0 {
11			compatible = "mips,mips1004Kc";
12		};
13
14		cpu@1 {
15			compatible = "mips,mips1004Kc";
16		};
17	};
18
19	cpuintc: cpuintc@0 {
20		#address-cells = <0>;
21		#interrupt-cells = <1>;
22		interrupt-controller;
23		compatible = "mti,cpu-interrupt-controller";
24	};
25
26	aliases {
27		serial0 = &uartlite;
28	};
29
30	cpuclock: cpuclock@0 {
31		#clock-cells = <0>;
32		compatible = "fixed-clock";
33
34		/* FIXME: there should be way to detect this */
35		clock-frequency = <880000000>;
36	};
37
38	sysclock: sysclock@0 {
39		#clock-cells = <0>;
40		compatible = "fixed-clock";
41
42		/* This is normally 1/4 of cpuclock */
43		clock-frequency = <220000000>;
44	};
45
46	mmc_clock: mmc_clock@0 {
47		#clock-cells = <0>;
48		compatible = "fixed-clock";
49		clock-frequency = <48000000>;
50	};
51
52	mmc_fixed_3v3: fixedregulator@0 {
53		compatible = "regulator-fixed";
54		regulator-name = "mmc_power";
55		regulator-min-microvolt = <3300000>;
56		regulator-max-microvolt = <3300000>;
57		enable-active-high;
58		regulator-always-on;
59	};
60
61	mmc_fixed_1v8_io: fixedregulator@1 {
62		compatible = "regulator-fixed";
63		regulator-name = "mmc_io";
64		regulator-min-microvolt = <1800000>;
65		regulator-max-microvolt = <1800000>;
66		enable-active-high;
67		regulator-always-on;
68	};
69
70	palmbus: palmbus@1E000000 {
71		compatible = "palmbus";
72		reg = <0x1E000000 0x100000>;
73		ranges = <0x0 0x1E000000 0x0FFFFF>;
74
75		#address-cells = <1>;
76		#size-cells = <1>;
77
78		sysc: sysc@0 {
79			compatible = "mtk,mt7621-sysc";
80			reg = <0x0 0x100>;
81		};
82
83		wdt: wdt@100 {
84			compatible = "mtk,mt7621-wdt";
85			reg = <0x100 0x100>;
86		};
87
88		gpio: gpio@600 {
89			#gpio-cells = <2>;
90			#interrupt-cells = <2>;
91			compatible = "mediatek,mt7621-gpio";
92			gpio-controller;
93			interrupt-controller;
94			reg = <0x600 0x100>;
95			interrupt-parent = <&gic>;
96			interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
97		};
98
99		i2c: i2c@900 {
100			compatible = "mediatek,mt7621-i2c";
101			reg = <0x900 0x100>;
102
103			clocks = <&sysclock>;
104
105			resets = <&rstctrl 16>;
106			reset-names = "i2c";
107
108			#address-cells = <1>;
109			#size-cells = <0>;
110
111			status = "disabled";
112
113			pinctrl-names = "default";
114			pinctrl-0 = <&i2c_pins>;
115		};
116
117		i2s: i2s@a00 {
118			compatible = "mediatek,mt7621-i2s";
119			reg = <0xa00 0x100>;
120
121			clocks = <&sysclock>;
122
123			resets = <&rstctrl 17>;
124			reset-names = "i2s";
125
126			interrupt-parent = <&gic>;
127			interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
128
129			txdma-req = <2>;
130			rxdma-req = <3>;
131
132			dmas = <&gdma 4>,
133				<&gdma 6>;
134			dma-names = "tx", "rx";
135
136			status = "disabled";
137		};
138
139		memc: memc@5000 {
140			compatible = "mtk,mt7621-memc";
141			reg = <0x5000 0x1000>;
142		};
143
144		cpc: cpc@1fbf0000 {
145			     compatible = "mtk,mt7621-cpc";
146			     reg = <0x1fbf0000 0x8000>;
147		};
148
149		mc: mc@1fbf8000 {
150			    compatible = "mtk,mt7621-mc";
151			    reg = <0x1fbf8000 0x8000>;
152		};
153
154		uartlite: uartlite@c00 {
155			compatible = "ns16550a";
156			reg = <0xc00 0x100>;
157
158			clocks = <&sysclock>;
159			clock-frequency = <50000000>;
160
161			interrupt-parent = <&gic>;
162			interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
163
164			reg-shift = <2>;
165			reg-io-width = <4>;
166			no-loopback-test;
167		};
168
169		spi0: spi@b00 {
170			status = "disabled";
171
172			compatible = "ralink,mt7621-spi";
173			reg = <0xb00 0x100>;
174
175			clocks = <&sysclock>;
176
177			resets = <&rstctrl 18>;
178			reset-names = "spi";
179
180			#address-cells = <1>;
181			#size-cells = <0>;
182
183			pinctrl-names = "default";
184			pinctrl-0 = <&spi_pins>;
185		};
186
187		gdma: gdma@2800 {
188			compatible = "ralink,rt3883-gdma";
189			reg = <0x2800 0x800>;
190
191			resets = <&rstctrl 14>;
192			reset-names = "dma";
193
194			interrupt-parent = <&gic>;
195			interrupts = <0 13 4>;
196
197			#dma-cells = <1>;
198			#dma-channels = <16>;
199			#dma-requests = <16>;
200
201			status = "disabled";
202		};
203
204		hsdma: hsdma@7000 {
205			compatible = "mediatek,mt7621-hsdma";
206			reg = <0x7000 0x1000>;
207
208			resets = <&rstctrl 5>;
209			reset-names = "hsdma";
210
211			interrupt-parent = <&gic>;
212			interrupts = <0 11 4>;
213
214			#dma-cells = <1>;
215			#dma-channels = <1>;
216			#dma-requests = <1>;
217
218			status = "disabled";
219		};
220	};
221
222	pinctrl: pinctrl {
223		compatible = "ralink,rt2880-pinmux";
224		pinctrl-names = "default";
225		pinctrl-0 = <&state_default>;
226
227		state_default: pinctrl0 {
228		};
229
230		i2c_pins: i2c0 {
231			i2c0 {
232				groups = "i2c";
233				function = "i2c";
234			};
235		};
236
237		spi_pins: spi0 {
238			spi0 {
239				groups = "spi";
240				function = "spi";
241			};
242		};
243
244		uart1_pins: uart1 {
245			uart1 {
246				groups = "uart1";
247				function = "uart1";
248			};
249		};
250
251		uart2_pins: uart2 {
252			uart2 {
253				groups = "uart2";
254				function = "uart2";
255			};
256		};
257
258		uart3_pins: uart3 {
259			uart3 {
260				groups = "uart3";
261				function = "uart3";
262			};
263		};
264
265		rgmii1_pins: rgmii1 {
266			rgmii1 {
267				groups = "rgmii1";
268				function = "rgmii1";
269			};
270		};
271
272		rgmii2_pins: rgmii2 {
273			rgmii2 {
274				groups = "rgmii2";
275				function = "rgmii2";
276			};
277		};
278
279		mdio_pins: mdio0 {
280			mdio0 {
281				groups = "mdio";
282				function = "mdio";
283			};
284		};
285
286		pcie_pins: pcie0 {
287			pcie0 {
288				groups = "pcie";
289				function = "gpio";
290			};
291		};
292
293		nand_pins: nand0 {
294			spi-nand {
295				groups = "spi";
296				function = "nand1";
297			};
298
299			sdhci-nand {
300				groups = "sdhci";
301				function = "nand2";
302			};
303		};
304
305		sdhci_pins: sdhci0 {
306			sdhci0 {
307				groups = "sdhci";
308				function = "sdhci";
309			};
310		};
311	};
312
313	rstctrl: rstctrl {
314		compatible = "ralink,rt2880-reset";
315		#reset-cells = <1>;
316	};
317
318	clkctrl: clkctrl {
319		compatible = "ralink,rt2880-clock";
320		#clock-cells = <1>;
321	};
322
323	sdhci: sdhci@1E130000 {
324		status = "disabled";
325
326		compatible = "mediatek,mt7620-mmc";
327		reg = <0x1E130000 0x4000>;
328
329		bus-width = <4>;
330		max-frequency = <48000000>;
331		cap-sd-highspeed;
332		cap-mmc-highspeed;
333		vmmc-supply = <&mmc_fixed_3v3>;
334		vqmmc-supply = <&mmc_fixed_1v8_io>;
335		disable-wp;
336
337		pinctrl-names = "default", "state_uhs";
338		pinctrl-0 = <&sdhci_pins>;
339		pinctrl-1 = <&sdhci_pins>;
340
341		clocks = <&mmc_clock &mmc_clock>;
342		clock-names = "source", "hclk";
343
344		interrupt-parent = <&gic>;
345		interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
346	};
347
348	xhci: xhci@1E1C0000 {
349		status = "okay";
350
351		compatible = "mediatek,mt8173-xhci";
352		reg = <0x1e1c0000 0x1000
353		       0x1e1d0700 0x0100>;
354		reg-names = "mac", "ippc";
355
356		clocks = <&sysclock>;
357		clock-names = "sys_ck";
358
359		interrupt-parent = <&gic>;
360		interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
361	};
362
363	gic: interrupt-controller@1fbc0000 {
364		compatible = "mti,gic";
365		reg = <0x1fbc0000 0x2000>;
366
367		interrupt-controller;
368		#interrupt-cells = <3>;
369
370		mti,reserved-cpu-vectors = <7>;
371
372		timer {
373			compatible = "mti,gic-timer";
374			interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
375			clocks = <&cpuclock>;
376		};
377	};
378
379	nand: nand@1e003000 {
380		status = "disabled";
381
382		compatible = "mtk,mt7621-nand";
383		bank-width = <2>;
384		reg = <0x1e003000 0x800
385			0x1e003800 0x800>;
386		#address-cells = <1>;
387		#size-cells = <1>;
388	};
389
390	ethsys: syscon@1e000000 {
391		compatible = "mediatek,mt7621-ethsys",
392			     "syscon";
393		reg = <0x1e000000 0x1000>;
394		#clock-cells = <1>;
395	};
396
397	ethernet: ethernet@1e100000 {
398		compatible = "mediatek,mt7621-eth";
399		reg = <0x1e100000 0x10000>;
400
401		clocks = <&sysclock>;
402		clock-names = "ethif";
403
404		#address-cells = <1>;
405		#size-cells = <0>;
406
407		resets = <&rstctrl 6 &rstctrl 23>;
408		reset-names = "fe", "eth";
409
410		interrupt-parent = <&gic>;
411		interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
412
413		mediatek,ethsys = <&ethsys>;
414
415		pinctrl-names = "default";
416		pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>;
417
418		gmac0: mac@0 {
419			compatible = "mediatek,eth-mac";
420			reg = <0>;
421			phy-mode = "rgmii";
422
423			fixed-link {
424				speed = <1000>;
425				full-duplex;
426				pause;
427			};
428		};
429
430		gmac1: mac@1 {
431			compatible = "mediatek,eth-mac";
432			reg = <1>;
433			status = "off";
434			phy-mode = "rgmii-rxid";
435		};
436
437		mdio-bus {
438			#address-cells = <1>;
439			#size-cells = <0>;
440
441			switch0: switch0@0 {
442				compatible = "mediatek,mt7621";
443				#address-cells = <1>;
444				#size-cells = <0>;
445				reg = <0>;
446				mediatek,mcm;
447				resets = <&rstctrl 2>;
448				reset-names = "mcm";
449
450				ports {
451					#address-cells = <1>;
452					#size-cells = <0>;
453					reg = <0>;
454
455					port@0 {
456						status = "off";
457						reg = <0>;
458						label = "lan0";
459					};
460
461					port@1 {
462						status = "off";
463						reg = <1>;
464						label = "lan1";
465					};
466
467					port@2 {
468						status = "off";
469						reg = <2>;
470						label = "lan2";
471					};
472
473					port@3 {
474						status = "off";
475						reg = <3>;
476						label = "lan3";
477					};
478
479					port@4 {
480						status = "off";
481						reg = <4>;
482						label = "lan4";
483					};
484
485					port@6 {
486						reg = <6>;
487						label = "cpu";
488						ethernet = <&gmac0>;
489						phy-mode = "trgmii";
490
491						fixed-link {
492							speed = <1000>;
493							full-duplex;
494						};
495					};
496				};
497			};
498		};
499	};
500
501	gsw: gsw@1e110000 {
502		compatible = "mediatek,mt7621-gsw";
503		reg = <0x1e110000 0x8000>;
504		interrupt-parent = <&gic>;
505		interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
506	};
507
508	pcie: pcie@1e140000 {
509		compatible = "mediatek,mt7621-pci";
510		reg = <0x1e140000 0x100     /* host-pci bridge registers */
511			0x1e142000 0x100    /* pcie port 0 RC control registers */
512			0x1e143000 0x100    /* pcie port 1 RC control registers */
513			0x1e144000 0x100>;  /* pcie port 2 RC control registers */
514		#address-cells = <3>;
515		#size-cells = <2>;
516
517		pinctrl-names = "default";
518		pinctrl-0 = <&pcie_pins>;
519
520		device_type = "pci";
521
522		bus-range = <0 255>;
523		ranges = <
524			0x02000000 0 0x60000000 0x60000000 0 0x10000000 /* pci memory */
525			0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
526		>;
527
528		interrupt-parent = <&gic>;
529		interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
530				GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
531				GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
532
533		status = "disabled";
534
535		resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
536		reset-names = "pcie0", "pcie1", "pcie2";
537		clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
538		clock-names = "pcie0", "pcie1", "pcie2";
539		phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
540		phy-names = "pcie-phy0", "pcie-phy2";
541
542		reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
543
544		pcie@0,0 {
545			reg = <0x0000 0 0 0 0>;
546			#address-cells = <3>;
547			#size-cells = <2>;
548			ranges;
549			bus-range = <0x00 0xff>;
550		};
551
552		pcie@1,0 {
553			reg = <0x0800 0 0 0 0>;
554			#address-cells = <3>;
555			#size-cells = <2>;
556			ranges;
557			bus-range = <0x00 0xff>;
558		};
559
560		pcie@2,0 {
561			reg = <0x1000 0 0 0 0>;
562			#address-cells = <3>;
563			#size-cells = <2>;
564			ranges;
565			bus-range = <0x00 0xff>;
566		};
567	};
568
569	pcie0_phy: pcie-phy@1e149000 {
570		compatible = "mediatek,mt7621-pci-phy";
571		reg = <0x1e149000 0x0700>;
572		#phy-cells = <1>;
573	};
574
575	pcie2_phy: pcie-phy@1e14a000 {
576		compatible = "mediatek,mt7621-pci-phy";
577		reg = <0x1e14a000 0x0700>;
578		#phy-cells = <1>;
579	};
580};
581