1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014-2019 Intel Corporation 4 */ 5 6 #ifndef _INTEL_GUC_FWIF_H 7 #define _INTEL_GUC_FWIF_H 8 9 #include <linux/bits.h> 10 #include <linux/compiler.h> 11 #include <linux/types.h> 12 13 #define GUC_CLIENT_PRIORITY_KMD_HIGH 0 14 #define GUC_CLIENT_PRIORITY_HIGH 1 15 #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2 16 #define GUC_CLIENT_PRIORITY_NORMAL 3 17 #define GUC_CLIENT_PRIORITY_NUM 4 18 19 #define GUC_MAX_STAGE_DESCRIPTORS 1024 20 #define GUC_INVALID_STAGE_ID GUC_MAX_STAGE_DESCRIPTORS 21 22 #define GUC_RENDER_ENGINE 0 23 #define GUC_VIDEO_ENGINE 1 24 #define GUC_BLITTER_ENGINE 2 25 #define GUC_VIDEOENHANCE_ENGINE 3 26 #define GUC_VIDEO_ENGINE2 4 27 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1) 28 29 #define GUC_MAX_ENGINE_CLASSES 5 30 #define GUC_MAX_INSTANCES_PER_CLASS 16 31 32 #define GUC_DOORBELL_INVALID 256 33 34 #define GUC_WQ_SIZE (PAGE_SIZE * 2) 35 36 /* Work queue item header definitions */ 37 #define WQ_STATUS_ACTIVE 1 38 #define WQ_STATUS_SUSPENDED 2 39 #define WQ_STATUS_CMD_ERROR 3 40 #define WQ_STATUS_ENGINE_ID_NOT_USED 4 41 #define WQ_STATUS_SUSPENDED_FROM_RESET 5 42 #define WQ_TYPE_SHIFT 0 43 #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT) 44 #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT) 45 #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT) 46 #define WQ_TYPE_NOOP (0x4 << WQ_TYPE_SHIFT) 47 #define WQ_TARGET_SHIFT 10 48 #define WQ_LEN_SHIFT 16 49 #define WQ_NO_WCFLUSH_WAIT (1 << 27) 50 #define WQ_PRESENT_WORKLOAD (1 << 28) 51 52 #define WQ_RING_TAIL_SHIFT 20 53 #define WQ_RING_TAIL_MAX 0x7FF /* 2^11 QWords */ 54 #define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT) 55 56 #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0) 57 #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1) 58 #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2) 59 #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3) 60 #define GUC_STAGE_DESC_ATTR_RESET BIT(4) 61 #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5) 62 #define GUC_STAGE_DESC_ATTR_PCH BIT(6) 63 #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7) 64 65 /* New GuC control data */ 66 #define GUC_CTL_CTXINFO 0 67 #define GUC_CTL_CTXNUM_IN16_SHIFT 0 68 #define GUC_CTL_BASE_ADDR_SHIFT 12 69 70 #define GUC_CTL_LOG_PARAMS 1 71 #define GUC_LOG_VALID (1 << 0) 72 #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) 73 #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) 74 #define GUC_LOG_CRASH_SHIFT 4 75 #define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT) 76 #define GUC_LOG_DPC_SHIFT 6 77 #define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT) 78 #define GUC_LOG_ISR_SHIFT 9 79 #define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT) 80 #define GUC_LOG_BUF_ADDR_SHIFT 12 81 82 #define GUC_CTL_WA 2 83 #define GUC_CTL_FEATURE 3 84 #define GUC_CTL_DISABLE_SCHEDULER (1 << 14) 85 86 #define GUC_CTL_DEBUG 4 87 #define GUC_LOG_VERBOSITY_SHIFT 0 88 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) 89 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) 90 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) 91 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) 92 /* Verbosity range-check limits, without the shift */ 93 #define GUC_LOG_VERBOSITY_MIN 0 94 #define GUC_LOG_VERBOSITY_MAX 3 95 #define GUC_LOG_VERBOSITY_MASK 0x0000000f 96 #define GUC_LOG_DESTINATION_MASK (3 << 4) 97 #define GUC_LOG_DISABLED (1 << 6) 98 #define GUC_PROFILE_ENABLED (1 << 7) 99 100 #define GUC_CTL_ADS 5 101 #define GUC_ADS_ADDR_SHIFT 1 102 #define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT) 103 104 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ 105 106 /* Work item for submitting workloads into work queue of GuC. */ 107 struct guc_wq_item { 108 u32 header; 109 u32 context_desc; 110 u32 submit_element_info; 111 u32 fence_id; 112 } __packed; 113 114 struct guc_process_desc { 115 u32 stage_id; 116 u64 db_base_addr; 117 u32 head; 118 u32 tail; 119 u32 error_offset; 120 u64 wq_base_addr; 121 u32 wq_size_bytes; 122 u32 wq_status; 123 u32 engine_presence; 124 u32 priority; 125 u32 reserved[30]; 126 } __packed; 127 128 /* engine id and context id is packed into guc_execlist_context.context_id*/ 129 #define GUC_ELC_CTXID_OFFSET 0 130 #define GUC_ELC_ENGINE_OFFSET 29 131 132 /* The execlist context including software and HW information */ 133 struct guc_execlist_context { 134 u32 context_desc; 135 u32 context_id; 136 u32 ring_status; 137 u32 ring_lrca; 138 u32 ring_begin; 139 u32 ring_end; 140 u32 ring_next_free_location; 141 u32 ring_current_tail_pointer_value; 142 u8 engine_state_submit_value; 143 u8 engine_state_wait_value; 144 u16 pagefault_count; 145 u16 engine_submit_queue_count; 146 } __packed; 147 148 /* 149 * This structure describes a stage set arranged for a particular communication 150 * between uKernel (GuC) and Driver (KMD). Technically, this is known as a 151 * "GuC Context descriptor" in the specs, but we use the term "stage descriptor" 152 * to avoid confusion with all the other things already named "context" in the 153 * driver. A static pool of these descriptors are stored inside a GEM object 154 * (stage_desc_pool) which is held for the entire lifetime of our interaction 155 * with the GuC, being allocated before the GuC is loaded with its firmware. 156 */ 157 struct guc_stage_desc { 158 u32 sched_common_area; 159 u32 stage_id; 160 u32 pas_id; 161 u8 engines_used; 162 u64 db_trigger_cpu; 163 u32 db_trigger_uk; 164 u64 db_trigger_phy; 165 u16 db_id; 166 167 struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM]; 168 169 u8 attribute; 170 171 u32 priority; 172 173 u32 wq_sampled_tail_offset; 174 u32 wq_total_submit_enqueues; 175 176 u32 process_desc; 177 u32 wq_addr; 178 u32 wq_size; 179 180 u32 engine_presence; 181 182 u8 engine_suspended; 183 184 u8 reserved0[3]; 185 u64 reserved1[1]; 186 187 u64 desc_private; 188 } __packed; 189 190 /** 191 * DOC: CTB based communication 192 * 193 * The CTB (command transport buffer) communication between Host and GuC 194 * is based on u32 data stream written to the shared buffer. One buffer can 195 * be used to transmit data only in one direction (one-directional channel). 196 * 197 * Current status of the each buffer is stored in the buffer descriptor. 198 * Buffer descriptor holds tail and head fields that represents active data 199 * stream. The tail field is updated by the data producer (sender), and head 200 * field is updated by the data consumer (receiver):: 201 * 202 * +------------+ 203 * | DESCRIPTOR | +=================+============+========+ 204 * +============+ | | MESSAGE(s) | | 205 * | address |--------->+=================+============+========+ 206 * +------------+ 207 * | head | ^-----head--------^ 208 * +------------+ 209 * | tail | ^---------tail-----------------^ 210 * +------------+ 211 * | size | ^---------------size--------------------^ 212 * +------------+ 213 * 214 * Each message in data stream starts with the single u32 treated as a header, 215 * followed by optional set of u32 data that makes message specific payload:: 216 * 217 * +------------+---------+---------+---------+ 218 * | MESSAGE | 219 * +------------+---------+---------+---------+ 220 * | msg[0] | [1] | ... | [n-1] | 221 * +------------+---------+---------+---------+ 222 * | MESSAGE | MESSAGE PAYLOAD | 223 * + HEADER +---------+---------+---------+ 224 * | | 0 | ... | n | 225 * +======+=====+=========+=========+=========+ 226 * | 31:16| code| | | | 227 * +------+-----+ | | | 228 * | 15:5|flags| | | | 229 * +------+-----+ | | | 230 * | 4:0| len| | | | 231 * +------+-----+---------+---------+---------+ 232 * 233 * ^-------------len-------------^ 234 * 235 * The message header consists of: 236 * 237 * - **len**, indicates length of the message payload (in u32) 238 * - **code**, indicates message code 239 * - **flags**, holds various bits to control message handling 240 */ 241 242 /* 243 * Describes single command transport buffer. 244 * Used by both guc-master and clients. 245 */ 246 struct guc_ct_buffer_desc { 247 u32 addr; /* gfx address */ 248 u64 host_private; /* host private data */ 249 u32 size; /* size in bytes */ 250 u32 head; /* offset updated by GuC*/ 251 u32 tail; /* offset updated by owner */ 252 u32 is_in_error; /* error indicator */ 253 u32 fence; /* fence updated by GuC */ 254 u32 status; /* status updated by GuC */ 255 u32 owner; /* id of the channel owner */ 256 u32 owner_sub_id; /* owner-defined field for extra tracking */ 257 u32 reserved[5]; 258 } __packed; 259 260 /* Type of command transport buffer */ 261 #define INTEL_GUC_CT_BUFFER_TYPE_SEND 0x0u 262 #define INTEL_GUC_CT_BUFFER_TYPE_RECV 0x1u 263 264 /* 265 * Definition of the command transport message header (DW0) 266 * 267 * bit[4..0] message len (in dwords) 268 * bit[7..5] reserved 269 * bit[8] response (G2H only) 270 * bit[8] write fence to desc (H2G only) 271 * bit[9] write status to H2G buff (H2G only) 272 * bit[10] send status back via G2H (H2G only) 273 * bit[15..11] reserved 274 * bit[31..16] action code 275 */ 276 #define GUC_CT_MSG_LEN_SHIFT 0 277 #define GUC_CT_MSG_LEN_MASK 0x1F 278 #define GUC_CT_MSG_IS_RESPONSE (1 << 8) 279 #define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8) 280 #define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9) 281 #define GUC_CT_MSG_SEND_STATUS (1 << 10) 282 #define GUC_CT_MSG_ACTION_SHIFT 16 283 #define GUC_CT_MSG_ACTION_MASK 0xFFFF 284 285 #define GUC_FORCEWAKE_RENDER (1 << 0) 286 #define GUC_FORCEWAKE_MEDIA (1 << 1) 287 288 #define GUC_POWER_UNSPECIFIED 0 289 #define GUC_POWER_D0 1 290 #define GUC_POWER_D1 2 291 #define GUC_POWER_D2 3 292 #define GUC_POWER_D3 4 293 294 /* Scheduling policy settings */ 295 296 /* Reset engine upon preempt failure */ 297 #define POLICY_RESET_ENGINE (1<<0) 298 /* Preempt to idle on quantum expiry */ 299 #define POLICY_PREEMPT_TO_IDLE (1<<1) 300 301 #define POLICY_MAX_NUM_WI 15 302 #define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000 303 #define POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000 304 #define POLICY_DEFAULT_PREEMPTION_TIME_US 500000 305 #define POLICY_DEFAULT_FAULT_TIME_US 250000 306 307 struct guc_policy { 308 /* Time for one workload to execute. (in micro seconds) */ 309 u32 execution_quantum; 310 /* Time to wait for a preemption request to completed before issuing a 311 * reset. (in micro seconds). */ 312 u32 preemption_time; 313 /* How much time to allow to run after the first fault is observed. 314 * Then preempt afterwards. (in micro seconds) */ 315 u32 fault_time; 316 u32 policy_flags; 317 u32 reserved[8]; 318 } __packed; 319 320 struct guc_policies { 321 struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINE_CLASSES]; 322 u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES]; 323 /* In micro seconds. How much time to allow before DPC processing is 324 * called back via interrupt (to prevent DPC queue drain starving). 325 * Typically 1000s of micro seconds (example only, not granularity). */ 326 u32 dpc_promote_time; 327 328 /* Must be set to take these new values. */ 329 u32 is_valid; 330 331 /* Max number of WIs to process per call. A large value may keep CS 332 * idle. */ 333 u32 max_num_work_items; 334 335 u32 reserved[4]; 336 } __packed; 337 338 /* GuC MMIO reg state struct */ 339 340 341 #define GUC_REGSET_MAX_REGISTERS 64 342 #define GUC_S3_SAVE_SPACE_PAGES 10 343 344 struct guc_mmio_reg { 345 u32 offset; 346 u32 value; 347 u32 flags; 348 #define GUC_REGSET_MASKED (1 << 0) 349 } __packed; 350 351 struct guc_mmio_regset { 352 struct guc_mmio_reg registers[GUC_REGSET_MAX_REGISTERS]; 353 u32 values_valid; 354 u32 number_of_registers; 355 } __packed; 356 357 /* GuC register sets */ 358 struct guc_mmio_reg_state { 359 struct guc_mmio_regset engine_reg[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; 360 u32 reserved[98]; 361 } __packed; 362 363 /* HW info */ 364 struct guc_gt_system_info { 365 u32 slice_enabled; 366 u32 rcs_enabled; 367 u32 reserved0; 368 u32 bcs_enabled; 369 u32 vdbox_enable_mask; 370 u32 vdbox_sfc_support_mask; 371 u32 vebox_enable_mask; 372 u32 reserved[9]; 373 } __packed; 374 375 /* Clients info */ 376 struct guc_ct_pool_entry { 377 struct guc_ct_buffer_desc desc; 378 u32 reserved[7]; 379 } __packed; 380 381 #define GUC_CT_POOL_SIZE 2 382 383 struct guc_clients_info { 384 u32 clients_num; 385 u32 reserved0[13]; 386 u32 ct_pool_addr; 387 u32 ct_pool_count; 388 u32 reserved[4]; 389 } __packed; 390 391 /* GuC Additional Data Struct */ 392 struct guc_ads { 393 u32 reg_state_addr; 394 u32 reg_state_buffer; 395 u32 scheduler_policies; 396 u32 gt_system_info; 397 u32 clients_info; 398 u32 control_data; 399 u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES]; 400 u32 eng_state_size[GUC_MAX_ENGINE_CLASSES]; 401 u32 reserved[16]; 402 } __packed; 403 404 /* GuC logging structures */ 405 406 enum guc_log_buffer_type { 407 GUC_ISR_LOG_BUFFER, 408 GUC_DPC_LOG_BUFFER, 409 GUC_CRASH_DUMP_LOG_BUFFER, 410 GUC_MAX_LOG_BUFFER 411 }; 412 413 /** 414 * struct guc_log_buffer_state - GuC log buffer state 415 * 416 * Below state structure is used for coordination of retrieval of GuC firmware 417 * logs. Separate state is maintained for each log buffer type. 418 * read_ptr points to the location where i915 read last in log buffer and 419 * is read only for GuC firmware. write_ptr is incremented by GuC with number 420 * of bytes written for each log entry and is read only for i915. 421 * When any type of log buffer becomes half full, GuC sends a flush interrupt. 422 * GuC firmware expects that while it is writing to 2nd half of the buffer, 423 * first half would get consumed by Host and then get a flush completed 424 * acknowledgment from Host, so that it does not end up doing any overwrite 425 * causing loss of logs. So when buffer gets half filled & i915 has requested 426 * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr 427 * to the value of write_ptr and raise the interrupt. 428 * On receiving the interrupt i915 should read the buffer, clear flush_to_file 429 * field and also update read_ptr with the value of sample_write_ptr, before 430 * sending an acknowledgment to GuC. marker & version fields are for internal 431 * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every 432 * time GuC detects the log buffer overflow. 433 */ 434 struct guc_log_buffer_state { 435 u32 marker[2]; 436 u32 read_ptr; 437 u32 write_ptr; 438 u32 size; 439 u32 sampled_write_ptr; 440 union { 441 struct { 442 u32 flush_to_file:1; 443 u32 buffer_full_cnt:4; 444 u32 reserved:27; 445 }; 446 u32 flags; 447 }; 448 u32 version; 449 } __packed; 450 451 struct guc_ctx_report { 452 u32 report_return_status; 453 u32 reserved1[64]; 454 u32 affected_count; 455 u32 reserved2[2]; 456 } __packed; 457 458 /* GuC Shared Context Data Struct */ 459 struct guc_shared_ctx_data { 460 u32 addr_of_last_preempted_data_low; 461 u32 addr_of_last_preempted_data_high; 462 u32 addr_of_last_preempted_data_high_tmp; 463 u32 padding; 464 u32 is_mapped_to_proxy; 465 u32 proxy_ctx_id; 466 u32 engine_reset_ctx_id; 467 u32 media_reset_count; 468 u32 reserved1[8]; 469 u32 uk_last_ctx_switch_reason; 470 u32 was_reset; 471 u32 lrca_gpu_addr; 472 u64 execlist_ctx; 473 u32 reserved2[66]; 474 struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM]; 475 } __packed; 476 477 /** 478 * DOC: MMIO based communication 479 * 480 * The MMIO based communication between Host and GuC uses software scratch 481 * registers, where first register holds data treated as message header, 482 * and other registers are used to hold message payload. 483 * 484 * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8, 485 * but no H2G command takes more than 8 parameters and the GuC FW 486 * itself uses an 8-element array to store the H2G message. 487 * 488 * +-----------+---------+---------+---------+ 489 * | MMIO[0] | MMIO[1] | ... | MMIO[n] | 490 * +-----------+---------+---------+---------+ 491 * | header | optional payload | 492 * +======+====+=========+=========+=========+ 493 * | 31:28|type| | | | 494 * +------+----+ | | | 495 * | 27:16|data| | | | 496 * +------+----+ | | | 497 * | 15:0|code| | | | 498 * +------+----+---------+---------+---------+ 499 * 500 * The message header consists of: 501 * 502 * - **type**, indicates message type 503 * - **code**, indicates message code, is specific for **type** 504 * - **data**, indicates message data, optional, depends on **code** 505 * 506 * The following message **types** are supported: 507 * 508 * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code 509 * must be priovided in **code** field. Optional action specific parameters 510 * can be provided in remaining payload registers or **data** field. 511 * 512 * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request, 513 * action response status will be provided in **code** field. Optional 514 * response data can be returned in remaining payload registers or **data** 515 * field. 516 */ 517 518 #define GUC_MAX_MMIO_MSG_LEN 8 519 520 #define INTEL_GUC_MSG_TYPE_SHIFT 28 521 #define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT) 522 #define INTEL_GUC_MSG_DATA_SHIFT 16 523 #define INTEL_GUC_MSG_DATA_MASK (0xFFF << INTEL_GUC_MSG_DATA_SHIFT) 524 #define INTEL_GUC_MSG_CODE_SHIFT 0 525 #define INTEL_GUC_MSG_CODE_MASK (0xFFFF << INTEL_GUC_MSG_CODE_SHIFT) 526 527 #define __INTEL_GUC_MSG_GET(T, m) \ 528 (((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT) 529 #define INTEL_GUC_MSG_TO_TYPE(m) __INTEL_GUC_MSG_GET(TYPE, m) 530 #define INTEL_GUC_MSG_TO_DATA(m) __INTEL_GUC_MSG_GET(DATA, m) 531 #define INTEL_GUC_MSG_TO_CODE(m) __INTEL_GUC_MSG_GET(CODE, m) 532 533 enum intel_guc_msg_type { 534 INTEL_GUC_MSG_TYPE_REQUEST = 0x0, 535 INTEL_GUC_MSG_TYPE_RESPONSE = 0xF, 536 }; 537 538 #define __INTEL_GUC_MSG_TYPE_IS(T, m) \ 539 (INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T) 540 #define INTEL_GUC_MSG_IS_REQUEST(m) __INTEL_GUC_MSG_TYPE_IS(REQUEST, m) 541 #define INTEL_GUC_MSG_IS_RESPONSE(m) __INTEL_GUC_MSG_TYPE_IS(RESPONSE, m) 542 543 enum intel_guc_action { 544 INTEL_GUC_ACTION_DEFAULT = 0x0, 545 INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2, 546 INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3, 547 INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10, 548 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20, 549 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30, 550 INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x40, 551 INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302, 552 INTEL_GUC_ACTION_ENTER_S_STATE = 0x501, 553 INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, 554 INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, 555 INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x3005, 556 INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, 557 INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505, 558 INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506, 559 INTEL_GUC_ACTION_LIMIT 560 }; 561 562 enum intel_guc_preempt_options { 563 INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4, 564 INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8, 565 }; 566 567 enum intel_guc_report_status { 568 INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0, 569 INTEL_GUC_REPORT_STATUS_ACKED = 0x1, 570 INTEL_GUC_REPORT_STATUS_ERROR = 0x2, 571 INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4, 572 }; 573 574 enum intel_guc_sleep_state_status { 575 INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1, 576 INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2, 577 INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3 578 #define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000 579 }; 580 581 #define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0) 582 #define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4 583 #define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT) 584 #define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8) 585 586 enum intel_guc_response_status { 587 INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0, 588 INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000, 589 }; 590 591 #define INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(m) \ 592 (typecheck(u32, (m)) && \ 593 ((m) & (INTEL_GUC_MSG_TYPE_MASK | INTEL_GUC_MSG_CODE_MASK)) == \ 594 ((INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT) | \ 595 (INTEL_GUC_RESPONSE_STATUS_SUCCESS << INTEL_GUC_MSG_CODE_SHIFT))) 596 597 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ 598 enum intel_guc_recv_message { 599 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), 600 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3) 601 }; 602 603 #endif 604