• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Based on arch/arm/include/asm/processor.h
4  *
5  * Copyright (C) 1995-1999 Russell King
6  * Copyright (C) 2012 ARM Ltd.
7  */
8 #ifndef __ASM_PROCESSOR_H
9 #define __ASM_PROCESSOR_H
10 
11 #define KERNEL_DS		UL(-1)
12 #define USER_DS			((UL(1) << VA_BITS) - 1)
13 
14 /*
15  * On arm64 systems, unaligned accesses by the CPU are cheap, and so there is
16  * no point in shifting all network buffers by 2 bytes just to make some IP
17  * header fields appear aligned in memory, potentially sacrificing some DMA
18  * performance on some platforms.
19  */
20 #define NET_IP_ALIGN	0
21 
22 #define MTE_CTRL_GCR_USER_EXCL_SHIFT	0
23 #define MTE_CTRL_GCR_USER_EXCL_MASK	0xffff
24 
25 #define MTE_CTRL_TCF_SYNC		(1UL << 16)
26 #define MTE_CTRL_TCF_ASYNC		(1UL << 17)
27 
28 #ifndef __ASSEMBLY__
29 
30 #include <linux/build_bug.h>
31 #include <linux/cache.h>
32 #include <linux/init.h>
33 #include <linux/stddef.h>
34 #include <linux/string.h>
35 #include <linux/thread_info.h>
36 #include <linux/android_vendor.h>
37 
38 #include <vdso/processor.h>
39 
40 #include <asm/alternative.h>
41 #include <asm/cpufeature.h>
42 #include <asm/hw_breakpoint.h>
43 #include <asm/kasan.h>
44 #include <asm/lse.h>
45 #include <asm/pgtable-hwdef.h>
46 #include <asm/pointer_auth.h>
47 #include <asm/ptrace.h>
48 #include <asm/spectre.h>
49 #include <asm/types.h>
50 
51 /*
52  * TASK_SIZE - the maximum size of a user space task.
53  * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
54  */
55 
56 #define DEFAULT_MAP_WINDOW_64	(UL(1) << VA_BITS_MIN)
57 #define TASK_SIZE_64		(UL(1) << vabits_actual)
58 
59 #ifdef CONFIG_COMPAT
60 #if defined(CONFIG_ARM64_64K_PAGES) && defined(CONFIG_KUSER_HELPERS)
61 /*
62  * With CONFIG_ARM64_64K_PAGES enabled, the last page is occupied
63  * by the compat vectors page.
64  */
65 #define TASK_SIZE_32		UL(0x100000000)
66 #else
67 #define TASK_SIZE_32		(UL(0x100000000) - PAGE_SIZE)
68 #endif /* CONFIG_ARM64_64K_PAGES */
69 #define TASK_SIZE		(test_thread_flag(TIF_32BIT) ? \
70 				TASK_SIZE_32 : TASK_SIZE_64)
71 #define TASK_SIZE_OF(tsk)	(test_tsk_thread_flag(tsk, TIF_32BIT) ? \
72 				TASK_SIZE_32 : TASK_SIZE_64)
73 #define DEFAULT_MAP_WINDOW	(test_thread_flag(TIF_32BIT) ? \
74 				TASK_SIZE_32 : DEFAULT_MAP_WINDOW_64)
75 #else
76 #define TASK_SIZE		TASK_SIZE_64
77 #define DEFAULT_MAP_WINDOW	DEFAULT_MAP_WINDOW_64
78 #endif /* CONFIG_COMPAT */
79 
80 #ifdef CONFIG_ARM64_FORCE_52BIT
81 #define STACK_TOP_MAX		TASK_SIZE_64
82 #define TASK_UNMAPPED_BASE	(PAGE_ALIGN(TASK_SIZE / 4))
83 #else
84 #define STACK_TOP_MAX		DEFAULT_MAP_WINDOW_64
85 #define TASK_UNMAPPED_BASE	(PAGE_ALIGN(DEFAULT_MAP_WINDOW / 4))
86 #endif /* CONFIG_ARM64_FORCE_52BIT */
87 
88 #ifdef CONFIG_COMPAT
89 #define AARCH32_VECTORS_BASE	0xffff0000
90 #define STACK_TOP		(test_thread_flag(TIF_32BIT) ? \
91 				AARCH32_VECTORS_BASE : STACK_TOP_MAX)
92 #else
93 #define STACK_TOP		STACK_TOP_MAX
94 #endif /* CONFIG_COMPAT */
95 
96 #ifndef CONFIG_ARM64_FORCE_52BIT
97 #define arch_get_mmap_end(addr) ((addr > DEFAULT_MAP_WINDOW) ? TASK_SIZE :\
98 				DEFAULT_MAP_WINDOW)
99 
100 #define arch_get_mmap_base(addr, base) ((addr > DEFAULT_MAP_WINDOW) ? \
101 					base + TASK_SIZE - DEFAULT_MAP_WINDOW :\
102 					base)
103 #endif /* CONFIG_ARM64_FORCE_52BIT */
104 
105 extern phys_addr_t arm64_dma_phys_limit;
106 #define ARCH_LOW_ADDRESS_LIMIT	(arm64_dma_phys_limit - 1)
107 
108 struct debug_info {
109 #ifdef CONFIG_HAVE_HW_BREAKPOINT
110 	/* Have we suspended stepping by a debugger? */
111 	int			suspended_step;
112 	/* Allow breakpoints and watchpoints to be disabled for this thread. */
113 	int			bps_disabled;
114 	int			wps_disabled;
115 	/* Hardware breakpoints pinned to this task. */
116 	struct perf_event	*hbp_break[ARM_MAX_BRP];
117 	struct perf_event	*hbp_watch[ARM_MAX_WRP];
118 #endif
119 };
120 
121 struct cpu_context {
122 	unsigned long x19;
123 	unsigned long x20;
124 	unsigned long x21;
125 	unsigned long x22;
126 	unsigned long x23;
127 	unsigned long x24;
128 	unsigned long x25;
129 	unsigned long x26;
130 	unsigned long x27;
131 	unsigned long x28;
132 	unsigned long fp;
133 	unsigned long sp;
134 	unsigned long pc;
135 };
136 
137 struct thread_struct {
138 	struct cpu_context	cpu_context;	/* cpu context */
139 
140 	/*
141 	 * Whitelisted fields for hardened usercopy:
142 	 * Maintainers must ensure manually that this contains no
143 	 * implicit padding.
144 	 */
145 	struct {
146 		unsigned long	tp_value;	/* TLS register */
147 		unsigned long	tp2_value;
148 		struct user_fpsimd_state fpsimd_state;
149 	} uw;
150 
151 	ANDROID_VENDOR_DATA(1);
152 
153 	unsigned int		fpsimd_cpu;
154 	void			*sve_state;	/* SVE registers, if any */
155 	unsigned int		sve_vl;		/* SVE vector length */
156 	unsigned int		sve_vl_onexec;	/* SVE vl after next exec */
157 	unsigned long		fault_address;	/* fault info */
158 	unsigned long		fault_code;	/* ESR_EL1 value */
159 	struct debug_info	debug;		/* debugging */
160 #ifdef CONFIG_ARM64_PTR_AUTH
161 	struct ptrauth_keys_user	keys_user;
162 	struct ptrauth_keys_kernel	keys_kernel;
163 #endif
164 #ifdef CONFIG_ARM64_MTE
165 	u64			mte_ctrl;
166 #endif
167 	u64			sctlr_user;
168 };
169 
170 #define SCTLR_USER_MASK                                                        \
171 	(SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | SCTLR_ELx_ENDA | SCTLR_ELx_ENDB |   \
172 	 SCTLR_EL1_TCF0_MASK)
173 
arch_thread_struct_whitelist(unsigned long * offset,unsigned long * size)174 static inline void arch_thread_struct_whitelist(unsigned long *offset,
175 						unsigned long *size)
176 {
177 	/* Verify that there is no padding among the whitelisted fields: */
178 	BUILD_BUG_ON(sizeof_field(struct thread_struct, uw) !=
179 		     sizeof_field(struct thread_struct, uw.tp_value) +
180 		     sizeof_field(struct thread_struct, uw.tp2_value) +
181 		     sizeof_field(struct thread_struct, uw.fpsimd_state));
182 
183 	*offset = offsetof(struct thread_struct, uw);
184 	*size = sizeof_field(struct thread_struct, uw);
185 }
186 
187 #ifdef CONFIG_COMPAT
188 #define task_user_tls(t)						\
189 ({									\
190 	unsigned long *__tls;						\
191 	if (is_compat_thread(task_thread_info(t)))			\
192 		__tls = &(t)->thread.uw.tp2_value;			\
193 	else								\
194 		__tls = &(t)->thread.uw.tp_value;			\
195 	__tls;								\
196  })
197 #else
198 #define task_user_tls(t)	(&(t)->thread.uw.tp_value)
199 #endif
200 
201 /* Sync TPIDR_EL0 back to thread_struct for current */
202 void tls_preserve_current_state(void);
203 
204 #define INIT_THREAD {				\
205 	.fpsimd_cpu = NR_CPUS,			\
206 }
207 
start_thread_common(struct pt_regs * regs,unsigned long pc)208 static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
209 {
210 	s32 previous_syscall = regs->syscallno;
211 	memset(regs, 0, sizeof(*regs));
212 	regs->syscallno = previous_syscall;
213 	regs->pc = pc;
214 
215 	if (system_uses_irq_prio_masking())
216 		regs->pmr_save = GIC_PRIO_IRQON;
217 }
218 
start_thread(struct pt_regs * regs,unsigned long pc,unsigned long sp)219 static inline void start_thread(struct pt_regs *regs, unsigned long pc,
220 				unsigned long sp)
221 {
222 	start_thread_common(regs, pc);
223 	regs->pstate = PSR_MODE_EL0t;
224 	spectre_v4_enable_task_mitigation(current);
225 	regs->sp = sp;
226 }
227 
228 #ifdef CONFIG_COMPAT
compat_start_thread(struct pt_regs * regs,unsigned long pc,unsigned long sp)229 static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
230 				       unsigned long sp)
231 {
232 	start_thread_common(regs, pc);
233 	regs->pstate = PSR_AA32_MODE_USR;
234 	if (pc & 1)
235 		regs->pstate |= PSR_AA32_T_BIT;
236 
237 #ifdef __AARCH64EB__
238 	regs->pstate |= PSR_AA32_E_BIT;
239 #endif
240 
241 	spectre_v4_enable_task_mitigation(current);
242 	regs->compat_sp = sp;
243 }
244 #endif
245 
is_ttbr0_addr(unsigned long addr)246 static __always_inline bool is_ttbr0_addr(unsigned long addr)
247 {
248 	/* entry assembly clears tags for TTBR0 addrs */
249 	return addr < TASK_SIZE;
250 }
251 
is_ttbr1_addr(unsigned long addr)252 static __always_inline bool is_ttbr1_addr(unsigned long addr)
253 {
254 	/* TTBR1 addresses may have a tag if KASAN_SW_TAGS is in use */
255 	return arch_kasan_reset_tag(addr) >= PAGE_OFFSET;
256 }
257 
258 /* Forward declaration, a strange C thing */
259 struct task_struct;
260 
261 /* Free all resources held by a thread. */
262 extern void release_thread(struct task_struct *);
263 
264 unsigned long get_wchan(struct task_struct *p);
265 
266 void update_sctlr_el1(u64 sctlr);
267 
268 /* Thread switching */
269 extern struct task_struct *cpu_switch_to(struct task_struct *prev,
270 					 struct task_struct *next);
271 
272 #define task_pt_regs(p) \
273 	((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
274 
275 #define KSTK_EIP(tsk)	((unsigned long)task_pt_regs(tsk)->pc)
276 #define KSTK_ESP(tsk)	user_stack_pointer(task_pt_regs(tsk))
277 
278 /*
279  * Prefetching support
280  */
281 #define ARCH_HAS_PREFETCH
prefetch(const void * ptr)282 static inline void prefetch(const void *ptr)
283 {
284 	asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
285 }
286 
287 #define ARCH_HAS_PREFETCHW
prefetchw(const void * ptr)288 static inline void prefetchw(const void *ptr)
289 {
290 	asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
291 }
292 
293 #define ARCH_HAS_SPINLOCK_PREFETCH
spin_lock_prefetch(const void * ptr)294 static inline void spin_lock_prefetch(const void *ptr)
295 {
296 	asm volatile(ARM64_LSE_ATOMIC_INSN(
297 		     "prfm pstl1strm, %a0",
298 		     "nop") : : "p" (ptr));
299 }
300 
301 extern unsigned long __ro_after_init signal_minsigstksz; /* sigframe size */
302 extern void __init minsigstksz_setup(void);
303 
304 /*
305  * Not at the top of the file due to a direct #include cycle between
306  * <asm/fpsimd.h> and <asm/processor.h>.  Deferring this #include
307  * ensures that contents of processor.h are visible to fpsimd.h even if
308  * processor.h is included first.
309  *
310  * These prctl helpers are the only things in this file that require
311  * fpsimd.h.  The core code expects them to be in this header.
312  */
313 #include <asm/fpsimd.h>
314 
315 /* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */
316 #define SVE_SET_VL(arg)	sve_set_current_vl(arg)
317 #define SVE_GET_VL()	sve_get_current_vl()
318 
319 /* PR_PAC_RESET_KEYS prctl */
320 #define PAC_RESET_KEYS(tsk, arg)	ptrauth_prctl_reset_keys(tsk, arg)
321 
322 /* PR_PAC_{SET,GET}_ENABLED_KEYS prctl */
323 #define PAC_SET_ENABLED_KEYS(tsk, keys, enabled)				\
324 	ptrauth_set_enabled_keys(tsk, keys, enabled)
325 #define PAC_GET_ENABLED_KEYS(tsk) ptrauth_get_enabled_keys(tsk)
326 
327 #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI
328 /* PR_{SET,GET}_TAGGED_ADDR_CTRL prctl */
329 long set_tagged_addr_ctrl(struct task_struct *task, unsigned long arg);
330 long get_tagged_addr_ctrl(struct task_struct *task);
331 #define SET_TAGGED_ADDR_CTRL(arg)	set_tagged_addr_ctrl(current, arg)
332 #define GET_TAGGED_ADDR_CTRL()		get_tagged_addr_ctrl(current)
333 #endif
334 
335 /*
336  * For CONFIG_GCC_PLUGIN_STACKLEAK
337  *
338  * These need to be macros because otherwise we get stuck in a nightmare
339  * of header definitions for the use of task_stack_page.
340  */
341 
342 #define current_top_of_stack()							\
343 ({										\
344 	struct stack_info _info;						\
345 	BUG_ON(!on_accessible_stack(current, current_stack_pointer, &_info));	\
346 	_info.high;								\
347 })
348 #define on_thread_stack()	(on_task_stack(current, current_stack_pointer, NULL))
349 
350 #endif /* __ASSEMBLY__ */
351 #endif /* __ASM_PROCESSOR_H */
352