1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 1994 Linus Torvalds
4 *
5 * Cyrix stuff, June 1998 by:
6 * - Rafael R. Reilova (moved everything from head.S),
7 * <rreilova@ececs.uc.edu>
8 * - Channing Corn (tests & fixes),
9 * - Andrew D. Balsa (code cleanup).
10 */
11 #include <linux/init.h>
12 #include <linux/cpu.h>
13 #include <linux/module.h>
14 #include <linux/nospec.h>
15 #include <linux/prctl.h>
16 #include <linux/sched/smt.h>
17 #include <linux/pgtable.h>
18 #include <linux/bpf.h>
19
20 #include <asm/spec-ctrl.h>
21 #include <asm/cmdline.h>
22 #include <asm/bugs.h>
23 #include <asm/processor.h>
24 #include <asm/processor-flags.h>
25 #include <asm/fpu/internal.h>
26 #include <asm/msr.h>
27 #include <asm/vmx.h>
28 #include <asm/paravirt.h>
29 #include <asm/intel-family.h>
30 #include <asm/e820/api.h>
31 #include <asm/hypervisor.h>
32 #include <asm/tlbflush.h>
33
34 #include "cpu.h"
35
36 static void __init spectre_v1_select_mitigation(void);
37 static void __init spectre_v2_select_mitigation(void);
38 static void __init retbleed_select_mitigation(void);
39 static void __init spectre_v2_user_select_mitigation(void);
40 static void __init ssb_select_mitigation(void);
41 static void __init l1tf_select_mitigation(void);
42 static void __init mds_select_mitigation(void);
43 static void __init md_clear_update_mitigation(void);
44 static void __init md_clear_select_mitigation(void);
45 static void __init taa_select_mitigation(void);
46 static void __init mmio_select_mitigation(void);
47 static void __init srbds_select_mitigation(void);
48 static void __init gds_select_mitigation(void);
49 static void __init srso_select_mitigation(void);
50
51 /* The base value of the SPEC_CTRL MSR without task-specific bits set */
52 u64 x86_spec_ctrl_base;
53 EXPORT_SYMBOL_GPL(x86_spec_ctrl_base);
54
55 /* The current value of the SPEC_CTRL MSR with task-specific bits set */
56 DEFINE_PER_CPU(u64, x86_spec_ctrl_current);
57 EXPORT_SYMBOL_GPL(x86_spec_ctrl_current);
58
59 u64 x86_pred_cmd __ro_after_init = PRED_CMD_IBPB;
60 EXPORT_SYMBOL_GPL(x86_pred_cmd);
61
62 static DEFINE_MUTEX(spec_ctrl_mutex);
63
64 void (*x86_return_thunk)(void) __ro_after_init = &__x86_return_thunk;
65
66 /* Update SPEC_CTRL MSR and its cached copy unconditionally */
update_spec_ctrl(u64 val)67 static void update_spec_ctrl(u64 val)
68 {
69 this_cpu_write(x86_spec_ctrl_current, val);
70 wrmsrl(MSR_IA32_SPEC_CTRL, val);
71 }
72
73 /*
74 * Keep track of the SPEC_CTRL MSR value for the current task, which may differ
75 * from x86_spec_ctrl_base due to STIBP/SSB in __speculation_ctrl_update().
76 */
update_spec_ctrl_cond(u64 val)77 void update_spec_ctrl_cond(u64 val)
78 {
79 if (this_cpu_read(x86_spec_ctrl_current) == val)
80 return;
81
82 this_cpu_write(x86_spec_ctrl_current, val);
83
84 /*
85 * When KERNEL_IBRS this MSR is written on return-to-user, unless
86 * forced the update can be delayed until that time.
87 */
88 if (!cpu_feature_enabled(X86_FEATURE_KERNEL_IBRS))
89 wrmsrl(MSR_IA32_SPEC_CTRL, val);
90 }
91
spec_ctrl_current(void)92 u64 spec_ctrl_current(void)
93 {
94 return this_cpu_read(x86_spec_ctrl_current);
95 }
96 EXPORT_SYMBOL_GPL(spec_ctrl_current);
97
98 /*
99 * AMD specific MSR info for Speculative Store Bypass control.
100 * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
101 */
102 u64 __ro_after_init x86_amd_ls_cfg_base;
103 u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask;
104
105 /* Control conditional STIBP in switch_to() */
106 DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp);
107 /* Control conditional IBPB in switch_mm() */
108 DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb);
109 /* Control unconditional IBPB in switch_mm() */
110 DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb);
111
112 /* Control MDS CPU buffer clear before returning to user space */
113 DEFINE_STATIC_KEY_FALSE(mds_user_clear);
114 EXPORT_SYMBOL_GPL(mds_user_clear);
115 /* Control MDS CPU buffer clear before idling (halt, mwait) */
116 DEFINE_STATIC_KEY_FALSE(mds_idle_clear);
117 EXPORT_SYMBOL_GPL(mds_idle_clear);
118
119 /* Controls CPU Fill buffer clear before KVM guest MMIO accesses */
120 DEFINE_STATIC_KEY_FALSE(mmio_stale_data_clear);
121 EXPORT_SYMBOL_GPL(mmio_stale_data_clear);
122
cpu_select_mitigations(void)123 void __init cpu_select_mitigations(void)
124 {
125 /*
126 * Read the SPEC_CTRL MSR to account for reserved bits which may
127 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
128 * init code as it is not enumerated and depends on the family.
129 */
130 if (cpu_feature_enabled(X86_FEATURE_MSR_SPEC_CTRL)) {
131 rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
132
133 /*
134 * Previously running kernel (kexec), may have some controls
135 * turned ON. Clear them and let the mitigations setup below
136 * rediscover them based on configuration.
137 */
138 x86_spec_ctrl_base &= ~SPEC_CTRL_MITIGATIONS_MASK;
139 }
140
141 /* Select the proper CPU mitigations before patching alternatives: */
142 spectre_v1_select_mitigation();
143 spectre_v2_select_mitigation();
144 /*
145 * retbleed_select_mitigation() relies on the state set by
146 * spectre_v2_select_mitigation(); specifically it wants to know about
147 * spectre_v2=ibrs.
148 */
149 retbleed_select_mitigation();
150 /*
151 * spectre_v2_user_select_mitigation() relies on the state set by
152 * retbleed_select_mitigation(); specifically the STIBP selection is
153 * forced for UNRET or IBPB.
154 */
155 spectre_v2_user_select_mitigation();
156 ssb_select_mitigation();
157 l1tf_select_mitigation();
158 md_clear_select_mitigation();
159 srbds_select_mitigation();
160
161 /*
162 * srso_select_mitigation() depends and must run after
163 * retbleed_select_mitigation().
164 */
165 srso_select_mitigation();
166 gds_select_mitigation();
167 }
168
169 /*
170 * NOTE: For VMX, this function is not called in the vmexit path.
171 * It uses vmx_spec_ctrl_restore_host() instead.
172 */
173 void
x86_virt_spec_ctrl(u64 guest_spec_ctrl,u64 guest_virt_spec_ctrl,bool setguest)174 x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
175 {
176 u64 msrval, guestval = guest_spec_ctrl, hostval = spec_ctrl_current();
177 struct thread_info *ti = current_thread_info();
178
179 if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
180 if (hostval != guestval) {
181 msrval = setguest ? guestval : hostval;
182 wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
183 }
184 }
185
186 /*
187 * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update
188 * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported.
189 */
190 if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) &&
191 !static_cpu_has(X86_FEATURE_VIRT_SSBD))
192 return;
193
194 /*
195 * If the host has SSBD mitigation enabled, force it in the host's
196 * virtual MSR value. If its not permanently enabled, evaluate
197 * current's TIF_SSBD thread flag.
198 */
199 if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE))
200 hostval = SPEC_CTRL_SSBD;
201 else
202 hostval = ssbd_tif_to_spec_ctrl(ti->flags);
203
204 /* Sanitize the guest value */
205 guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD;
206
207 if (hostval != guestval) {
208 unsigned long tif;
209
210 tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) :
211 ssbd_spec_ctrl_to_tif(hostval);
212
213 speculation_ctrl_update(tif);
214 }
215 }
216 EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl);
217
x86_amd_ssb_disable(void)218 static void x86_amd_ssb_disable(void)
219 {
220 u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask;
221
222 if (boot_cpu_has(X86_FEATURE_VIRT_SSBD))
223 wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD);
224 else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD))
225 wrmsrl(MSR_AMD64_LS_CFG, msrval);
226 }
227
228 #undef pr_fmt
229 #define pr_fmt(fmt) "MDS: " fmt
230
231 /* Default mitigation for MDS-affected CPUs */
232 static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL;
233 static bool mds_nosmt __ro_after_init = false;
234
235 static const char * const mds_strings[] = {
236 [MDS_MITIGATION_OFF] = "Vulnerable",
237 [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers",
238 [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode",
239 };
240
mds_select_mitigation(void)241 static void __init mds_select_mitigation(void)
242 {
243 if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) {
244 mds_mitigation = MDS_MITIGATION_OFF;
245 return;
246 }
247
248 if (mds_mitigation == MDS_MITIGATION_FULL) {
249 if (!boot_cpu_has(X86_FEATURE_MD_CLEAR))
250 mds_mitigation = MDS_MITIGATION_VMWERV;
251
252 static_branch_enable(&mds_user_clear);
253
254 if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) &&
255 (mds_nosmt || cpu_mitigations_auto_nosmt()))
256 cpu_smt_disable(false);
257 }
258 }
259
mds_cmdline(char * str)260 static int __init mds_cmdline(char *str)
261 {
262 if (!boot_cpu_has_bug(X86_BUG_MDS))
263 return 0;
264
265 if (!str)
266 return -EINVAL;
267
268 if (!strcmp(str, "off"))
269 mds_mitigation = MDS_MITIGATION_OFF;
270 else if (!strcmp(str, "full"))
271 mds_mitigation = MDS_MITIGATION_FULL;
272 else if (!strcmp(str, "full,nosmt")) {
273 mds_mitigation = MDS_MITIGATION_FULL;
274 mds_nosmt = true;
275 }
276
277 return 0;
278 }
279 early_param("mds", mds_cmdline);
280
281 #undef pr_fmt
282 #define pr_fmt(fmt) "TAA: " fmt
283
284 enum taa_mitigations {
285 TAA_MITIGATION_OFF,
286 TAA_MITIGATION_UCODE_NEEDED,
287 TAA_MITIGATION_VERW,
288 TAA_MITIGATION_TSX_DISABLED,
289 };
290
291 /* Default mitigation for TAA-affected CPUs */
292 static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW;
293 static bool taa_nosmt __ro_after_init;
294
295 static const char * const taa_strings[] = {
296 [TAA_MITIGATION_OFF] = "Vulnerable",
297 [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
298 [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
299 [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled",
300 };
301
taa_select_mitigation(void)302 static void __init taa_select_mitigation(void)
303 {
304 u64 ia32_cap;
305
306 if (!boot_cpu_has_bug(X86_BUG_TAA)) {
307 taa_mitigation = TAA_MITIGATION_OFF;
308 return;
309 }
310
311 /* TSX previously disabled by tsx=off */
312 if (!boot_cpu_has(X86_FEATURE_RTM)) {
313 taa_mitigation = TAA_MITIGATION_TSX_DISABLED;
314 return;
315 }
316
317 if (cpu_mitigations_off()) {
318 taa_mitigation = TAA_MITIGATION_OFF;
319 return;
320 }
321
322 /*
323 * TAA mitigation via VERW is turned off if both
324 * tsx_async_abort=off and mds=off are specified.
325 */
326 if (taa_mitigation == TAA_MITIGATION_OFF &&
327 mds_mitigation == MDS_MITIGATION_OFF)
328 return;
329
330 if (boot_cpu_has(X86_FEATURE_MD_CLEAR))
331 taa_mitigation = TAA_MITIGATION_VERW;
332 else
333 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
334
335 /*
336 * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1.
337 * A microcode update fixes this behavior to clear CPU buffers. It also
338 * adds support for MSR_IA32_TSX_CTRL which is enumerated by the
339 * ARCH_CAP_TSX_CTRL_MSR bit.
340 *
341 * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode
342 * update is required.
343 */
344 ia32_cap = x86_read_arch_cap_msr();
345 if ( (ia32_cap & ARCH_CAP_MDS_NO) &&
346 !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR))
347 taa_mitigation = TAA_MITIGATION_UCODE_NEEDED;
348
349 /*
350 * TSX is enabled, select alternate mitigation for TAA which is
351 * the same as MDS. Enable MDS static branch to clear CPU buffers.
352 *
353 * For guests that can't determine whether the correct microcode is
354 * present on host, enable the mitigation for UCODE_NEEDED as well.
355 */
356 static_branch_enable(&mds_user_clear);
357
358 if (taa_nosmt || cpu_mitigations_auto_nosmt())
359 cpu_smt_disable(false);
360 }
361
tsx_async_abort_parse_cmdline(char * str)362 static int __init tsx_async_abort_parse_cmdline(char *str)
363 {
364 if (!boot_cpu_has_bug(X86_BUG_TAA))
365 return 0;
366
367 if (!str)
368 return -EINVAL;
369
370 if (!strcmp(str, "off")) {
371 taa_mitigation = TAA_MITIGATION_OFF;
372 } else if (!strcmp(str, "full")) {
373 taa_mitigation = TAA_MITIGATION_VERW;
374 } else if (!strcmp(str, "full,nosmt")) {
375 taa_mitigation = TAA_MITIGATION_VERW;
376 taa_nosmt = true;
377 }
378
379 return 0;
380 }
381 early_param("tsx_async_abort", tsx_async_abort_parse_cmdline);
382
383 #undef pr_fmt
384 #define pr_fmt(fmt) "MMIO Stale Data: " fmt
385
386 enum mmio_mitigations {
387 MMIO_MITIGATION_OFF,
388 MMIO_MITIGATION_UCODE_NEEDED,
389 MMIO_MITIGATION_VERW,
390 };
391
392 /* Default mitigation for Processor MMIO Stale Data vulnerabilities */
393 static enum mmio_mitigations mmio_mitigation __ro_after_init = MMIO_MITIGATION_VERW;
394 static bool mmio_nosmt __ro_after_init = false;
395
396 static const char * const mmio_strings[] = {
397 [MMIO_MITIGATION_OFF] = "Vulnerable",
398 [MMIO_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode",
399 [MMIO_MITIGATION_VERW] = "Mitigation: Clear CPU buffers",
400 };
401
mmio_select_mitigation(void)402 static void __init mmio_select_mitigation(void)
403 {
404 u64 ia32_cap;
405
406 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA) ||
407 boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN) ||
408 cpu_mitigations_off()) {
409 mmio_mitigation = MMIO_MITIGATION_OFF;
410 return;
411 }
412
413 if (mmio_mitigation == MMIO_MITIGATION_OFF)
414 return;
415
416 ia32_cap = x86_read_arch_cap_msr();
417
418 /*
419 * Enable CPU buffer clear mitigation for host and VMM, if also affected
420 * by MDS or TAA. Otherwise, enable mitigation for VMM only.
421 */
422 if (boot_cpu_has_bug(X86_BUG_MDS) || (boot_cpu_has_bug(X86_BUG_TAA) &&
423 boot_cpu_has(X86_FEATURE_RTM)))
424 static_branch_enable(&mds_user_clear);
425 else
426 static_branch_enable(&mmio_stale_data_clear);
427
428 /*
429 * If Processor-MMIO-Stale-Data bug is present and Fill Buffer data can
430 * be propagated to uncore buffers, clearing the Fill buffers on idle
431 * is required irrespective of SMT state.
432 */
433 if (!(ia32_cap & ARCH_CAP_FBSDP_NO))
434 static_branch_enable(&mds_idle_clear);
435
436 /*
437 * Check if the system has the right microcode.
438 *
439 * CPU Fill buffer clear mitigation is enumerated by either an explicit
440 * FB_CLEAR or by the presence of both MD_CLEAR and L1D_FLUSH on MDS
441 * affected systems.
442 */
443 if ((ia32_cap & ARCH_CAP_FB_CLEAR) ||
444 (boot_cpu_has(X86_FEATURE_MD_CLEAR) &&
445 boot_cpu_has(X86_FEATURE_FLUSH_L1D) &&
446 !(ia32_cap & ARCH_CAP_MDS_NO)))
447 mmio_mitigation = MMIO_MITIGATION_VERW;
448 else
449 mmio_mitigation = MMIO_MITIGATION_UCODE_NEEDED;
450
451 if (mmio_nosmt || cpu_mitigations_auto_nosmt())
452 cpu_smt_disable(false);
453 }
454
mmio_stale_data_parse_cmdline(char * str)455 static int __init mmio_stale_data_parse_cmdline(char *str)
456 {
457 if (!boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
458 return 0;
459
460 if (!str)
461 return -EINVAL;
462
463 if (!strcmp(str, "off")) {
464 mmio_mitigation = MMIO_MITIGATION_OFF;
465 } else if (!strcmp(str, "full")) {
466 mmio_mitigation = MMIO_MITIGATION_VERW;
467 } else if (!strcmp(str, "full,nosmt")) {
468 mmio_mitigation = MMIO_MITIGATION_VERW;
469 mmio_nosmt = true;
470 }
471
472 return 0;
473 }
474 early_param("mmio_stale_data", mmio_stale_data_parse_cmdline);
475
476 #undef pr_fmt
477 #define pr_fmt(fmt) "" fmt
478
md_clear_update_mitigation(void)479 static void __init md_clear_update_mitigation(void)
480 {
481 if (cpu_mitigations_off())
482 return;
483
484 if (!static_key_enabled(&mds_user_clear))
485 goto out;
486
487 /*
488 * mds_user_clear is now enabled. Update MDS, TAA and MMIO Stale Data
489 * mitigation, if necessary.
490 */
491 if (mds_mitigation == MDS_MITIGATION_OFF &&
492 boot_cpu_has_bug(X86_BUG_MDS)) {
493 mds_mitigation = MDS_MITIGATION_FULL;
494 mds_select_mitigation();
495 }
496 if (taa_mitigation == TAA_MITIGATION_OFF &&
497 boot_cpu_has_bug(X86_BUG_TAA)) {
498 taa_mitigation = TAA_MITIGATION_VERW;
499 taa_select_mitigation();
500 }
501 if (mmio_mitigation == MMIO_MITIGATION_OFF &&
502 boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA)) {
503 mmio_mitigation = MMIO_MITIGATION_VERW;
504 mmio_select_mitigation();
505 }
506 out:
507 if (boot_cpu_has_bug(X86_BUG_MDS))
508 pr_info("MDS: %s\n", mds_strings[mds_mitigation]);
509 if (boot_cpu_has_bug(X86_BUG_TAA))
510 pr_info("TAA: %s\n", taa_strings[taa_mitigation]);
511 if (boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
512 pr_info("MMIO Stale Data: %s\n", mmio_strings[mmio_mitigation]);
513 else if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
514 pr_info("MMIO Stale Data: Unknown: No mitigations\n");
515 }
516
md_clear_select_mitigation(void)517 static void __init md_clear_select_mitigation(void)
518 {
519 mds_select_mitigation();
520 taa_select_mitigation();
521 mmio_select_mitigation();
522
523 /*
524 * As MDS, TAA and MMIO Stale Data mitigations are inter-related, update
525 * and print their mitigation after MDS, TAA and MMIO Stale Data
526 * mitigation selection is done.
527 */
528 md_clear_update_mitigation();
529 }
530
531 #undef pr_fmt
532 #define pr_fmt(fmt) "SRBDS: " fmt
533
534 enum srbds_mitigations {
535 SRBDS_MITIGATION_OFF,
536 SRBDS_MITIGATION_UCODE_NEEDED,
537 SRBDS_MITIGATION_FULL,
538 SRBDS_MITIGATION_TSX_OFF,
539 SRBDS_MITIGATION_HYPERVISOR,
540 };
541
542 static enum srbds_mitigations srbds_mitigation __ro_after_init = SRBDS_MITIGATION_FULL;
543
544 static const char * const srbds_strings[] = {
545 [SRBDS_MITIGATION_OFF] = "Vulnerable",
546 [SRBDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
547 [SRBDS_MITIGATION_FULL] = "Mitigation: Microcode",
548 [SRBDS_MITIGATION_TSX_OFF] = "Mitigation: TSX disabled",
549 [SRBDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status",
550 };
551
552 static bool srbds_off;
553
update_srbds_msr(void)554 void update_srbds_msr(void)
555 {
556 u64 mcu_ctrl;
557
558 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
559 return;
560
561 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
562 return;
563
564 if (srbds_mitigation == SRBDS_MITIGATION_UCODE_NEEDED)
565 return;
566
567 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
568
569 switch (srbds_mitigation) {
570 case SRBDS_MITIGATION_OFF:
571 case SRBDS_MITIGATION_TSX_OFF:
572 mcu_ctrl |= RNGDS_MITG_DIS;
573 break;
574 case SRBDS_MITIGATION_FULL:
575 mcu_ctrl &= ~RNGDS_MITG_DIS;
576 break;
577 default:
578 break;
579 }
580
581 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
582 }
583
srbds_select_mitigation(void)584 static void __init srbds_select_mitigation(void)
585 {
586 u64 ia32_cap;
587
588 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
589 return;
590
591 /*
592 * Check to see if this is one of the MDS_NO systems supporting TSX that
593 * are only exposed to SRBDS when TSX is enabled or when CPU is affected
594 * by Processor MMIO Stale Data vulnerability.
595 */
596 ia32_cap = x86_read_arch_cap_msr();
597 if ((ia32_cap & ARCH_CAP_MDS_NO) && !boot_cpu_has(X86_FEATURE_RTM) &&
598 !boot_cpu_has_bug(X86_BUG_MMIO_STALE_DATA))
599 srbds_mitigation = SRBDS_MITIGATION_TSX_OFF;
600 else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
601 srbds_mitigation = SRBDS_MITIGATION_HYPERVISOR;
602 else if (!boot_cpu_has(X86_FEATURE_SRBDS_CTRL))
603 srbds_mitigation = SRBDS_MITIGATION_UCODE_NEEDED;
604 else if (cpu_mitigations_off() || srbds_off)
605 srbds_mitigation = SRBDS_MITIGATION_OFF;
606
607 update_srbds_msr();
608 pr_info("%s\n", srbds_strings[srbds_mitigation]);
609 }
610
srbds_parse_cmdline(char * str)611 static int __init srbds_parse_cmdline(char *str)
612 {
613 if (!str)
614 return -EINVAL;
615
616 if (!boot_cpu_has_bug(X86_BUG_SRBDS))
617 return 0;
618
619 srbds_off = !strcmp(str, "off");
620 return 0;
621 }
622 early_param("srbds", srbds_parse_cmdline);
623
624 #undef pr_fmt
625 #define pr_fmt(fmt) "GDS: " fmt
626
627 enum gds_mitigations {
628 GDS_MITIGATION_OFF,
629 GDS_MITIGATION_UCODE_NEEDED,
630 GDS_MITIGATION_FORCE,
631 GDS_MITIGATION_FULL,
632 GDS_MITIGATION_FULL_LOCKED,
633 GDS_MITIGATION_HYPERVISOR,
634 };
635
636 #if IS_ENABLED(CONFIG_GDS_FORCE_MITIGATION)
637 static enum gds_mitigations gds_mitigation __ro_after_init = GDS_MITIGATION_FORCE;
638 #else
639 static enum gds_mitigations gds_mitigation __ro_after_init = GDS_MITIGATION_FULL;
640 #endif
641
642 static const char * const gds_strings[] = {
643 [GDS_MITIGATION_OFF] = "Vulnerable",
644 [GDS_MITIGATION_UCODE_NEEDED] = "Vulnerable: No microcode",
645 [GDS_MITIGATION_FORCE] = "Mitigation: AVX disabled, no microcode",
646 [GDS_MITIGATION_FULL] = "Mitigation: Microcode",
647 [GDS_MITIGATION_FULL_LOCKED] = "Mitigation: Microcode (locked)",
648 [GDS_MITIGATION_HYPERVISOR] = "Unknown: Dependent on hypervisor status",
649 };
650
gds_ucode_mitigated(void)651 bool gds_ucode_mitigated(void)
652 {
653 return (gds_mitigation == GDS_MITIGATION_FULL ||
654 gds_mitigation == GDS_MITIGATION_FULL_LOCKED);
655 }
656 EXPORT_SYMBOL_GPL(gds_ucode_mitigated);
657
update_gds_msr(void)658 void update_gds_msr(void)
659 {
660 u64 mcu_ctrl_after;
661 u64 mcu_ctrl;
662
663 switch (gds_mitigation) {
664 case GDS_MITIGATION_OFF:
665 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
666 mcu_ctrl |= GDS_MITG_DIS;
667 break;
668 case GDS_MITIGATION_FULL_LOCKED:
669 /*
670 * The LOCKED state comes from the boot CPU. APs might not have
671 * the same state. Make sure the mitigation is enabled on all
672 * CPUs.
673 */
674 case GDS_MITIGATION_FULL:
675 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
676 mcu_ctrl &= ~GDS_MITG_DIS;
677 break;
678 case GDS_MITIGATION_FORCE:
679 case GDS_MITIGATION_UCODE_NEEDED:
680 case GDS_MITIGATION_HYPERVISOR:
681 return;
682 };
683
684 wrmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
685
686 /*
687 * Check to make sure that the WRMSR value was not ignored. Writes to
688 * GDS_MITG_DIS will be ignored if this processor is locked but the boot
689 * processor was not.
690 */
691 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl_after);
692 WARN_ON_ONCE(mcu_ctrl != mcu_ctrl_after);
693 }
694
gds_select_mitigation(void)695 static void __init gds_select_mitigation(void)
696 {
697 u64 mcu_ctrl;
698
699 if (!boot_cpu_has_bug(X86_BUG_GDS))
700 return;
701
702 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
703 gds_mitigation = GDS_MITIGATION_HYPERVISOR;
704 goto out;
705 }
706
707 if (cpu_mitigations_off())
708 gds_mitigation = GDS_MITIGATION_OFF;
709 /* Will verify below that mitigation _can_ be disabled */
710
711 /* No microcode */
712 if (!(x86_read_arch_cap_msr() & ARCH_CAP_GDS_CTRL)) {
713 if (gds_mitigation == GDS_MITIGATION_FORCE) {
714 /*
715 * This only needs to be done on the boot CPU so do it
716 * here rather than in update_gds_msr()
717 */
718 setup_clear_cpu_cap(X86_FEATURE_AVX);
719 pr_warn("Microcode update needed! Disabling AVX as mitigation.\n");
720 } else {
721 gds_mitigation = GDS_MITIGATION_UCODE_NEEDED;
722 }
723 goto out;
724 }
725
726 /* Microcode has mitigation, use it */
727 if (gds_mitigation == GDS_MITIGATION_FORCE)
728 gds_mitigation = GDS_MITIGATION_FULL;
729
730 rdmsrl(MSR_IA32_MCU_OPT_CTRL, mcu_ctrl);
731 if (mcu_ctrl & GDS_MITG_LOCKED) {
732 if (gds_mitigation == GDS_MITIGATION_OFF)
733 pr_warn("Mitigation locked. Disable failed.\n");
734
735 /*
736 * The mitigation is selected from the boot CPU. All other CPUs
737 * _should_ have the same state. If the boot CPU isn't locked
738 * but others are then update_gds_msr() will WARN() of the state
739 * mismatch. If the boot CPU is locked update_gds_msr() will
740 * ensure the other CPUs have the mitigation enabled.
741 */
742 gds_mitigation = GDS_MITIGATION_FULL_LOCKED;
743 }
744
745 update_gds_msr();
746 out:
747 pr_info("%s\n", gds_strings[gds_mitigation]);
748 }
749
gds_parse_cmdline(char * str)750 static int __init gds_parse_cmdline(char *str)
751 {
752 if (!str)
753 return -EINVAL;
754
755 if (!boot_cpu_has_bug(X86_BUG_GDS))
756 return 0;
757
758 if (!strcmp(str, "off"))
759 gds_mitigation = GDS_MITIGATION_OFF;
760 else if (!strcmp(str, "force"))
761 gds_mitigation = GDS_MITIGATION_FORCE;
762
763 return 0;
764 }
765 early_param("gather_data_sampling", gds_parse_cmdline);
766
767 #undef pr_fmt
768 #define pr_fmt(fmt) "Spectre V1 : " fmt
769
770 enum spectre_v1_mitigation {
771 SPECTRE_V1_MITIGATION_NONE,
772 SPECTRE_V1_MITIGATION_AUTO,
773 };
774
775 static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init =
776 SPECTRE_V1_MITIGATION_AUTO;
777
778 static const char * const spectre_v1_strings[] = {
779 [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers",
780 [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization",
781 };
782
783 /*
784 * Does SMAP provide full mitigation against speculative kernel access to
785 * userspace?
786 */
smap_works_speculatively(void)787 static bool smap_works_speculatively(void)
788 {
789 if (!boot_cpu_has(X86_FEATURE_SMAP))
790 return false;
791
792 /*
793 * On CPUs which are vulnerable to Meltdown, SMAP does not
794 * prevent speculative access to user data in the L1 cache.
795 * Consider SMAP to be non-functional as a mitigation on these
796 * CPUs.
797 */
798 if (boot_cpu_has(X86_BUG_CPU_MELTDOWN))
799 return false;
800
801 return true;
802 }
803
spectre_v1_select_mitigation(void)804 static void __init spectre_v1_select_mitigation(void)
805 {
806 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) {
807 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
808 return;
809 }
810
811 if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) {
812 /*
813 * With Spectre v1, a user can speculatively control either
814 * path of a conditional swapgs with a user-controlled GS
815 * value. The mitigation is to add lfences to both code paths.
816 *
817 * If FSGSBASE is enabled, the user can put a kernel address in
818 * GS, in which case SMAP provides no protection.
819 *
820 * If FSGSBASE is disabled, the user can only put a user space
821 * address in GS. That makes an attack harder, but still
822 * possible if there's no SMAP protection.
823 */
824 if (boot_cpu_has(X86_FEATURE_FSGSBASE) ||
825 !smap_works_speculatively()) {
826 /*
827 * Mitigation can be provided from SWAPGS itself or
828 * PTI as the CR3 write in the Meltdown mitigation
829 * is serializing.
830 *
831 * If neither is there, mitigate with an LFENCE to
832 * stop speculation through swapgs.
833 */
834 if (boot_cpu_has_bug(X86_BUG_SWAPGS) &&
835 !boot_cpu_has(X86_FEATURE_PTI))
836 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER);
837
838 /*
839 * Enable lfences in the kernel entry (non-swapgs)
840 * paths, to prevent user entry from speculatively
841 * skipping swapgs.
842 */
843 setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL);
844 }
845 }
846
847 pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]);
848 }
849
nospectre_v1_cmdline(char * str)850 static int __init nospectre_v1_cmdline(char *str)
851 {
852 spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE;
853 return 0;
854 }
855 early_param("nospectre_v1", nospectre_v1_cmdline);
856
857 static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init =
858 SPECTRE_V2_NONE;
859
860 #undef pr_fmt
861 #define pr_fmt(fmt) "RETBleed: " fmt
862
863 enum retbleed_mitigation {
864 RETBLEED_MITIGATION_NONE,
865 RETBLEED_MITIGATION_UNRET,
866 RETBLEED_MITIGATION_IBPB,
867 RETBLEED_MITIGATION_IBRS,
868 RETBLEED_MITIGATION_EIBRS,
869 };
870
871 enum retbleed_mitigation_cmd {
872 RETBLEED_CMD_OFF,
873 RETBLEED_CMD_AUTO,
874 RETBLEED_CMD_UNRET,
875 RETBLEED_CMD_IBPB,
876 };
877
878 const char * const retbleed_strings[] = {
879 [RETBLEED_MITIGATION_NONE] = "Vulnerable",
880 [RETBLEED_MITIGATION_UNRET] = "Mitigation: untrained return thunk",
881 [RETBLEED_MITIGATION_IBPB] = "Mitigation: IBPB",
882 [RETBLEED_MITIGATION_IBRS] = "Mitigation: IBRS",
883 [RETBLEED_MITIGATION_EIBRS] = "Mitigation: Enhanced IBRS",
884 };
885
886 static enum retbleed_mitigation retbleed_mitigation __ro_after_init =
887 RETBLEED_MITIGATION_NONE;
888 static enum retbleed_mitigation_cmd retbleed_cmd __ro_after_init =
889 RETBLEED_CMD_AUTO;
890
891 static int __ro_after_init retbleed_nosmt = false;
892
retbleed_parse_cmdline(char * str)893 static int __init retbleed_parse_cmdline(char *str)
894 {
895 if (!str)
896 return -EINVAL;
897
898 while (str) {
899 char *next = strchr(str, ',');
900 if (next) {
901 *next = 0;
902 next++;
903 }
904
905 if (!strcmp(str, "off")) {
906 retbleed_cmd = RETBLEED_CMD_OFF;
907 } else if (!strcmp(str, "auto")) {
908 retbleed_cmd = RETBLEED_CMD_AUTO;
909 } else if (!strcmp(str, "unret")) {
910 retbleed_cmd = RETBLEED_CMD_UNRET;
911 } else if (!strcmp(str, "ibpb")) {
912 retbleed_cmd = RETBLEED_CMD_IBPB;
913 } else if (!strcmp(str, "nosmt")) {
914 retbleed_nosmt = true;
915 } else {
916 pr_err("Ignoring unknown retbleed option (%s).", str);
917 }
918
919 str = next;
920 }
921
922 return 0;
923 }
924 early_param("retbleed", retbleed_parse_cmdline);
925
926 #define RETBLEED_UNTRAIN_MSG "WARNING: BTB untrained return thunk mitigation is only effective on AMD/Hygon!\n"
927 #define RETBLEED_INTEL_MSG "WARNING: Spectre v2 mitigation leaves CPU vulnerable to RETBleed attacks, data leaks possible!\n"
928
retbleed_select_mitigation(void)929 static void __init retbleed_select_mitigation(void)
930 {
931 bool mitigate_smt = false;
932
933 if (!boot_cpu_has_bug(X86_BUG_RETBLEED) || cpu_mitigations_off())
934 return;
935
936 switch (retbleed_cmd) {
937 case RETBLEED_CMD_OFF:
938 return;
939
940 case RETBLEED_CMD_UNRET:
941 if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY)) {
942 retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
943 } else {
944 pr_err("WARNING: kernel not compiled with CPU_UNRET_ENTRY.\n");
945 goto do_cmd_auto;
946 }
947 break;
948
949 case RETBLEED_CMD_IBPB:
950 if (!boot_cpu_has(X86_FEATURE_IBPB)) {
951 pr_err("WARNING: CPU does not support IBPB.\n");
952 goto do_cmd_auto;
953 } else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY)) {
954 retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
955 } else {
956 pr_err("WARNING: kernel not compiled with CPU_IBPB_ENTRY.\n");
957 goto do_cmd_auto;
958 }
959 break;
960
961 do_cmd_auto:
962 case RETBLEED_CMD_AUTO:
963 default:
964 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
965 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
966 if (IS_ENABLED(CONFIG_CPU_UNRET_ENTRY))
967 retbleed_mitigation = RETBLEED_MITIGATION_UNRET;
968 else if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY) && boot_cpu_has(X86_FEATURE_IBPB))
969 retbleed_mitigation = RETBLEED_MITIGATION_IBPB;
970 }
971
972 /*
973 * The Intel mitigation (IBRS or eIBRS) was already selected in
974 * spectre_v2_select_mitigation(). 'retbleed_mitigation' will
975 * be set accordingly below.
976 */
977
978 break;
979 }
980
981 switch (retbleed_mitigation) {
982 case RETBLEED_MITIGATION_UNRET:
983 setup_force_cpu_cap(X86_FEATURE_RETHUNK);
984 setup_force_cpu_cap(X86_FEATURE_UNRET);
985
986 if (IS_ENABLED(CONFIG_RETHUNK))
987 x86_return_thunk = retbleed_return_thunk;
988
989 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
990 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
991 pr_err(RETBLEED_UNTRAIN_MSG);
992
993 mitigate_smt = true;
994 break;
995
996 case RETBLEED_MITIGATION_IBPB:
997 setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB);
998 mitigate_smt = true;
999 break;
1000
1001 default:
1002 break;
1003 }
1004
1005 if (mitigate_smt && !boot_cpu_has(X86_FEATURE_STIBP) &&
1006 (retbleed_nosmt || cpu_mitigations_auto_nosmt()))
1007 cpu_smt_disable(false);
1008
1009 /*
1010 * Let IBRS trump all on Intel without affecting the effects of the
1011 * retbleed= cmdline option.
1012 */
1013 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
1014 switch (spectre_v2_enabled) {
1015 case SPECTRE_V2_IBRS:
1016 retbleed_mitigation = RETBLEED_MITIGATION_IBRS;
1017 break;
1018 case SPECTRE_V2_EIBRS:
1019 case SPECTRE_V2_EIBRS_RETPOLINE:
1020 case SPECTRE_V2_EIBRS_LFENCE:
1021 retbleed_mitigation = RETBLEED_MITIGATION_EIBRS;
1022 break;
1023 default:
1024 pr_err(RETBLEED_INTEL_MSG);
1025 }
1026 }
1027
1028 pr_info("%s\n", retbleed_strings[retbleed_mitigation]);
1029 }
1030
1031 #undef pr_fmt
1032 #define pr_fmt(fmt) "Spectre V2 : " fmt
1033
1034 static enum spectre_v2_user_mitigation spectre_v2_user_stibp __ro_after_init =
1035 SPECTRE_V2_USER_NONE;
1036 static enum spectre_v2_user_mitigation spectre_v2_user_ibpb __ro_after_init =
1037 SPECTRE_V2_USER_NONE;
1038
1039 #ifdef CONFIG_RETPOLINE
1040 static bool spectre_v2_bad_module;
1041
retpoline_module_ok(bool has_retpoline)1042 bool retpoline_module_ok(bool has_retpoline)
1043 {
1044 if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
1045 return true;
1046
1047 pr_err("System may be vulnerable to spectre v2\n");
1048 spectre_v2_bad_module = true;
1049 return false;
1050 }
1051
spectre_v2_module_string(void)1052 static inline const char *spectre_v2_module_string(void)
1053 {
1054 return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
1055 }
1056 #else
spectre_v2_module_string(void)1057 static inline const char *spectre_v2_module_string(void) { return ""; }
1058 #endif
1059
1060 #define SPECTRE_V2_LFENCE_MSG "WARNING: LFENCE mitigation is not recommended for this CPU, data leaks possible!\n"
1061 #define SPECTRE_V2_EIBRS_EBPF_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS on, data leaks possible via Spectre v2 BHB attacks!\n"
1062 #define SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG "WARNING: Unprivileged eBPF is enabled with eIBRS+LFENCE mitigation and SMT, data leaks possible via Spectre v2 BHB attacks!\n"
1063 #define SPECTRE_V2_IBRS_PERF_MSG "WARNING: IBRS mitigation selected on Enhanced IBRS CPU, this may cause unnecessary performance loss\n"
1064
1065 #ifdef CONFIG_BPF_SYSCALL
unpriv_ebpf_notify(int new_state)1066 void unpriv_ebpf_notify(int new_state)
1067 {
1068 if (new_state)
1069 return;
1070
1071 /* Unprivileged eBPF is enabled */
1072
1073 switch (spectre_v2_enabled) {
1074 case SPECTRE_V2_EIBRS:
1075 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
1076 break;
1077 case SPECTRE_V2_EIBRS_LFENCE:
1078 if (sched_smt_active())
1079 pr_err(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1080 break;
1081 default:
1082 break;
1083 }
1084 }
1085 #endif
1086
match_option(const char * arg,int arglen,const char * opt)1087 static inline bool match_option(const char *arg, int arglen, const char *opt)
1088 {
1089 int len = strlen(opt);
1090
1091 return len == arglen && !strncmp(arg, opt, len);
1092 }
1093
1094 /* The kernel command line selection for spectre v2 */
1095 enum spectre_v2_mitigation_cmd {
1096 SPECTRE_V2_CMD_NONE,
1097 SPECTRE_V2_CMD_AUTO,
1098 SPECTRE_V2_CMD_FORCE,
1099 SPECTRE_V2_CMD_RETPOLINE,
1100 SPECTRE_V2_CMD_RETPOLINE_GENERIC,
1101 SPECTRE_V2_CMD_RETPOLINE_LFENCE,
1102 SPECTRE_V2_CMD_EIBRS,
1103 SPECTRE_V2_CMD_EIBRS_RETPOLINE,
1104 SPECTRE_V2_CMD_EIBRS_LFENCE,
1105 SPECTRE_V2_CMD_IBRS,
1106 };
1107
1108 enum spectre_v2_user_cmd {
1109 SPECTRE_V2_USER_CMD_NONE,
1110 SPECTRE_V2_USER_CMD_AUTO,
1111 SPECTRE_V2_USER_CMD_FORCE,
1112 SPECTRE_V2_USER_CMD_PRCTL,
1113 SPECTRE_V2_USER_CMD_PRCTL_IBPB,
1114 SPECTRE_V2_USER_CMD_SECCOMP,
1115 SPECTRE_V2_USER_CMD_SECCOMP_IBPB,
1116 };
1117
1118 static const char * const spectre_v2_user_strings[] = {
1119 [SPECTRE_V2_USER_NONE] = "User space: Vulnerable",
1120 [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection",
1121 [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection",
1122 [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl",
1123 [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl",
1124 };
1125
1126 static const struct {
1127 const char *option;
1128 enum spectre_v2_user_cmd cmd;
1129 bool secure;
1130 } v2_user_options[] __initconst = {
1131 { "auto", SPECTRE_V2_USER_CMD_AUTO, false },
1132 { "off", SPECTRE_V2_USER_CMD_NONE, false },
1133 { "on", SPECTRE_V2_USER_CMD_FORCE, true },
1134 { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false },
1135 { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false },
1136 { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false },
1137 { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false },
1138 };
1139
spec_v2_user_print_cond(const char * reason,bool secure)1140 static void __init spec_v2_user_print_cond(const char *reason, bool secure)
1141 {
1142 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1143 pr_info("spectre_v2_user=%s forced on command line.\n", reason);
1144 }
1145
1146 static __ro_after_init enum spectre_v2_mitigation_cmd spectre_v2_cmd;
1147
1148 static enum spectre_v2_user_cmd __init
spectre_v2_parse_user_cmdline(void)1149 spectre_v2_parse_user_cmdline(void)
1150 {
1151 char arg[20];
1152 int ret, i;
1153
1154 switch (spectre_v2_cmd) {
1155 case SPECTRE_V2_CMD_NONE:
1156 return SPECTRE_V2_USER_CMD_NONE;
1157 case SPECTRE_V2_CMD_FORCE:
1158 return SPECTRE_V2_USER_CMD_FORCE;
1159 default:
1160 break;
1161 }
1162
1163 ret = cmdline_find_option(boot_command_line, "spectre_v2_user",
1164 arg, sizeof(arg));
1165 if (ret < 0)
1166 return SPECTRE_V2_USER_CMD_AUTO;
1167
1168 for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) {
1169 if (match_option(arg, ret, v2_user_options[i].option)) {
1170 spec_v2_user_print_cond(v2_user_options[i].option,
1171 v2_user_options[i].secure);
1172 return v2_user_options[i].cmd;
1173 }
1174 }
1175
1176 pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg);
1177 return SPECTRE_V2_USER_CMD_AUTO;
1178 }
1179
spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)1180 static inline bool spectre_v2_in_eibrs_mode(enum spectre_v2_mitigation mode)
1181 {
1182 return mode == SPECTRE_V2_EIBRS ||
1183 mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1184 mode == SPECTRE_V2_EIBRS_LFENCE;
1185 }
1186
spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)1187 static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode)
1188 {
1189 return spectre_v2_in_eibrs_mode(mode) || mode == SPECTRE_V2_IBRS;
1190 }
1191
1192 static void __init
spectre_v2_user_select_mitigation(void)1193 spectre_v2_user_select_mitigation(void)
1194 {
1195 enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE;
1196 bool smt_possible = IS_ENABLED(CONFIG_SMP);
1197 enum spectre_v2_user_cmd cmd;
1198
1199 if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP))
1200 return;
1201
1202 if (cpu_smt_control == CPU_SMT_FORCE_DISABLED ||
1203 cpu_smt_control == CPU_SMT_NOT_SUPPORTED)
1204 smt_possible = false;
1205
1206 cmd = spectre_v2_parse_user_cmdline();
1207 switch (cmd) {
1208 case SPECTRE_V2_USER_CMD_NONE:
1209 goto set_mode;
1210 case SPECTRE_V2_USER_CMD_FORCE:
1211 mode = SPECTRE_V2_USER_STRICT;
1212 break;
1213 case SPECTRE_V2_USER_CMD_PRCTL:
1214 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1215 mode = SPECTRE_V2_USER_PRCTL;
1216 break;
1217 case SPECTRE_V2_USER_CMD_AUTO:
1218 case SPECTRE_V2_USER_CMD_SECCOMP:
1219 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1220 if (IS_ENABLED(CONFIG_SECCOMP))
1221 mode = SPECTRE_V2_USER_SECCOMP;
1222 else
1223 mode = SPECTRE_V2_USER_PRCTL;
1224 break;
1225 }
1226
1227 /* Initialize Indirect Branch Prediction Barrier */
1228 if (boot_cpu_has(X86_FEATURE_IBPB)) {
1229 setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
1230
1231 spectre_v2_user_ibpb = mode;
1232 switch (cmd) {
1233 case SPECTRE_V2_USER_CMD_FORCE:
1234 case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
1235 case SPECTRE_V2_USER_CMD_SECCOMP_IBPB:
1236 static_branch_enable(&switch_mm_always_ibpb);
1237 spectre_v2_user_ibpb = SPECTRE_V2_USER_STRICT;
1238 break;
1239 case SPECTRE_V2_USER_CMD_PRCTL:
1240 case SPECTRE_V2_USER_CMD_AUTO:
1241 case SPECTRE_V2_USER_CMD_SECCOMP:
1242 static_branch_enable(&switch_mm_cond_ibpb);
1243 break;
1244 default:
1245 break;
1246 }
1247
1248 pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n",
1249 static_key_enabled(&switch_mm_always_ibpb) ?
1250 "always-on" : "conditional");
1251 }
1252
1253 /*
1254 * If no STIBP, enhanced IBRS is enabled, or SMT impossible, STIBP
1255 * is not required.
1256 *
1257 * Enhanced IBRS also protects against cross-thread branch target
1258 * injection in user-mode as the IBRS bit remains always set which
1259 * implicitly enables cross-thread protections. However, in legacy IBRS
1260 * mode, the IBRS bit is set only on kernel entry and cleared on return
1261 * to userspace. This disables the implicit cross-thread protection,
1262 * so allow for STIBP to be selected in that case.
1263 */
1264 if (!boot_cpu_has(X86_FEATURE_STIBP) ||
1265 !smt_possible ||
1266 spectre_v2_in_eibrs_mode(spectre_v2_enabled))
1267 return;
1268
1269 /*
1270 * At this point, an STIBP mode other than "off" has been set.
1271 * If STIBP support is not being forced, check if STIBP always-on
1272 * is preferred.
1273 */
1274 if (mode != SPECTRE_V2_USER_STRICT &&
1275 boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON))
1276 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1277
1278 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET ||
1279 retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
1280 if (mode != SPECTRE_V2_USER_STRICT &&
1281 mode != SPECTRE_V2_USER_STRICT_PREFERRED)
1282 pr_info("Selecting STIBP always-on mode to complement retbleed mitigation\n");
1283 mode = SPECTRE_V2_USER_STRICT_PREFERRED;
1284 }
1285
1286 spectre_v2_user_stibp = mode;
1287
1288 set_mode:
1289 pr_info("%s\n", spectre_v2_user_strings[mode]);
1290 }
1291
1292 static const char * const spectre_v2_strings[] = {
1293 [SPECTRE_V2_NONE] = "Vulnerable",
1294 [SPECTRE_V2_RETPOLINE] = "Mitigation: Retpolines",
1295 [SPECTRE_V2_LFENCE] = "Mitigation: LFENCE",
1296 [SPECTRE_V2_EIBRS] = "Mitigation: Enhanced IBRS",
1297 [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced IBRS + LFENCE",
1298 [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced IBRS + Retpolines",
1299 [SPECTRE_V2_IBRS] = "Mitigation: IBRS",
1300 };
1301
1302 static const struct {
1303 const char *option;
1304 enum spectre_v2_mitigation_cmd cmd;
1305 bool secure;
1306 } mitigation_options[] __initconst = {
1307 { "off", SPECTRE_V2_CMD_NONE, false },
1308 { "on", SPECTRE_V2_CMD_FORCE, true },
1309 { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false },
1310 { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
1311 { "retpoline,lfence", SPECTRE_V2_CMD_RETPOLINE_LFENCE, false },
1312 { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
1313 { "eibrs", SPECTRE_V2_CMD_EIBRS, false },
1314 { "eibrs,lfence", SPECTRE_V2_CMD_EIBRS_LFENCE, false },
1315 { "eibrs,retpoline", SPECTRE_V2_CMD_EIBRS_RETPOLINE, false },
1316 { "auto", SPECTRE_V2_CMD_AUTO, false },
1317 { "ibrs", SPECTRE_V2_CMD_IBRS, false },
1318 };
1319
spec_v2_print_cond(const char * reason,bool secure)1320 static void __init spec_v2_print_cond(const char *reason, bool secure)
1321 {
1322 if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure)
1323 pr_info("%s selected on command line.\n", reason);
1324 }
1325
spectre_v2_parse_cmdline(void)1326 static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
1327 {
1328 enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
1329 char arg[20];
1330 int ret, i;
1331
1332 if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") ||
1333 cpu_mitigations_off())
1334 return SPECTRE_V2_CMD_NONE;
1335
1336 ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
1337 if (ret < 0)
1338 return SPECTRE_V2_CMD_AUTO;
1339
1340 for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
1341 if (!match_option(arg, ret, mitigation_options[i].option))
1342 continue;
1343 cmd = mitigation_options[i].cmd;
1344 break;
1345 }
1346
1347 if (i >= ARRAY_SIZE(mitigation_options)) {
1348 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1349 return SPECTRE_V2_CMD_AUTO;
1350 }
1351
1352 if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
1353 cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1354 cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC ||
1355 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1356 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1357 !IS_ENABLED(CONFIG_RETPOLINE)) {
1358 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1359 mitigation_options[i].option);
1360 return SPECTRE_V2_CMD_AUTO;
1361 }
1362
1363 if ((cmd == SPECTRE_V2_CMD_EIBRS ||
1364 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE ||
1365 cmd == SPECTRE_V2_CMD_EIBRS_RETPOLINE) &&
1366 !boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1367 pr_err("%s selected but CPU doesn't have eIBRS. Switching to AUTO select\n",
1368 mitigation_options[i].option);
1369 return SPECTRE_V2_CMD_AUTO;
1370 }
1371
1372 if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE ||
1373 cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) &&
1374 !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
1375 pr_err("%s selected, but CPU doesn't have a serializing LFENCE. Switching to AUTO select\n",
1376 mitigation_options[i].option);
1377 return SPECTRE_V2_CMD_AUTO;
1378 }
1379
1380 if (cmd == SPECTRE_V2_CMD_IBRS && !IS_ENABLED(CONFIG_CPU_IBRS_ENTRY)) {
1381 pr_err("%s selected but not compiled in. Switching to AUTO select\n",
1382 mitigation_options[i].option);
1383 return SPECTRE_V2_CMD_AUTO;
1384 }
1385
1386 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1387 pr_err("%s selected but not Intel CPU. Switching to AUTO select\n",
1388 mitigation_options[i].option);
1389 return SPECTRE_V2_CMD_AUTO;
1390 }
1391
1392 if (cmd == SPECTRE_V2_CMD_IBRS && !boot_cpu_has(X86_FEATURE_IBRS)) {
1393 pr_err("%s selected but CPU doesn't have IBRS. Switching to AUTO select\n",
1394 mitigation_options[i].option);
1395 return SPECTRE_V2_CMD_AUTO;
1396 }
1397
1398 if (cmd == SPECTRE_V2_CMD_IBRS && boot_cpu_has(X86_FEATURE_XENPV)) {
1399 pr_err("%s selected but running as XenPV guest. Switching to AUTO select\n",
1400 mitigation_options[i].option);
1401 return SPECTRE_V2_CMD_AUTO;
1402 }
1403
1404 spec_v2_print_cond(mitigation_options[i].option,
1405 mitigation_options[i].secure);
1406 return cmd;
1407 }
1408
spectre_v2_select_retpoline(void)1409 static enum spectre_v2_mitigation __init spectre_v2_select_retpoline(void)
1410 {
1411 if (!IS_ENABLED(CONFIG_RETPOLINE)) {
1412 pr_err("Kernel not compiled with retpoline; no mitigation available!");
1413 return SPECTRE_V2_NONE;
1414 }
1415
1416 return SPECTRE_V2_RETPOLINE;
1417 }
1418
1419 /* Disable in-kernel use of non-RSB RET predictors */
spec_ctrl_disable_kernel_rrsba(void)1420 static void __init spec_ctrl_disable_kernel_rrsba(void)
1421 {
1422 u64 ia32_cap;
1423
1424 if (!boot_cpu_has(X86_FEATURE_RRSBA_CTRL))
1425 return;
1426
1427 ia32_cap = x86_read_arch_cap_msr();
1428
1429 if (ia32_cap & ARCH_CAP_RRSBA) {
1430 x86_spec_ctrl_base |= SPEC_CTRL_RRSBA_DIS_S;
1431 update_spec_ctrl(x86_spec_ctrl_base);
1432 }
1433 }
1434
spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode)1435 static void __init spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_mitigation mode)
1436 {
1437 /*
1438 * Similar to context switches, there are two types of RSB attacks
1439 * after VM exit:
1440 *
1441 * 1) RSB underflow
1442 *
1443 * 2) Poisoned RSB entry
1444 *
1445 * When retpoline is enabled, both are mitigated by filling/clearing
1446 * the RSB.
1447 *
1448 * When IBRS is enabled, while #1 would be mitigated by the IBRS branch
1449 * prediction isolation protections, RSB still needs to be cleared
1450 * because of #2. Note that SMEP provides no protection here, unlike
1451 * user-space-poisoned RSB entries.
1452 *
1453 * eIBRS should protect against RSB poisoning, but if the EIBRS_PBRSB
1454 * bug is present then a LITE version of RSB protection is required,
1455 * just a single call needs to retire before a RET is executed.
1456 */
1457 switch (mode) {
1458 case SPECTRE_V2_NONE:
1459 return;
1460
1461 case SPECTRE_V2_EIBRS_LFENCE:
1462 case SPECTRE_V2_EIBRS:
1463 if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
1464 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT_LITE);
1465 pr_info("Spectre v2 / PBRSB-eIBRS: Retire a single CALL on VMEXIT\n");
1466 }
1467 return;
1468
1469 case SPECTRE_V2_EIBRS_RETPOLINE:
1470 case SPECTRE_V2_RETPOLINE:
1471 case SPECTRE_V2_LFENCE:
1472 case SPECTRE_V2_IBRS:
1473 setup_force_cpu_cap(X86_FEATURE_RSB_VMEXIT);
1474 pr_info("Spectre v2 / SpectreRSB : Filling RSB on VMEXIT\n");
1475 return;
1476 }
1477
1478 pr_warn_once("Unknown Spectre v2 mode, disabling RSB mitigation at VM exit");
1479 dump_stack();
1480 }
1481
spectre_v2_select_mitigation(void)1482 static void __init spectre_v2_select_mitigation(void)
1483 {
1484 enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
1485 enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
1486
1487 /*
1488 * If the CPU is not affected and the command line mode is NONE or AUTO
1489 * then nothing to do.
1490 */
1491 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
1492 (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
1493 return;
1494
1495 switch (cmd) {
1496 case SPECTRE_V2_CMD_NONE:
1497 return;
1498
1499 case SPECTRE_V2_CMD_FORCE:
1500 case SPECTRE_V2_CMD_AUTO:
1501 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) {
1502 mode = SPECTRE_V2_EIBRS;
1503 break;
1504 }
1505
1506 if (IS_ENABLED(CONFIG_CPU_IBRS_ENTRY) &&
1507 boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1508 retbleed_cmd != RETBLEED_CMD_OFF &&
1509 boot_cpu_has(X86_FEATURE_IBRS) &&
1510 boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
1511 mode = SPECTRE_V2_IBRS;
1512 break;
1513 }
1514
1515 mode = spectre_v2_select_retpoline();
1516 break;
1517
1518 case SPECTRE_V2_CMD_RETPOLINE_LFENCE:
1519 pr_err(SPECTRE_V2_LFENCE_MSG);
1520 mode = SPECTRE_V2_LFENCE;
1521 break;
1522
1523 case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
1524 mode = SPECTRE_V2_RETPOLINE;
1525 break;
1526
1527 case SPECTRE_V2_CMD_RETPOLINE:
1528 mode = spectre_v2_select_retpoline();
1529 break;
1530
1531 case SPECTRE_V2_CMD_IBRS:
1532 mode = SPECTRE_V2_IBRS;
1533 break;
1534
1535 case SPECTRE_V2_CMD_EIBRS:
1536 mode = SPECTRE_V2_EIBRS;
1537 break;
1538
1539 case SPECTRE_V2_CMD_EIBRS_LFENCE:
1540 mode = SPECTRE_V2_EIBRS_LFENCE;
1541 break;
1542
1543 case SPECTRE_V2_CMD_EIBRS_RETPOLINE:
1544 mode = SPECTRE_V2_EIBRS_RETPOLINE;
1545 break;
1546 }
1547
1548 if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
1549 pr_err(SPECTRE_V2_EIBRS_EBPF_MSG);
1550
1551 if (spectre_v2_in_ibrs_mode(mode)) {
1552 x86_spec_ctrl_base |= SPEC_CTRL_IBRS;
1553 update_spec_ctrl(x86_spec_ctrl_base);
1554 }
1555
1556 switch (mode) {
1557 case SPECTRE_V2_NONE:
1558 case SPECTRE_V2_EIBRS:
1559 break;
1560
1561 case SPECTRE_V2_IBRS:
1562 setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS);
1563 if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED))
1564 pr_warn(SPECTRE_V2_IBRS_PERF_MSG);
1565 break;
1566
1567 case SPECTRE_V2_LFENCE:
1568 case SPECTRE_V2_EIBRS_LFENCE:
1569 setup_force_cpu_cap(X86_FEATURE_RETPOLINE_LFENCE);
1570 fallthrough;
1571
1572 case SPECTRE_V2_RETPOLINE:
1573 case SPECTRE_V2_EIBRS_RETPOLINE:
1574 setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
1575 break;
1576 }
1577
1578 /*
1579 * Disable alternate RSB predictions in kernel when indirect CALLs and
1580 * JMPs gets protection against BHI and Intramode-BTI, but RET
1581 * prediction from a non-RSB predictor is still a risk.
1582 */
1583 if (mode == SPECTRE_V2_EIBRS_LFENCE ||
1584 mode == SPECTRE_V2_EIBRS_RETPOLINE ||
1585 mode == SPECTRE_V2_RETPOLINE)
1586 spec_ctrl_disable_kernel_rrsba();
1587
1588 spectre_v2_enabled = mode;
1589 pr_info("%s\n", spectre_v2_strings[mode]);
1590
1591 /*
1592 * If Spectre v2 protection has been enabled, fill the RSB during a
1593 * context switch. In general there are two types of RSB attacks
1594 * across context switches, for which the CALLs/RETs may be unbalanced.
1595 *
1596 * 1) RSB underflow
1597 *
1598 * Some Intel parts have "bottomless RSB". When the RSB is empty,
1599 * speculated return targets may come from the branch predictor,
1600 * which could have a user-poisoned BTB or BHB entry.
1601 *
1602 * AMD has it even worse: *all* returns are speculated from the BTB,
1603 * regardless of the state of the RSB.
1604 *
1605 * When IBRS or eIBRS is enabled, the "user -> kernel" attack
1606 * scenario is mitigated by the IBRS branch prediction isolation
1607 * properties, so the RSB buffer filling wouldn't be necessary to
1608 * protect against this type of attack.
1609 *
1610 * The "user -> user" attack scenario is mitigated by RSB filling.
1611 *
1612 * 2) Poisoned RSB entry
1613 *
1614 * If the 'next' in-kernel return stack is shorter than 'prev',
1615 * 'next' could be tricked into speculating with a user-poisoned RSB
1616 * entry.
1617 *
1618 * The "user -> kernel" attack scenario is mitigated by SMEP and
1619 * eIBRS.
1620 *
1621 * The "user -> user" scenario, also known as SpectreBHB, requires
1622 * RSB clearing.
1623 *
1624 * So to mitigate all cases, unconditionally fill RSB on context
1625 * switches.
1626 *
1627 * FIXME: Is this pointless for retbleed-affected AMD?
1628 */
1629 setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
1630 pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n");
1631
1632 spectre_v2_determine_rsb_fill_type_at_vmexit(mode);
1633
1634 /*
1635 * Retpoline protects the kernel, but doesn't protect firmware. IBRS
1636 * and Enhanced IBRS protect firmware too, so enable IBRS around
1637 * firmware calls only when IBRS / Enhanced IBRS aren't otherwise
1638 * enabled.
1639 *
1640 * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because
1641 * the user might select retpoline on the kernel command line and if
1642 * the CPU supports Enhanced IBRS, kernel might un-intentionally not
1643 * enable IBRS around firmware calls.
1644 */
1645 if (boot_cpu_has_bug(X86_BUG_RETBLEED) &&
1646 boot_cpu_has(X86_FEATURE_IBPB) &&
1647 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1648 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)) {
1649
1650 if (retbleed_cmd != RETBLEED_CMD_IBPB) {
1651 setup_force_cpu_cap(X86_FEATURE_USE_IBPB_FW);
1652 pr_info("Enabling Speculation Barrier for firmware calls\n");
1653 }
1654
1655 } else if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) {
1656 setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
1657 pr_info("Enabling Restricted Speculation for firmware calls\n");
1658 }
1659
1660 /* Set up IBPB and STIBP depending on the general spectre V2 command */
1661 spectre_v2_cmd = cmd;
1662 }
1663
update_stibp_msr(void * __unused)1664 static void update_stibp_msr(void * __unused)
1665 {
1666 u64 val = spec_ctrl_current() | (x86_spec_ctrl_base & SPEC_CTRL_STIBP);
1667 update_spec_ctrl(val);
1668 }
1669
1670 /* Update x86_spec_ctrl_base in case SMT state changed. */
update_stibp_strict(void)1671 static void update_stibp_strict(void)
1672 {
1673 u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP;
1674
1675 if (sched_smt_active())
1676 mask |= SPEC_CTRL_STIBP;
1677
1678 if (mask == x86_spec_ctrl_base)
1679 return;
1680
1681 pr_info("Update user space SMT mitigation: STIBP %s\n",
1682 mask & SPEC_CTRL_STIBP ? "always-on" : "off");
1683 x86_spec_ctrl_base = mask;
1684 on_each_cpu(update_stibp_msr, NULL, 1);
1685 }
1686
1687 /* Update the static key controlling the evaluation of TIF_SPEC_IB */
update_indir_branch_cond(void)1688 static void update_indir_branch_cond(void)
1689 {
1690 if (sched_smt_active())
1691 static_branch_enable(&switch_to_cond_stibp);
1692 else
1693 static_branch_disable(&switch_to_cond_stibp);
1694 }
1695
1696 #undef pr_fmt
1697 #define pr_fmt(fmt) fmt
1698
1699 /* Update the static key controlling the MDS CPU buffer clear in idle */
update_mds_branch_idle(void)1700 static void update_mds_branch_idle(void)
1701 {
1702 u64 ia32_cap = x86_read_arch_cap_msr();
1703
1704 /*
1705 * Enable the idle clearing if SMT is active on CPUs which are
1706 * affected only by MSBDS and not any other MDS variant.
1707 *
1708 * The other variants cannot be mitigated when SMT is enabled, so
1709 * clearing the buffers on idle just to prevent the Store Buffer
1710 * repartitioning leak would be a window dressing exercise.
1711 */
1712 if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY))
1713 return;
1714
1715 if (sched_smt_active()) {
1716 static_branch_enable(&mds_idle_clear);
1717 } else if (mmio_mitigation == MMIO_MITIGATION_OFF ||
1718 (ia32_cap & ARCH_CAP_FBSDP_NO)) {
1719 static_branch_disable(&mds_idle_clear);
1720 }
1721 }
1722
1723 #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n"
1724 #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n"
1725 #define MMIO_MSG_SMT "MMIO Stale Data CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/processor_mmio_stale_data.html for more details.\n"
1726
cpu_bugs_smt_update(void)1727 void cpu_bugs_smt_update(void)
1728 {
1729 mutex_lock(&spec_ctrl_mutex);
1730
1731 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
1732 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
1733 pr_warn_once(SPECTRE_V2_EIBRS_LFENCE_EBPF_SMT_MSG);
1734
1735 switch (spectre_v2_user_stibp) {
1736 case SPECTRE_V2_USER_NONE:
1737 break;
1738 case SPECTRE_V2_USER_STRICT:
1739 case SPECTRE_V2_USER_STRICT_PREFERRED:
1740 update_stibp_strict();
1741 break;
1742 case SPECTRE_V2_USER_PRCTL:
1743 case SPECTRE_V2_USER_SECCOMP:
1744 update_indir_branch_cond();
1745 break;
1746 }
1747
1748 switch (mds_mitigation) {
1749 case MDS_MITIGATION_FULL:
1750 case MDS_MITIGATION_VMWERV:
1751 if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY))
1752 pr_warn_once(MDS_MSG_SMT);
1753 update_mds_branch_idle();
1754 break;
1755 case MDS_MITIGATION_OFF:
1756 break;
1757 }
1758
1759 switch (taa_mitigation) {
1760 case TAA_MITIGATION_VERW:
1761 case TAA_MITIGATION_UCODE_NEEDED:
1762 if (sched_smt_active())
1763 pr_warn_once(TAA_MSG_SMT);
1764 break;
1765 case TAA_MITIGATION_TSX_DISABLED:
1766 case TAA_MITIGATION_OFF:
1767 break;
1768 }
1769
1770 switch (mmio_mitigation) {
1771 case MMIO_MITIGATION_VERW:
1772 case MMIO_MITIGATION_UCODE_NEEDED:
1773 if (sched_smt_active())
1774 pr_warn_once(MMIO_MSG_SMT);
1775 break;
1776 case MMIO_MITIGATION_OFF:
1777 break;
1778 }
1779
1780 mutex_unlock(&spec_ctrl_mutex);
1781 }
1782
1783 #undef pr_fmt
1784 #define pr_fmt(fmt) "Speculative Store Bypass: " fmt
1785
1786 static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE;
1787
1788 /* The kernel command line selection */
1789 enum ssb_mitigation_cmd {
1790 SPEC_STORE_BYPASS_CMD_NONE,
1791 SPEC_STORE_BYPASS_CMD_AUTO,
1792 SPEC_STORE_BYPASS_CMD_ON,
1793 SPEC_STORE_BYPASS_CMD_PRCTL,
1794 SPEC_STORE_BYPASS_CMD_SECCOMP,
1795 };
1796
1797 static const char * const ssb_strings[] = {
1798 [SPEC_STORE_BYPASS_NONE] = "Vulnerable",
1799 [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled",
1800 [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl",
1801 [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp",
1802 };
1803
1804 static const struct {
1805 const char *option;
1806 enum ssb_mitigation_cmd cmd;
1807 } ssb_mitigation_options[] __initconst = {
1808 { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
1809 { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */
1810 { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */
1811 { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
1812 { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */
1813 };
1814
ssb_parse_cmdline(void)1815 static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
1816 {
1817 enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
1818 char arg[20];
1819 int ret, i;
1820
1821 if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") ||
1822 cpu_mitigations_off()) {
1823 return SPEC_STORE_BYPASS_CMD_NONE;
1824 } else {
1825 ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
1826 arg, sizeof(arg));
1827 if (ret < 0)
1828 return SPEC_STORE_BYPASS_CMD_AUTO;
1829
1830 for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
1831 if (!match_option(arg, ret, ssb_mitigation_options[i].option))
1832 continue;
1833
1834 cmd = ssb_mitigation_options[i].cmd;
1835 break;
1836 }
1837
1838 if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
1839 pr_err("unknown option (%s). Switching to AUTO select\n", arg);
1840 return SPEC_STORE_BYPASS_CMD_AUTO;
1841 }
1842 }
1843
1844 return cmd;
1845 }
1846
__ssb_select_mitigation(void)1847 static enum ssb_mitigation __init __ssb_select_mitigation(void)
1848 {
1849 enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
1850 enum ssb_mitigation_cmd cmd;
1851
1852 if (!boot_cpu_has(X86_FEATURE_SSBD))
1853 return mode;
1854
1855 cmd = ssb_parse_cmdline();
1856 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
1857 (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
1858 cmd == SPEC_STORE_BYPASS_CMD_AUTO))
1859 return mode;
1860
1861 switch (cmd) {
1862 case SPEC_STORE_BYPASS_CMD_AUTO:
1863 case SPEC_STORE_BYPASS_CMD_SECCOMP:
1864 /*
1865 * Choose prctl+seccomp as the default mode if seccomp is
1866 * enabled.
1867 */
1868 if (IS_ENABLED(CONFIG_SECCOMP))
1869 mode = SPEC_STORE_BYPASS_SECCOMP;
1870 else
1871 mode = SPEC_STORE_BYPASS_PRCTL;
1872 break;
1873 case SPEC_STORE_BYPASS_CMD_ON:
1874 mode = SPEC_STORE_BYPASS_DISABLE;
1875 break;
1876 case SPEC_STORE_BYPASS_CMD_PRCTL:
1877 mode = SPEC_STORE_BYPASS_PRCTL;
1878 break;
1879 case SPEC_STORE_BYPASS_CMD_NONE:
1880 break;
1881 }
1882
1883 /*
1884 * We have three CPU feature flags that are in play here:
1885 * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
1886 * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass
1887 * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
1888 */
1889 if (mode == SPEC_STORE_BYPASS_DISABLE) {
1890 setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
1891 /*
1892 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may
1893 * use a completely different MSR and bit dependent on family.
1894 */
1895 if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) &&
1896 !static_cpu_has(X86_FEATURE_AMD_SSBD)) {
1897 x86_amd_ssb_disable();
1898 } else {
1899 x86_spec_ctrl_base |= SPEC_CTRL_SSBD;
1900 update_spec_ctrl(x86_spec_ctrl_base);
1901 }
1902 }
1903
1904 return mode;
1905 }
1906
ssb_select_mitigation(void)1907 static void ssb_select_mitigation(void)
1908 {
1909 ssb_mode = __ssb_select_mitigation();
1910
1911 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
1912 pr_info("%s\n", ssb_strings[ssb_mode]);
1913 }
1914
1915 #undef pr_fmt
1916 #define pr_fmt(fmt) "Speculation prctl: " fmt
1917
task_update_spec_tif(struct task_struct * tsk)1918 static void task_update_spec_tif(struct task_struct *tsk)
1919 {
1920 /* Force the update of the real TIF bits */
1921 set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE);
1922
1923 /*
1924 * Immediately update the speculation control MSRs for the current
1925 * task, but for a non-current task delay setting the CPU
1926 * mitigation until it is scheduled next.
1927 *
1928 * This can only happen for SECCOMP mitigation. For PRCTL it's
1929 * always the current task.
1930 */
1931 if (tsk == current)
1932 speculation_ctrl_update_current();
1933 }
1934
ssb_prctl_set(struct task_struct * task,unsigned long ctrl)1935 static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1936 {
1937 if (ssb_mode != SPEC_STORE_BYPASS_PRCTL &&
1938 ssb_mode != SPEC_STORE_BYPASS_SECCOMP)
1939 return -ENXIO;
1940
1941 switch (ctrl) {
1942 case PR_SPEC_ENABLE:
1943 /* If speculation is force disabled, enable is not allowed */
1944 if (task_spec_ssb_force_disable(task))
1945 return -EPERM;
1946 task_clear_spec_ssb_disable(task);
1947 task_clear_spec_ssb_noexec(task);
1948 task_update_spec_tif(task);
1949 break;
1950 case PR_SPEC_DISABLE:
1951 task_set_spec_ssb_disable(task);
1952 task_clear_spec_ssb_noexec(task);
1953 task_update_spec_tif(task);
1954 break;
1955 case PR_SPEC_FORCE_DISABLE:
1956 task_set_spec_ssb_disable(task);
1957 task_set_spec_ssb_force_disable(task);
1958 task_clear_spec_ssb_noexec(task);
1959 task_update_spec_tif(task);
1960 break;
1961 case PR_SPEC_DISABLE_NOEXEC:
1962 if (task_spec_ssb_force_disable(task))
1963 return -EPERM;
1964 task_set_spec_ssb_disable(task);
1965 task_set_spec_ssb_noexec(task);
1966 task_update_spec_tif(task);
1967 break;
1968 default:
1969 return -ERANGE;
1970 }
1971 return 0;
1972 }
1973
is_spec_ib_user_controlled(void)1974 static bool is_spec_ib_user_controlled(void)
1975 {
1976 return spectre_v2_user_ibpb == SPECTRE_V2_USER_PRCTL ||
1977 spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
1978 spectre_v2_user_stibp == SPECTRE_V2_USER_PRCTL ||
1979 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP;
1980 }
1981
ib_prctl_set(struct task_struct * task,unsigned long ctrl)1982 static int ib_prctl_set(struct task_struct *task, unsigned long ctrl)
1983 {
1984 switch (ctrl) {
1985 case PR_SPEC_ENABLE:
1986 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
1987 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
1988 return 0;
1989
1990 /*
1991 * With strict mode for both IBPB and STIBP, the instruction
1992 * code paths avoid checking this task flag and instead,
1993 * unconditionally run the instruction. However, STIBP and IBPB
1994 * are independent and either can be set to conditionally
1995 * enabled regardless of the mode of the other.
1996 *
1997 * If either is set to conditional, allow the task flag to be
1998 * updated, unless it was force-disabled by a previous prctl
1999 * call. Currently, this is possible on an AMD CPU which has the
2000 * feature X86_FEATURE_AMD_STIBP_ALWAYS_ON. In this case, if the
2001 * kernel is booted with 'spectre_v2_user=seccomp', then
2002 * spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP and
2003 * spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED.
2004 */
2005 if (!is_spec_ib_user_controlled() ||
2006 task_spec_ib_force_disable(task))
2007 return -EPERM;
2008
2009 task_clear_spec_ib_disable(task);
2010 task_update_spec_tif(task);
2011 break;
2012 case PR_SPEC_DISABLE:
2013 case PR_SPEC_FORCE_DISABLE:
2014 /*
2015 * Indirect branch speculation is always allowed when
2016 * mitigation is force disabled.
2017 */
2018 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
2019 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
2020 return -EPERM;
2021
2022 if (!is_spec_ib_user_controlled())
2023 return 0;
2024
2025 task_set_spec_ib_disable(task);
2026 if (ctrl == PR_SPEC_FORCE_DISABLE)
2027 task_set_spec_ib_force_disable(task);
2028 task_update_spec_tif(task);
2029 if (task == current)
2030 indirect_branch_prediction_barrier();
2031 break;
2032 default:
2033 return -ERANGE;
2034 }
2035 return 0;
2036 }
2037
arch_prctl_spec_ctrl_set(struct task_struct * task,unsigned long which,unsigned long ctrl)2038 int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
2039 unsigned long ctrl)
2040 {
2041 switch (which) {
2042 case PR_SPEC_STORE_BYPASS:
2043 return ssb_prctl_set(task, ctrl);
2044 case PR_SPEC_INDIRECT_BRANCH:
2045 return ib_prctl_set(task, ctrl);
2046 default:
2047 return -ENODEV;
2048 }
2049 }
2050
2051 #ifdef CONFIG_SECCOMP
arch_seccomp_spec_mitigate(struct task_struct * task)2052 void arch_seccomp_spec_mitigate(struct task_struct *task)
2053 {
2054 if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP)
2055 ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE);
2056 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_SECCOMP ||
2057 spectre_v2_user_stibp == SPECTRE_V2_USER_SECCOMP)
2058 ib_prctl_set(task, PR_SPEC_FORCE_DISABLE);
2059 }
2060 #endif
2061
ssb_prctl_get(struct task_struct * task)2062 static int ssb_prctl_get(struct task_struct *task)
2063 {
2064 switch (ssb_mode) {
2065 case SPEC_STORE_BYPASS_DISABLE:
2066 return PR_SPEC_DISABLE;
2067 case SPEC_STORE_BYPASS_SECCOMP:
2068 case SPEC_STORE_BYPASS_PRCTL:
2069 if (task_spec_ssb_force_disable(task))
2070 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
2071 if (task_spec_ssb_noexec(task))
2072 return PR_SPEC_PRCTL | PR_SPEC_DISABLE_NOEXEC;
2073 if (task_spec_ssb_disable(task))
2074 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
2075 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
2076 default:
2077 if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
2078 return PR_SPEC_ENABLE;
2079 return PR_SPEC_NOT_AFFECTED;
2080 }
2081 }
2082
ib_prctl_get(struct task_struct * task)2083 static int ib_prctl_get(struct task_struct *task)
2084 {
2085 if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
2086 return PR_SPEC_NOT_AFFECTED;
2087
2088 if (spectre_v2_user_ibpb == SPECTRE_V2_USER_NONE &&
2089 spectre_v2_user_stibp == SPECTRE_V2_USER_NONE)
2090 return PR_SPEC_ENABLE;
2091 else if (is_spec_ib_user_controlled()) {
2092 if (task_spec_ib_force_disable(task))
2093 return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE;
2094 if (task_spec_ib_disable(task))
2095 return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
2096 return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
2097 } else if (spectre_v2_user_ibpb == SPECTRE_V2_USER_STRICT ||
2098 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
2099 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED)
2100 return PR_SPEC_DISABLE;
2101 else
2102 return PR_SPEC_NOT_AFFECTED;
2103 }
2104
arch_prctl_spec_ctrl_get(struct task_struct * task,unsigned long which)2105 int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
2106 {
2107 switch (which) {
2108 case PR_SPEC_STORE_BYPASS:
2109 return ssb_prctl_get(task);
2110 case PR_SPEC_INDIRECT_BRANCH:
2111 return ib_prctl_get(task);
2112 default:
2113 return -ENODEV;
2114 }
2115 }
2116
x86_spec_ctrl_setup_ap(void)2117 void x86_spec_ctrl_setup_ap(void)
2118 {
2119 if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
2120 update_spec_ctrl(x86_spec_ctrl_base);
2121
2122 if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
2123 x86_amd_ssb_disable();
2124 }
2125
2126 bool itlb_multihit_kvm_mitigation;
2127 EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation);
2128
2129 #undef pr_fmt
2130 #define pr_fmt(fmt) "L1TF: " fmt
2131
2132 /* Default mitigation for L1TF-affected CPUs */
2133 enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH;
2134 #if IS_ENABLED(CONFIG_KVM_INTEL)
2135 EXPORT_SYMBOL_GPL(l1tf_mitigation);
2136 #endif
2137 enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
2138 EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation);
2139
2140 /*
2141 * These CPUs all support 44bits physical address space internally in the
2142 * cache but CPUID can report a smaller number of physical address bits.
2143 *
2144 * The L1TF mitigation uses the top most address bit for the inversion of
2145 * non present PTEs. When the installed memory reaches into the top most
2146 * address bit due to memory holes, which has been observed on machines
2147 * which report 36bits physical address bits and have 32G RAM installed,
2148 * then the mitigation range check in l1tf_select_mitigation() triggers.
2149 * This is a false positive because the mitigation is still possible due to
2150 * the fact that the cache uses 44bit internally. Use the cache bits
2151 * instead of the reported physical bits and adjust them on the affected
2152 * machines to 44bit if the reported bits are less than 44.
2153 */
override_cache_bits(struct cpuinfo_x86 * c)2154 static void override_cache_bits(struct cpuinfo_x86 *c)
2155 {
2156 if (c->x86 != 6)
2157 return;
2158
2159 switch (c->x86_model) {
2160 case INTEL_FAM6_NEHALEM:
2161 case INTEL_FAM6_WESTMERE:
2162 case INTEL_FAM6_SANDYBRIDGE:
2163 case INTEL_FAM6_IVYBRIDGE:
2164 case INTEL_FAM6_HASWELL:
2165 case INTEL_FAM6_HASWELL_L:
2166 case INTEL_FAM6_HASWELL_G:
2167 case INTEL_FAM6_BROADWELL:
2168 case INTEL_FAM6_BROADWELL_G:
2169 case INTEL_FAM6_SKYLAKE_L:
2170 case INTEL_FAM6_SKYLAKE:
2171 case INTEL_FAM6_KABYLAKE_L:
2172 case INTEL_FAM6_KABYLAKE:
2173 if (c->x86_cache_bits < 44)
2174 c->x86_cache_bits = 44;
2175 break;
2176 }
2177 }
2178
l1tf_select_mitigation(void)2179 static void __init l1tf_select_mitigation(void)
2180 {
2181 u64 half_pa;
2182
2183 if (!boot_cpu_has_bug(X86_BUG_L1TF))
2184 return;
2185
2186 if (cpu_mitigations_off())
2187 l1tf_mitigation = L1TF_MITIGATION_OFF;
2188 else if (cpu_mitigations_auto_nosmt())
2189 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2190
2191 override_cache_bits(&boot_cpu_data);
2192
2193 switch (l1tf_mitigation) {
2194 case L1TF_MITIGATION_OFF:
2195 case L1TF_MITIGATION_FLUSH_NOWARN:
2196 case L1TF_MITIGATION_FLUSH:
2197 break;
2198 case L1TF_MITIGATION_FLUSH_NOSMT:
2199 case L1TF_MITIGATION_FULL:
2200 cpu_smt_disable(false);
2201 break;
2202 case L1TF_MITIGATION_FULL_FORCE:
2203 cpu_smt_disable(true);
2204 break;
2205 }
2206
2207 #if CONFIG_PGTABLE_LEVELS == 2
2208 pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n");
2209 return;
2210 #endif
2211
2212 half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT;
2213 if (l1tf_mitigation != L1TF_MITIGATION_OFF &&
2214 e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) {
2215 pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n");
2216 pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n",
2217 half_pa);
2218 pr_info("However, doing so will make a part of your RAM unusable.\n");
2219 pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n");
2220 return;
2221 }
2222
2223 setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV);
2224 }
2225
l1tf_cmdline(char * str)2226 static int __init l1tf_cmdline(char *str)
2227 {
2228 if (!boot_cpu_has_bug(X86_BUG_L1TF))
2229 return 0;
2230
2231 if (!str)
2232 return -EINVAL;
2233
2234 if (!strcmp(str, "off"))
2235 l1tf_mitigation = L1TF_MITIGATION_OFF;
2236 else if (!strcmp(str, "flush,nowarn"))
2237 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN;
2238 else if (!strcmp(str, "flush"))
2239 l1tf_mitigation = L1TF_MITIGATION_FLUSH;
2240 else if (!strcmp(str, "flush,nosmt"))
2241 l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT;
2242 else if (!strcmp(str, "full"))
2243 l1tf_mitigation = L1TF_MITIGATION_FULL;
2244 else if (!strcmp(str, "full,force"))
2245 l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE;
2246
2247 return 0;
2248 }
2249 early_param("l1tf", l1tf_cmdline);
2250
2251 #undef pr_fmt
2252 #define pr_fmt(fmt) "Speculative Return Stack Overflow: " fmt
2253
2254 enum srso_mitigation {
2255 SRSO_MITIGATION_NONE,
2256 SRSO_MITIGATION_MICROCODE,
2257 SRSO_MITIGATION_SAFE_RET,
2258 SRSO_MITIGATION_IBPB,
2259 SRSO_MITIGATION_IBPB_ON_VMEXIT,
2260 };
2261
2262 enum srso_mitigation_cmd {
2263 SRSO_CMD_OFF,
2264 SRSO_CMD_MICROCODE,
2265 SRSO_CMD_SAFE_RET,
2266 SRSO_CMD_IBPB,
2267 SRSO_CMD_IBPB_ON_VMEXIT,
2268 };
2269
2270 static const char * const srso_strings[] = {
2271 [SRSO_MITIGATION_NONE] = "Vulnerable",
2272 [SRSO_MITIGATION_MICROCODE] = "Mitigation: microcode",
2273 [SRSO_MITIGATION_SAFE_RET] = "Mitigation: safe RET",
2274 [SRSO_MITIGATION_IBPB] = "Mitigation: IBPB",
2275 [SRSO_MITIGATION_IBPB_ON_VMEXIT] = "Mitigation: IBPB on VMEXIT only"
2276 };
2277
2278 static enum srso_mitigation srso_mitigation __ro_after_init = SRSO_MITIGATION_NONE;
2279 static enum srso_mitigation_cmd srso_cmd __ro_after_init = SRSO_CMD_SAFE_RET;
2280
srso_parse_cmdline(char * str)2281 static int __init srso_parse_cmdline(char *str)
2282 {
2283 if (!str)
2284 return -EINVAL;
2285
2286 if (!strcmp(str, "off"))
2287 srso_cmd = SRSO_CMD_OFF;
2288 else if (!strcmp(str, "microcode"))
2289 srso_cmd = SRSO_CMD_MICROCODE;
2290 else if (!strcmp(str, "safe-ret"))
2291 srso_cmd = SRSO_CMD_SAFE_RET;
2292 else if (!strcmp(str, "ibpb"))
2293 srso_cmd = SRSO_CMD_IBPB;
2294 else if (!strcmp(str, "ibpb-vmexit"))
2295 srso_cmd = SRSO_CMD_IBPB_ON_VMEXIT;
2296 else
2297 pr_err("Ignoring unknown SRSO option (%s).", str);
2298
2299 return 0;
2300 }
2301 early_param("spec_rstack_overflow", srso_parse_cmdline);
2302
2303 #define SRSO_NOTICE "WARNING: See https://kernel.org/doc/html/latest/admin-guide/hw-vuln/srso.html for mitigation options."
2304
srso_select_mitigation(void)2305 static void __init srso_select_mitigation(void)
2306 {
2307 bool has_microcode;
2308
2309 if (!boot_cpu_has_bug(X86_BUG_SRSO) || cpu_mitigations_off())
2310 goto pred_cmd;
2311
2312 /*
2313 * The first check is for the kernel running as a guest in order
2314 * for guests to verify whether IBPB is a viable mitigation.
2315 */
2316 has_microcode = boot_cpu_has(X86_FEATURE_IBPB_BRTYPE) || cpu_has_ibpb_brtype_microcode();
2317 if (!has_microcode) {
2318 pr_warn("IBPB-extending microcode not applied!\n");
2319 pr_warn(SRSO_NOTICE);
2320 } else {
2321 /*
2322 * Enable the synthetic (even if in a real CPUID leaf)
2323 * flags for guests.
2324 */
2325 setup_force_cpu_cap(X86_FEATURE_IBPB_BRTYPE);
2326
2327 /*
2328 * Zen1/2 with SMT off aren't vulnerable after the right
2329 * IBPB microcode has been applied.
2330 */
2331 if (boot_cpu_data.x86 < 0x19 && !cpu_smt_possible()) {
2332 setup_force_cpu_cap(X86_FEATURE_SRSO_NO);
2333 return;
2334 }
2335 }
2336
2337 if (retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
2338 if (has_microcode) {
2339 pr_err("Retbleed IBPB mitigation enabled, using same for SRSO\n");
2340 srso_mitigation = SRSO_MITIGATION_IBPB;
2341 goto pred_cmd;
2342 }
2343 }
2344
2345 switch (srso_cmd) {
2346 case SRSO_CMD_OFF:
2347 goto pred_cmd;
2348
2349 case SRSO_CMD_MICROCODE:
2350 if (has_microcode) {
2351 srso_mitigation = SRSO_MITIGATION_MICROCODE;
2352 pr_warn(SRSO_NOTICE);
2353 }
2354 break;
2355
2356 case SRSO_CMD_SAFE_RET:
2357 if (IS_ENABLED(CONFIG_CPU_SRSO)) {
2358 /*
2359 * Enable the return thunk for generated code
2360 * like ftrace, static_call, etc.
2361 */
2362 setup_force_cpu_cap(X86_FEATURE_RETHUNK);
2363 setup_force_cpu_cap(X86_FEATURE_UNRET);
2364
2365 if (boot_cpu_data.x86 == 0x19) {
2366 setup_force_cpu_cap(X86_FEATURE_SRSO_ALIAS);
2367 x86_return_thunk = srso_alias_return_thunk;
2368 } else {
2369 setup_force_cpu_cap(X86_FEATURE_SRSO);
2370 x86_return_thunk = srso_return_thunk;
2371 }
2372 srso_mitigation = SRSO_MITIGATION_SAFE_RET;
2373 } else {
2374 pr_err("WARNING: kernel not compiled with CPU_SRSO.\n");
2375 goto pred_cmd;
2376 }
2377 break;
2378
2379 case SRSO_CMD_IBPB:
2380 if (IS_ENABLED(CONFIG_CPU_IBPB_ENTRY)) {
2381 if (has_microcode) {
2382 setup_force_cpu_cap(X86_FEATURE_ENTRY_IBPB);
2383 srso_mitigation = SRSO_MITIGATION_IBPB;
2384 }
2385 } else {
2386 pr_err("WARNING: kernel not compiled with CPU_IBPB_ENTRY.\n");
2387 goto pred_cmd;
2388 }
2389 break;
2390
2391 case SRSO_CMD_IBPB_ON_VMEXIT:
2392 if (IS_ENABLED(CONFIG_CPU_SRSO)) {
2393 if (!boot_cpu_has(X86_FEATURE_ENTRY_IBPB) && has_microcode) {
2394 setup_force_cpu_cap(X86_FEATURE_IBPB_ON_VMEXIT);
2395 srso_mitigation = SRSO_MITIGATION_IBPB_ON_VMEXIT;
2396 }
2397 } else {
2398 pr_err("WARNING: kernel not compiled with CPU_SRSO.\n");
2399 goto pred_cmd;
2400 }
2401 break;
2402
2403 default:
2404 break;
2405 }
2406
2407 pr_info("%s%s\n", srso_strings[srso_mitigation], (has_microcode ? "" : ", no microcode"));
2408
2409 pred_cmd:
2410 if ((!boot_cpu_has_bug(X86_BUG_SRSO) || srso_cmd == SRSO_CMD_OFF) &&
2411 boot_cpu_has(X86_FEATURE_SBPB))
2412 x86_pred_cmd = PRED_CMD_SBPB;
2413 }
2414
2415 #undef pr_fmt
2416 #define pr_fmt(fmt) fmt
2417
2418 #ifdef CONFIG_SYSFS
2419
2420 #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion"
2421
2422 #if IS_ENABLED(CONFIG_KVM_INTEL)
2423 static const char * const l1tf_vmx_states[] = {
2424 [VMENTER_L1D_FLUSH_AUTO] = "auto",
2425 [VMENTER_L1D_FLUSH_NEVER] = "vulnerable",
2426 [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes",
2427 [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes",
2428 [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled",
2429 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary"
2430 };
2431
l1tf_show_state(char * buf)2432 static ssize_t l1tf_show_state(char *buf)
2433 {
2434 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO)
2435 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2436
2437 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED ||
2438 (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER &&
2439 sched_smt_active())) {
2440 return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG,
2441 l1tf_vmx_states[l1tf_vmx_mitigation]);
2442 }
2443
2444 return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG,
2445 l1tf_vmx_states[l1tf_vmx_mitigation],
2446 sched_smt_active() ? "vulnerable" : "disabled");
2447 }
2448
itlb_multihit_show_state(char * buf)2449 static ssize_t itlb_multihit_show_state(char *buf)
2450 {
2451 if (!boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) ||
2452 !boot_cpu_has(X86_FEATURE_VMX))
2453 return sprintf(buf, "KVM: Mitigation: VMX unsupported\n");
2454 else if (!(cr4_read_shadow() & X86_CR4_VMXE))
2455 return sprintf(buf, "KVM: Mitigation: VMX disabled\n");
2456 else if (itlb_multihit_kvm_mitigation)
2457 return sprintf(buf, "KVM: Mitigation: Split huge pages\n");
2458 else
2459 return sprintf(buf, "KVM: Vulnerable\n");
2460 }
2461 #else
l1tf_show_state(char * buf)2462 static ssize_t l1tf_show_state(char *buf)
2463 {
2464 return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG);
2465 }
2466
itlb_multihit_show_state(char * buf)2467 static ssize_t itlb_multihit_show_state(char *buf)
2468 {
2469 return sprintf(buf, "Processor vulnerable\n");
2470 }
2471 #endif
2472
mds_show_state(char * buf)2473 static ssize_t mds_show_state(char *buf)
2474 {
2475 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2476 return sprintf(buf, "%s; SMT Host state unknown\n",
2477 mds_strings[mds_mitigation]);
2478 }
2479
2480 if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) {
2481 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2482 (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" :
2483 sched_smt_active() ? "mitigated" : "disabled"));
2484 }
2485
2486 return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation],
2487 sched_smt_active() ? "vulnerable" : "disabled");
2488 }
2489
tsx_async_abort_show_state(char * buf)2490 static ssize_t tsx_async_abort_show_state(char *buf)
2491 {
2492 if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) ||
2493 (taa_mitigation == TAA_MITIGATION_OFF))
2494 return sprintf(buf, "%s\n", taa_strings[taa_mitigation]);
2495
2496 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2497 return sprintf(buf, "%s; SMT Host state unknown\n",
2498 taa_strings[taa_mitigation]);
2499 }
2500
2501 return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation],
2502 sched_smt_active() ? "vulnerable" : "disabled");
2503 }
2504
mmio_stale_data_show_state(char * buf)2505 static ssize_t mmio_stale_data_show_state(char *buf)
2506 {
2507 if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2508 return sysfs_emit(buf, "Unknown: No mitigations\n");
2509
2510 if (mmio_mitigation == MMIO_MITIGATION_OFF)
2511 return sysfs_emit(buf, "%s\n", mmio_strings[mmio_mitigation]);
2512
2513 if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
2514 return sysfs_emit(buf, "%s; SMT Host state unknown\n",
2515 mmio_strings[mmio_mitigation]);
2516 }
2517
2518 return sysfs_emit(buf, "%s; SMT %s\n", mmio_strings[mmio_mitigation],
2519 sched_smt_active() ? "vulnerable" : "disabled");
2520 }
2521
stibp_state(void)2522 static char *stibp_state(void)
2523 {
2524 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled))
2525 return "";
2526
2527 switch (spectre_v2_user_stibp) {
2528 case SPECTRE_V2_USER_NONE:
2529 return ", STIBP: disabled";
2530 case SPECTRE_V2_USER_STRICT:
2531 return ", STIBP: forced";
2532 case SPECTRE_V2_USER_STRICT_PREFERRED:
2533 return ", STIBP: always-on";
2534 case SPECTRE_V2_USER_PRCTL:
2535 case SPECTRE_V2_USER_SECCOMP:
2536 if (static_key_enabled(&switch_to_cond_stibp))
2537 return ", STIBP: conditional";
2538 }
2539 return "";
2540 }
2541
ibpb_state(void)2542 static char *ibpb_state(void)
2543 {
2544 if (boot_cpu_has(X86_FEATURE_IBPB)) {
2545 if (static_key_enabled(&switch_mm_always_ibpb))
2546 return ", IBPB: always-on";
2547 if (static_key_enabled(&switch_mm_cond_ibpb))
2548 return ", IBPB: conditional";
2549 return ", IBPB: disabled";
2550 }
2551 return "";
2552 }
2553
pbrsb_eibrs_state(void)2554 static char *pbrsb_eibrs_state(void)
2555 {
2556 if (boot_cpu_has_bug(X86_BUG_EIBRS_PBRSB)) {
2557 if (boot_cpu_has(X86_FEATURE_RSB_VMEXIT_LITE) ||
2558 boot_cpu_has(X86_FEATURE_RSB_VMEXIT))
2559 return ", PBRSB-eIBRS: SW sequence";
2560 else
2561 return ", PBRSB-eIBRS: Vulnerable";
2562 } else {
2563 return ", PBRSB-eIBRS: Not affected";
2564 }
2565 }
2566
spectre_v2_show_state(char * buf)2567 static ssize_t spectre_v2_show_state(char *buf)
2568 {
2569 if (spectre_v2_enabled == SPECTRE_V2_LFENCE)
2570 return sprintf(buf, "Vulnerable: LFENCE\n");
2571
2572 if (spectre_v2_enabled == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled())
2573 return sprintf(buf, "Vulnerable: eIBRS with unprivileged eBPF\n");
2574
2575 if (sched_smt_active() && unprivileged_ebpf_enabled() &&
2576 spectre_v2_enabled == SPECTRE_V2_EIBRS_LFENCE)
2577 return sprintf(buf, "Vulnerable: eIBRS+LFENCE with unprivileged eBPF and SMT\n");
2578
2579 return sprintf(buf, "%s%s%s%s%s%s%s\n",
2580 spectre_v2_strings[spectre_v2_enabled],
2581 ibpb_state(),
2582 boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
2583 stibp_state(),
2584 boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "",
2585 pbrsb_eibrs_state(),
2586 spectre_v2_module_string());
2587 }
2588
srbds_show_state(char * buf)2589 static ssize_t srbds_show_state(char *buf)
2590 {
2591 return sprintf(buf, "%s\n", srbds_strings[srbds_mitigation]);
2592 }
2593
retbleed_show_state(char * buf)2594 static ssize_t retbleed_show_state(char *buf)
2595 {
2596 if (retbleed_mitigation == RETBLEED_MITIGATION_UNRET ||
2597 retbleed_mitigation == RETBLEED_MITIGATION_IBPB) {
2598 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
2599 boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
2600 return sprintf(buf, "Vulnerable: untrained return thunk / IBPB on non-AMD based uarch\n");
2601
2602 return sprintf(buf, "%s; SMT %s\n",
2603 retbleed_strings[retbleed_mitigation],
2604 !sched_smt_active() ? "disabled" :
2605 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT ||
2606 spectre_v2_user_stibp == SPECTRE_V2_USER_STRICT_PREFERRED ?
2607 "enabled with STIBP protection" : "vulnerable");
2608 }
2609
2610 return sprintf(buf, "%s\n", retbleed_strings[retbleed_mitigation]);
2611 }
2612
gds_show_state(char * buf)2613 static ssize_t gds_show_state(char *buf)
2614 {
2615 return sysfs_emit(buf, "%s\n", gds_strings[gds_mitigation]);
2616 }
2617
srso_show_state(char * buf)2618 static ssize_t srso_show_state(char *buf)
2619 {
2620 if (boot_cpu_has(X86_FEATURE_SRSO_NO))
2621 return sysfs_emit(buf, "Mitigation: SMT disabled\n");
2622
2623 return sysfs_emit(buf, "%s%s\n",
2624 srso_strings[srso_mitigation],
2625 boot_cpu_has(X86_FEATURE_IBPB_BRTYPE) ? "" : ", no microcode");
2626 }
2627
cpu_show_common(struct device * dev,struct device_attribute * attr,char * buf,unsigned int bug)2628 static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
2629 char *buf, unsigned int bug)
2630 {
2631 if (!boot_cpu_has_bug(bug))
2632 return sprintf(buf, "Not affected\n");
2633
2634 switch (bug) {
2635 case X86_BUG_CPU_MELTDOWN:
2636 if (boot_cpu_has(X86_FEATURE_PTI))
2637 return sprintf(buf, "Mitigation: PTI\n");
2638
2639 if (hypervisor_is_type(X86_HYPER_XEN_PV))
2640 return sprintf(buf, "Unknown (XEN PV detected, hypervisor mitigation required)\n");
2641
2642 break;
2643
2644 case X86_BUG_SPECTRE_V1:
2645 return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]);
2646
2647 case X86_BUG_SPECTRE_V2:
2648 return spectre_v2_show_state(buf);
2649
2650 case X86_BUG_SPEC_STORE_BYPASS:
2651 return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
2652
2653 case X86_BUG_L1TF:
2654 if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV))
2655 return l1tf_show_state(buf);
2656 break;
2657
2658 case X86_BUG_MDS:
2659 return mds_show_state(buf);
2660
2661 case X86_BUG_TAA:
2662 return tsx_async_abort_show_state(buf);
2663
2664 case X86_BUG_ITLB_MULTIHIT:
2665 return itlb_multihit_show_state(buf);
2666
2667 case X86_BUG_SRBDS:
2668 return srbds_show_state(buf);
2669
2670 case X86_BUG_MMIO_STALE_DATA:
2671 case X86_BUG_MMIO_UNKNOWN:
2672 return mmio_stale_data_show_state(buf);
2673
2674 case X86_BUG_RETBLEED:
2675 return retbleed_show_state(buf);
2676
2677 case X86_BUG_GDS:
2678 return gds_show_state(buf);
2679
2680 case X86_BUG_SRSO:
2681 return srso_show_state(buf);
2682
2683 default:
2684 break;
2685 }
2686
2687 return sprintf(buf, "Vulnerable\n");
2688 }
2689
cpu_show_meltdown(struct device * dev,struct device_attribute * attr,char * buf)2690 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
2691 {
2692 return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
2693 }
2694
cpu_show_spectre_v1(struct device * dev,struct device_attribute * attr,char * buf)2695 ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
2696 {
2697 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
2698 }
2699
cpu_show_spectre_v2(struct device * dev,struct device_attribute * attr,char * buf)2700 ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
2701 {
2702 return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
2703 }
2704
cpu_show_spec_store_bypass(struct device * dev,struct device_attribute * attr,char * buf)2705 ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
2706 {
2707 return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
2708 }
2709
cpu_show_l1tf(struct device * dev,struct device_attribute * attr,char * buf)2710 ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf)
2711 {
2712 return cpu_show_common(dev, attr, buf, X86_BUG_L1TF);
2713 }
2714
cpu_show_mds(struct device * dev,struct device_attribute * attr,char * buf)2715 ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf)
2716 {
2717 return cpu_show_common(dev, attr, buf, X86_BUG_MDS);
2718 }
2719
cpu_show_tsx_async_abort(struct device * dev,struct device_attribute * attr,char * buf)2720 ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf)
2721 {
2722 return cpu_show_common(dev, attr, buf, X86_BUG_TAA);
2723 }
2724
cpu_show_itlb_multihit(struct device * dev,struct device_attribute * attr,char * buf)2725 ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf)
2726 {
2727 return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT);
2728 }
2729
cpu_show_srbds(struct device * dev,struct device_attribute * attr,char * buf)2730 ssize_t cpu_show_srbds(struct device *dev, struct device_attribute *attr, char *buf)
2731 {
2732 return cpu_show_common(dev, attr, buf, X86_BUG_SRBDS);
2733 }
2734
cpu_show_mmio_stale_data(struct device * dev,struct device_attribute * attr,char * buf)2735 ssize_t cpu_show_mmio_stale_data(struct device *dev, struct device_attribute *attr, char *buf)
2736 {
2737 if (boot_cpu_has_bug(X86_BUG_MMIO_UNKNOWN))
2738 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_UNKNOWN);
2739 else
2740 return cpu_show_common(dev, attr, buf, X86_BUG_MMIO_STALE_DATA);
2741 }
2742
cpu_show_retbleed(struct device * dev,struct device_attribute * attr,char * buf)2743 ssize_t cpu_show_retbleed(struct device *dev, struct device_attribute *attr, char *buf)
2744 {
2745 return cpu_show_common(dev, attr, buf, X86_BUG_RETBLEED);
2746 }
2747
cpu_show_gds(struct device * dev,struct device_attribute * attr,char * buf)2748 ssize_t cpu_show_gds(struct device *dev, struct device_attribute *attr, char *buf)
2749 {
2750 return cpu_show_common(dev, attr, buf, X86_BUG_GDS);
2751 }
2752
cpu_show_spec_rstack_overflow(struct device * dev,struct device_attribute * attr,char * buf)2753 ssize_t cpu_show_spec_rstack_overflow(struct device *dev, struct device_attribute *attr, char *buf)
2754 {
2755 return cpu_show_common(dev, attr, buf, X86_BUG_SRSO);
2756 }
2757 #endif
2758