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/Documentation/devicetree/bindings/soundwire/
Dsoundwire-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soundwire/soundwire-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 - Vinod Koul <vkoul@kernel.org>
14 SoundWire busses can be described with a node for the SoundWire controller
15 device and a set of child nodes for each SoundWire slave on the bus.
21 "#address-cells":
24 "#size-cells":
[all …]
/Documentation/devicetree/bindings/mfd/
Dkontron,sl28cpld.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Walle <michael@walle.cc>
14 watchdog, fan monitoring, PWM controller, interrupt controller and a
26 "#address-cells":
29 "#size-cells":
30 const: 0
32 "#interrupt-cells":
38 interrupt-controller: true
[all …]
Dgateworks-gsc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/gateworks-gsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The Gateworks System Controller (GSC) is a device present across various
11 Gateworks product families that provides a set of system related features
14 - Watchdog Timer
15 - GPIO
16 - Pushbutton controller
17 - Hardware monitor with ADC's for temperature and voltage rails and
[all …]
/Documentation/trace/postprocess/
Ddecode_msr.py3 # decode_msr msr-index.h < trace
9 with open(sys.argv[1] if len(sys.argv) > 1 else "msr-index.h", "r") as f:
10 for j in f:
11 m = re.match(r'#define (MSR_\w+)\s+(0x[0-9a-fA-F]+)', j)
16 ( "MSR_LASTBRANCH_%d_FROM_IP", 0x680, 0x69F ),
17 ( "MSR_LASTBRANCH_%d_TO_IP", 0x6C0, 0x6DF ),
18 ( "LBR_INFO_%d", 0xdc0, 0xddf ),
22 m = re.search(r'(read|write)_msr:\s+([0-9a-f]+)', j)
31 r = er[0] % (num - er[1],)
Dtrace-vmscan-postprocess.pl2 # This is a POC for reading the text representation of trace output related to
3 # page reclaim. It makes an attempt to extract some high-level information on
6 # Example usage: trace-vmscan-postprocess.pl < /sys/kernel/debug/tracing/trace_pipe
8 # --read-procstat If the trace lacks process info, get it from /proc
9 # --ignore-pid Aggregate processes of the same name together
25 use constant MM_VMSCAN_WRITEPAGE_ANON_SYNC => 9;
31 # Per-order events
43 # High-level events extrapolated from tracepoints
77 my $sigint_report = 0;
78 my $sigint_exit = 0;
[all …]
/Documentation/ABI/stable/
Dsysfs-class-tpm4 Contact: linux-integrity@vger.kernel.org
5 Description: The device/ directory under a specific TPM instance exposes
12 Contact: linux-integrity@vger.kernel.org
13 Description: The "active" property prints a '1' if the TPM chip is accepting
16 visible to the OS, but will only accept a restricted set of
24 Contact: linux-integrity@vger.kernel.org
32 Contact: linux-integrity@vger.kernel.org
37 Manufacturer: 0x53544d20
41 Manufacturer is a hex dump of the 4 byte manufacturer info
42 space in a TPM. TCG version shows the TCG TPM spec level that
[all …]
/Documentation/devicetree/bindings/soc/qcom/
Dqcom,geni-se.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Mukesh Savaliya <msavaliy@codeaurora.org>
11 - Akash Asthana <akashast@codeaurora.org>
15 is a programmable module for supporting a wide range of serial interfaces
16 like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
18 Wrapper controller is modeled as a node with zero or more child nodes each
19 representing a serial engine.
[all …]
/Documentation/devicetree/bindings/bus/
Dallwinner,sun50i-a64-de2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/bus/allwinner,sun50i-a64-de2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
15 pattern: "^bus(@[0-9a-f]+)?$"
17 "#address-cells":
20 "#size-cells":
25 - const: allwinner,sun50i-a64-de2
[all …]
Dsocionext,uniphier-system-bus.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The UniPhier System Bus is an external bus that connects on-board devices to
11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
16 within each bank to the CPU-viewed address. The needed setup includes the
21 - Masahiro Yamada <yamada.masahiro@socionext.com>
25 const: socionext,uniphier-system-bus
30 "#address-cells":
[all …]
/Documentation/devicetree/bindings/iio/adc/
Dqcom,spmi-vadc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,spmi-vadc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
15 voltage. The VADC is a 15-bit sigma-delta ADC.
17 voltage. The VADC is a 16-bit sigma-delta ADC.
22 - items:
23 - const: qcom,pms405-adc
[all …]
/Documentation/userspace-api/ioctl/
Dioctl-number.rst21 system calls 'write' and 'read'. For example, a SET_FOO ioctl would
23 a GET_FOO ioctl would be _IOR, although the kernel would actually write
28 many drivers share a partial letter with other drivers.
30 If you are writing a driver for a new device and need a letter, pick an
33 patch to Linus Torvalds. Or you can e-mail me at <mec@shout.net> and
36 The second argument to _IO, _IOW, _IOR, or _IOWR is a sequence number
50 if a program calls an ioctl on the wrong device, it will get an
67 no attempt to list non-X86 architectures or ioctls from drivers/staging/.
73 0x00 00-1F linux/fs.h conflict!
74 0x00 00-1F scsi/scsi_ioctl.h conflict!
[all …]
/Documentation/devicetree/bindings/nvmem/
Dnvmem.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
16 On a significant proportion of boards, the manufacturer has stored
24 pattern: "^(eeprom|efuse|nvram)(@.*|-[0-9a-f])*$"
26 "#address-cells":
29 "#size-cells":
32 read-only:
37 wp-gpios:
[all …]
/Documentation/devicetree/bindings/gpio/
Dmrvl-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpio/mrvl-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
12 - Rob Herring <robh+dt@kernel.org>
15 - if:
20 - intel,pxa25x-gpio
21 - intel,pxa26x-gpio
[all …]
Dsnps,dw-apb-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Synopsys DesignWare GPIO controllers have a configurable number of ports,
12 GPIO-controller properties as desribed in this bindings file.
15 - Hoan Tran <hoan@os.amperecomputing.com>
16 - Serge Semin <fancer.lancer@gmail.com>
20 pattern: "^gpio@[0-9a-f]+$"
23 const: snps,dw-apb-gpio
[all …]
Dxylon,logicvc-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/gpio/xylon,logicvc-gpio.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
15 controller. These are meant to be used for controlling display-related
20 - GPIO[4:0] (display control) mapped to index 0-4
21 - EN_BLIGHT (power control) mapped to index 5
22 - EN_VDD (power control) mapped to index 6
23 - EN_VEE (power control) mapped to index 7
[all …]
/Documentation/devicetree/bindings/net/
Dnxp,tja11xx.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 "^ethernet-phy@[0-9a-f]+$":
29 minimum: 0
35 - reg
[all …]
/Documentation/vm/
Dzsmalloc.rst11 (0-order) pages, it would suffer from very high fragmentation --
15 To overcome these issues, zsmalloc allocates a bunch of 0-order pages
17 pages act as a single higher-order page i.e. an object can span 0-order
18 page boundaries. The code refers to these linked pages as a single entity
23 worst case, page is incompressible and is thus stored "as-is" i.e. in
27 Additionally, zs_malloc() does not return a dereferenceable pointer.
31 issues on 32-bit systems where the VA region for kernel space mappings
33 be mapped using zs_map_object() to get a usable pointer and subsequently
40 ``/sys/kernel/debug/zsmalloc/<user name>``. Here is a sample of stat output::
47 9 176 0 1 186 129 8 4
[all …]
/Documentation/devicetree/bindings/leds/
Dleds-lp50xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-lp50xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dan Murphy <dmurphy@ti.com>
13 The LP50XX is multi-channel, I2C RGB LED Drivers that can group RGB LEDs into
14 a LED group or control them individually.
27 - ti,lp5009
28 - ti,lp5012
29 - ti,lp5018
[all …]
Dleds-class-multicolor.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-class-multicolor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dan Murphy <dmurphy@ti.com>
14 either integrated multi-color LED elements (like RGB, RGBW, RGBWA-UV
15 etc.) or standalone LEDs, to achieve logically grouped multi-color LED
16 modules. This is achieved by adding multi-led nodes layer to the
23 "^multi-led@([0-9a-f])$":
32 enum: [ 8, 9 ]
[all …]
/Documentation/devicetree/bindings/pwm/
Dpwm.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
14 pattern: "^pwm(@.*|-[0-9a-f])*$"
16 "#pwm-cells":
18 Number of cells in a PWM specifier.
21 - "#pwm-cells"
26 - |
28 compatible = "nvidia,tegra20-pwm";
[all …]
/Documentation/devicetree/bindings/regulator/
Dmaxim,max77826.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Iskren Chernev <iskren.chernev@gmail.com>
14 pattern: "pmic@[0-9a-f]{1,2}"
17 - maxim,max77826
27 after their hardware counterparts LDO[1-15], BUCK and BUCKBOOST
30 "^LDO([1-9]|1[0-5])$":
41 - compatible
42 - reg
[all …]
/Documentation/devicetree/bindings/watchdog/
Dwatchdog.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guenter Roeck <linux@roeck-us.net>
11 - Wim Van Sebroeck <wim@linux-watchdog.org>
15 describe watchdog devices in a device tree.
19 pattern: "^watchdog(@.*|-[0-9a-f])?$"
21 timeout-sec:
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
Dpincfg.txt4 - pio-map : array of pin configurations. Each pin is defined by 6
7 - port : port number of the pin; 0-6 represent port A-G in UM.
8 - pin : pin number in the port.
9 - dir : direction of the pin, should encode as follows:
11 0 = The pin is disabled
16 - open_drain : indicates the pin is normal or wired-OR:
18 0 = The pin is actively driven as an output
19 1 = The pin is an open-drain driver. As an output, the pin is
20 driven active-low, otherwise it is three-stated.
22 - assignment : function number of the pin according to the Pin Assignment
[all …]
/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra186-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
16 handles memory requests for 40-bit virtual addresses from internal clients
27 pattern: "^memory-controller@[0-9a-f]+$"
31 - enum:
[all …]
/Documentation/devicetree/bindings/sound/
Dnvidia,tegra210-admaif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-admaif.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^admaif@[0-9a-f]*$"
26 - enum:
27 - nvidia,tegra210-admaif
28 - nvidia,tegra186-admaif
[all …]

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