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/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra124-emc.yaml38 "^emc-timings-[0-9]+$":
48 "^timing-[0-9]+$":
79 minimum: 0
142 minimum: 0
340 reg = <0x70019000 0x1000>;
352 reg = <0x7001b000 0x1000>;
358 emc-timings-0 {
361 timing-0 {
364 nvidia,emc-auto-cal-config = <0xa1430000>;
365 nvidia,emc-auto-cal-config2 = <0x00000000>;
[all …]
Dnvidia,tegra30-emc.yaml40 "^emc-timings-[0-9]+$":
49 "^timing-[0-9]+$":
62 minimum: 0
78 Mode Register 0.
85 minimum: 0
224 reg = <0x7000f400 0x400>;
225 interrupts = <0 78 4>;
236 nvidia,emc-auto-cal-interval = <0x001fffff>;
237 nvidia,emc-mode-1 = <0x80100002>;
238 nvidia,emc-mode-2 = <0x80200018>;
[all …]
/Documentation/devicetree/bindings/pci/
Dxilinx-nwl-pcie.txt34 address. The value must be 0.
48 interrupts = <0 114 4>, <0 115 4>, <0 116 4>, <0 117 4>, <0 118 4>;
50 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
51 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
52 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
53 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
54 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
57 reg = <0x0 0xfd0e0000 0x0 0x1000>,
58 <0x0 0xfd480000 0x0 0x1000>,
59 <0x80 0x00000000 0x0 0x1000000>;
[all …]
Dxgene-pci.txt35 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
36 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
38 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
39 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
40 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
41 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
42 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
43 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
44 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
45 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
[all …]
Dxgene-pci-msi.txt8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
Daltera-pcie.txt31 reg = <0xc0000000 0x20000000>,
32 <0xff220000 0x00004000>;
35 interrupts = <0 40 4>;
38 bus-range = <0x0 0xFF>;
43 interrupt-map-mask = <0 0 0 7>;
44 interrupt-map = <0 0 0 1 &pcie_0 1>,
45 <0 0 0 2 &pcie_0 2>,
46 <0 0 0 3 &pcie_0 3>,
47 <0 0 0 4 &pcie_0 4>;
48 ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
[all …]
Dfaraday,ftpci100.txt9 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
10 Technology) and product ID 0x4321.
23 - bus-range: set to <0x00 0xff>
45 - #address-cells: set to <0>
64 interrupt-map-mask = <0xf800 0 0 7>;
66 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
67 <0x4800 0 0 2 &pci_intc 1>,
68 <0x4800 0 0 3 &pci_intc 2>,
69 <0x4800 0 0 4 &pci_intc 3>,
70 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
[all …]
Dhisilicon-pcie.txt17 - port-id: Should be 0, 1, 2 or 3.
26 reg = <0 0xb0080000 0 0x10000>, <0x220 0x00000000 0 0x2000>;
28 bus-range = <0 15>;
34 ranges = <0x82000000 0 0x00000000 0x220 0x00000000 0 0x10000000>;
38 interrupt-map-mask = <0xf800 0 0 7>;
39 interrupt-map = <0x0 0 0 1 &mbigen_pcie 1 10
40 0x0 0 0 2 &mbigen_pcie 2 11
41 0x0 0 0 3 &mbigen_pcie 3 12
42 0x0 0 0 4 &mbigen_pcie 4 13>;
Dxilinx-versal-cpm.yaml47 const: 0
79 interrupts = <0 72 4>;
81 interrupt-map-mask = <0 0 0 7>;
82 interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
83 <0 0 0 2 &pcie_intc_0 1>,
84 <0 0 0 3 &pcie_intc_0 2>,
85 <0 0 0 4 &pcie_intc_0 3>;
86 bus-range = <0x00 0xff>;
87 ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
88 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
[all …]
Drcar-pci.txt55 reg = <0 0xfe000000 0 0x80000>;
58 bus-range = <0x00 0xff>;
60 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
61 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
62 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
63 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
64 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000
65 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
66 interrupts = <0 116 4>, <0 117 4>, <0 118 4>;
68 interrupt-map-mask = <0 0 0 0>;
[all …]
Dbrcm,stb-pcie.yaml123 reg = <0x0 0x7d500000 0x9310>;
131 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
132 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
135 ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 0x0 0x04000000>;
136 dma-ranges = <0x42000000 0x1 0x00000000 0x0 0x40000000 0x0 0x80000000>,
137 <0x42000000 0x1 0x80000000 0x3 0x00000000 0x0 0x80000000>;
139 brcm,scb-sizes = <0x0000000080000000 0x0000000080000000>;
Dmobiveil-pcie.txt49 reg = <0xa0000000 0x00001000>,
50 <0xb0000000 0x00010000>,
51 <0xff000000 0x00200000>,
52 <0xb0010000 0x00001000>;
60 bus-range = <0x00000000 0x000000ff>;
64 interrupts = < 0 89 4 >;
65 interrupt-map-mask = <0 0 0 7>;
66 interrupt-map = <0 0 0 0 &pci_express 0>,
67 <0 0 0 1 &pci_express 1>,
68 <0 0 0 2 &pci_express 2>,
[all …]
Dlayerscape-pci.txt36 The second entry must be '0' or '1' based on physical PCIe controller index.
46 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
47 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
51 fsl,pcie-scfg = <&scfg 0>;
57 bus-range = <0x0 0xff>;
58 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
59 0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000 /* prefetchable memory */
60 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
62 interrupt-map-mask = <0 0 0 7>;
63 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/Documentation/devicetree/bindings/usb/
Ddwc3-cavium.txt14 reg = <0x00011800 0x69000000 0x00000000 0x00000100>;
16 #address-cells = <0x00000002>;
17 #size-cells = <0x00000002>;
18 refclk-frequency = <0x05f5e100>;
21 power = <0x00000002 0x00000002 0x00000001>;
24 reg = <0x00016900 0x00000000 0x00000010 0x00000000>;
25 interrupt-parent = <0x00000010>;
26 interrupts = <0x00000009 0x00000004>;
/Documentation/devicetree/bindings/mtd/
Dpartition.txt71 flash@0 {
77 partition@0 {
79 reg = <0x0000000 0x100000>;
84 reg = <0x0100000 0x200000>;
96 partition@0 {
98 reg = <0x00000000 0x1 0x00000000>;
110 partition@0 {
112 reg = <0x0 0x00000000 0x2 0x00000000>;
118 reg = <0x2 0x00000000 0x1 0x00000000>;
129 partition@0 {
[all …]
Dibm,ndfc.txt5 - reg : should specify chip select and size used for the chip (0x2000).
8 - ccr : NDFC config and control register value (default 0).
9 - bank-settings : NDFC bank configuration register value (default 0).
16 ndfc@1,0 {
18 reg = <0x00000001 0x00000000 0x00002000>;
19 ccr = <0x00001000>;
20 bank-settings = <0x80002222>;
28 partition@0 {
30 reg = <0x00000000 0x00200000>;
34 reg = <0x00200000 0x03E00000>;
Dti,am654-hbmc.txt23 reg = <0x0 0x47000000 0x0 0x100>;
31 mux-reg-masks = <0x4 0x2>; /* 0: reg 0x4, bit 1 */
37 reg = <0x0 0x47034000 0x0 0x100>,
38 <0x5 0x00000000 0x1 0x0000000>;
42 ranges = <0x0 0x0 0x5 0x00000000 0x4000000>, /* CS0 - 64MB */
43 <0x1 0x0 0x5 0x04000000 0x4000000>; /* CS1 - 64MB */
44 mux-controls = <&hbmc_mux 0>;
47 flash@0,0 {
49 reg = <0x0 0x0 0x4000000>;
/Documentation/devicetree/bindings/
Dnuma.txt29 /* numa node 0 */
30 numa-node-id = <0>;
65 0_______20______1
76 0 -> 1 = 20
79 3 -> 0 = 20
80 0 -> 2 = 40
87 distance-matrix = <0 0 10>,
88 <0 1 20>,
89 <0 2 40>,
90 <0 3 20>,
[all …]
/Documentation/devicetree/bindings/bus/
Dsocionext,uniphier-system-bus.yaml45 implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
46 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
53 bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
55 bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
61 "^.*@[1-5],[1-9a-f][0-9a-f]+$":
77 // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
78 // mapped to 0x43f00000 of the parent bus.
79 // - the UART device is connected at the offset 0x00200000 of CS5 and
80 // mapped to 0x46200000 of the parent bus.
84 reg = <0x58c00000 0x400>;
[all …]
Dbrcm,bus-axi.txt26 reg = <0x18000000 0x1000>;
27 ranges = <0x00000000 0x18000000 0x00100000>;
31 interrupt-map-mask = <0x000fffff 0xffff>;
33 /* Ethernet Controller 0 */
34 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
37 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
39 /* PCIe Controller 0 */
40 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
41 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
42 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
[all …]
Dimx-weim.txt25 <cs-number> 0 <physical address of mapping> <size>
32 register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
36 IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
38 05 128M 0M 0M 0M
39 033 64M 64M 0M 0M
40 0113 64M 32M 32M 0M
44 what bootloader sets up in IOMUXC_GPR1[11:0] will be
70 reg = <0x021b8000 0x4000>;
74 ranges = <0 0 0x08000000 0x08000000>;
77 nor@0,0 {
[all …]
Darm,integrator-ap-lm.yaml15 determine if a logic module is connected at index 0, 1, 2 or 3. The logic
35 "^bus(@[0-9a-f]*)?$":
37 and are named with bus. The first module is at 0xc0000000, the second
38 at 0xd0000000 and so on until the top of the memory of the system at
39 0xffffffff. All information about the memory used by the module is
55 ranges = <0xc0000000 0xc0000000 0x40000000>;
60 ranges = <0x00000000 0xc0000000 0x10000000>;
61 /* The Logic Modules sees the Core Module 0 RAM @80000000 */
62 dma-ranges = <0x00000000 0x80000000 0x10000000>;
68 reg = <0x00100000 0x1000>;
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Dloongson,liointc.yaml53 interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
54 and each bit in the cell refers to a child interrupt from 0 to 31.
76 reg = <0x3ff01400 0x64>;
85 loongson,parent_int_map = <0xf0ffffff>, /* int0 */
86 <0x0f000000>, /* int1 */
87 <0x00000000>, /* int2 */
88 <0x00000000>; /* int3 */
/Documentation/arm/sa1100/
Dassabet.rst91 load zImage -r -b 0x100000
95 load -m ymodem -r -b 0x100000
99 fis create "Linux kernel" -b 0x100000 -l 0xc0000
108 load ramdisk_image.gz -r -b 0x800000
119 exec -b 0x100000 -l 0xc0000
140 load sample_img.jffs2 -r -b 0x100000
144 RedBoot> load sample_img.jffs2 -r -b 0x100000
145 Raw file loaded 0x00100000-0x00377424
154 0x500E0000 .. 0x503C0000
162 size of unallocated flash: 0x503c0000 - 0x500e0000 = 0x2e0000
[all …]
/Documentation/devicetree/bindings/perf/
Darm-ccn.txt21 reg = <0x20 0x00000000 0 0x1000000>;
22 interrupts = <0 181 4>;

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