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/Documentation/devicetree/bindings/pci/
Dlayerscape-pci.txt36 The second entry must be '0' or '1' based on physical PCIe controller index.
46 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
47 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
51 fsl,pcie-scfg = <&scfg 0>;
57 bus-range = <0x0 0xff>;
58 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
59 0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000 /* prefetchable memory */
60 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
62 interrupt-map-mask = <0 0 0 7>;
63 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
[all …]
Dxgene-pci.txt35 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
36 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
38 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
39 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
40 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
41 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
42 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
43 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
44 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
45 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
[all …]
Dxgene-pci-msi.txt8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
Dpcie-al.txt33 reg = <0x0 0xfb600000 0x0 0x00100000
34 0x0 0xfd800000 0x0 0x00010000
35 0x0 0xfd810000 0x0 0x00001000>;
37 bus-range = <0 255>;
43 interrupt-map-mask = <0x00 0 0 7>;
44 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; /* INTa */
45 ranges = <0x02000000 0x0 0xc0010000 0x0 0xc0010000 0x0 0x07ff0000>;
Dbrcm,iproc-pcie.txt77 reg = <0x18012000 0x1000>;
80 interrupt-map-mask = <0 0 0 0>;
81 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
83 linux,pci-domain = <0>;
85 bus-range = <0x00 0xff>;
90 ranges = <0x81000000 0 0 0x28000000 0 0x00010000
91 0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
93 phys = <&phy 0 5>;
97 brcm,pcie-ob-axi-offset = <0x00000000>;
115 reg = <0x18013000 0x1000>;
[all …]
Dsamsung,exynos5440-pcie.txt27 reg = <0x270000 0x1000>, <0x271000 0x40>;
34 reg = <0x290000 0x1000>, <0x40000000 0x1000>;
42 ranges = <0x81000000 0 0 0x60001000 0 0x00010000
43 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
45 interrupt-map-mask = <0 0 0 0>;
46 interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
53 reset-gpio = <&pin_ctrl 5 0>;
57 reset-gpio = <&pin_ctrl 22 0>;
Daxis,artpec6-pcie.txt28 reg = <0xf8050000 0x2000
29 0xf8040000 0x1000
30 0xc0000000 0x2000>;
36 ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
38 0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
40 bus-range = <0x00 0xff>;
44 interrupt-map-mask = <0 0 0 0x7>;
45 interrupt-map = <0 0 0 1 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
46 <0 0 0 2 &intc GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
47 <0 0 0 3 &intc GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
[all …]
Dversatile.yaml38 - const: 0x1800
39 - const: 0
40 - const: 0
58 reg = <0x10001000 0x1000>,
59 <0x41000000 0x10000>,
60 <0x42000000 0x100000>;
61 bus-range = <0 0xff>;
67 <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */
68 <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */
69 <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
[all …]
Dmobiveil-pcie.txt49 reg = <0xa0000000 0x00001000>,
50 <0xb0000000 0x00010000>,
51 <0xff000000 0x00200000>,
52 <0xb0010000 0x00001000>;
60 bus-range = <0x00000000 0x000000ff>;
64 interrupts = < 0 89 4 >;
65 interrupt-map-mask = <0 0 0 7>;
66 interrupt-map = <0 0 0 0 &pci_express 0>,
67 <0 0 0 1 &pci_express 1>,
68 <0 0 0 2 &pci_express 2>,
[all …]
Dhisilicon-histb-pcie.txt38 - phys: List of phandle and phy mode specifier, should be 0.
44 reg = <0xf9860000 0x1000>,
45 <0xf0000000 0x2000>,
46 <0xf2000000 0x01000000>;
51 bus-range = <0 15>;
53 ranges=<0x81000000 0 0 0xf4000000 0 0x00010000
54 0x82000000 0 0xf3000000 0xf3000000 0 0x01000000>;
58 interrupt-map-mask = <0 0 0 0>;
59 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
65 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
Duniphier-pcie.txt52 reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
53 <0x2fff0000 0x10000>;
60 bus-range = <0x0 0xff>;
64 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000
66 0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;
69 interrupts = <0 224 4>, <0 225 4>;
70 interrupt-map-mask = <0 0 0 7>;
71 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
72 <0 0 0 2 &pcie_intc 1>, /* INTB */
73 <0 0 0 3 &pcie_intc 2>, /* INTC */
[all …]
Ddesignware-pcie.txt46 0x00-0xff is assumed if not present)
55 reg = <0xdfc00000 0x0001000>, /* IP registers */
56 <0xd0000000 0x0002000>; /* Configuration space */
61 ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000
62 0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
70 reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
71 <0xdfc01000 0x0001000>, /* IP registers 2 */
72 <0xd0000000 0x2000000>; /* Configuration space */
Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
Dfsl,imx6q-pcie.txt22 - fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0
23 - fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0
67 reg = <0x01ffc000 0x04000>,
68 <0x01f00000 0x80000>;
73 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000
74 0x81000000 0 0 0x01f80000 0 0x00010000
75 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
80 interrupt-map-mask = <0 0 0 0x7>;
81 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
82 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
[all …]
Dti-pci.txt74 ranges = <0x51000000 0x51000000 0x3000
75 0x0 0x20000000 0x10000000>;
78 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
80 interrupts = <0 232 0x4>, <0 233 0x4>;
84 ranges = <0x81000000 0 0 0x03000 0 0x00010000
85 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
91 interrupt-map-mask = <0 0 0 7>;
92 interrupt-map = <0 0 0 1 &pcie_intc 1>,
93 <0 0 0 2 &pcie_intc 2>,
94 <0 0 0 3 &pcie_intc 3>,
[all …]
Dralink,rt3883-pci.txt38 address. The value must be 0. As such, 'interrupt-map' nodes do not
53 address. The value must be 0.
105 reg = <0x10140000 0x20000>;
114 #address-cells = <0>;
128 bus-range = <0 255>;
130 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
131 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
134 interrupt-map-mask = <0xf800 0 0 7>;
137 0x8800 0 0 1 &pciintc 18
138 0x8800 0 0 2 &pciintc 18
[all …]
/Documentation/devicetree/bindings/hwlock/
Dsirf,hwspinlock.txt19 reg = <0x13240000 0x00010000>;
/Documentation/devicetree/bindings/phy/
Dbrcm,stingray-usb-phy.txt10 the PHY number of two PHYs. 0 for HS PHY and 1 for SS PHY.
11 - Must be 0 for brcm,sr-usb-hs-phy.
16 usbphy0: usb-phy@0 {
18 reg = <0x00000000 0x100>;
24 reg = <0x00010000 0x100>,
30 reg = <0x00020000 0x100>,
31 #phy-cells = <0>;
/Documentation/firmware-guide/acpi/
Ddebug.rst41 ACPI_UTILITIES 0x00000001
42 ACPI_HARDWARE 0x00000002
43 ACPI_EVENTS 0x00000004
44 ACPI_TABLES 0x00000008
45 ACPI_NAMESPACE 0x00000010
46 ACPI_PARSER 0x00000020
47 ACPI_DISPATCHER 0x00000040
48 ACPI_EXECUTER 0x00000080
49 ACPI_RESOURCES 0x00000100
50 ACPI_CA_DEBUGGER 0x00000200
[all …]
/Documentation/devicetree/bindings/gpio/
Dgpio-samsung.txt18 - Pin number: is a value between 0 to 7.
19 - Flags and Pull Up/Down: 0 - Pull Up/Down Disabled.
22 Bit 16 (0x00010000) - Input is active low.
23 - Drive Strength: 0 - 1x,
38 reg = <0x11400000 0x20>;
/Documentation/devicetree/bindings/powerpc/fsl/
Dlbc.txt19 reg = <0xf0010100 0x40>;
21 ranges = <0x0 0x0 0xfe000000 0x02000000
22 0x1 0x0 0xf4500000 0x00008000
23 0x2 0x0 0xfd810000 0x00010000>;
25 flash@0,0 {
27 reg = <0x0 0x0 0x2000000>;
32 board-control@1,0 {
33 reg = <0x1 0x0 0x20>;
37 simple-periph@2,0 {
39 reg = <0x2 0x0 0x10000>;
[all …]
/Documentation/devicetree/bindings/edac/
Damazon,al-mc-edac.yaml63 reg = <0x0 0xf0080000 0x0 0x00010000>;
/Documentation/devicetree/bindings/memory-controllers/fsl/
Difc.txt37 reg = <0x0 0xffe1e000 0 0x2000>;
42 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
43 0x1 0x0 0x0 0xffa00000 0x00010000
44 0x3 0x0 0x0 0xffb00000 0x00020000>;
46 flash@0,0 {
50 reg = <0x0 0x0 0x2000000>;
54 partition@0 {
56 reg = <0x0 0x02000000>;
61 flash@1,0 {
65 reg = <0x1 0x0 0x10000>;
[all …]
/Documentation/devicetree/bindings/thermal/
Dqoriq-thermal.yaml16 Register (IPBRR0) at offset 0x0BF8.
20 0x01900102 T1040
78 reg = <0xf0000 0x1000>;
79 interrupts = <18 2 0 0>;
80 fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
81 fsl,tmu-calibration = <0x00000000 0x00000025>,
82 <0x00000001 0x00000028>,
83 <0x00000002 0x0000002d>,
84 <0x00000003 0x00000031>,
85 <0x00000004 0x00000036>,
[all …]
/Documentation/devicetree/bindings/powerpc/opal/
Dpower-mgt.txt44 0x00000001 /* Decrementer would stop */
45 0x00000002 /* Needs timebase restore */
46 0x00001000 /* Restore GPRs like nap */
47 0x00002000 /* Restore hypervisor resource from PACA pointer */
48 0x00004000 /* Program PORE to restore PACA pointer */
49 0x00010000 /* This is a nap state (POWER7,POWER8) */
50 0x00020000 /* This is a fast-sleep state (POWER8)*/
51 0x00040000 /* This is a winkle state (POWER8) */
52 0x00080000 /* This is a fast-sleep state which requires a */
55 0x00800000 /* This state uses SPR PMICR instruction */
[all …]

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