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/Documentation/devicetree/bindings/gpu/
Dnvidia,gk20a.txt46 reg = <0x0 0x57000000 0x0 0x01000000>,
47 <0x0 0x58000000 0x0 0x01000000>;
64 reg = <0x0 0x57000000 0x0 0x01000000>,
65 <0x0 0x58000000 0x0 0x01000000>;
82 reg = <0x0 0x17000000 0x0 0x1000000>,
83 <0x0 0x18000000 0x0 0x1000000>;
100 reg = <0x17000000 0x10000000>,
101 <0x18000000 0x10000000>;
Daspeed-gfx.txt28 reg = <0x1e6e6000 0x1000>;
32 interrupts = <0x19>;
37 size = <0x01000000>;
38 alignment = <0x01000000>;
/Documentation/devicetree/bindings/pci/
Dcdns,cdns-pcie-host.yaml47 bus-range = <0x0 0xff>;
48 linux,pci-domain = <0>;
49 vendor-id = <0x17cd>;
50 device-id = <0x0200>;
52 reg = <0x0 0xfb000000 0x0 0x01000000>,
53 <0x0 0x41000000 0x0 0x00001000>;
56 ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
57 <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
58 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
60 #interrupt-cells = <0x1>;
[all …]
Dv3-v360epc-pci.txt18 each be exactly 256MB (0x10000000) in size.
38 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
42 bus-range = <0x00 0xff>;
43 ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
44 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
45 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
46 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
47 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
48 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
49 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
[all …]
Dhisilicon-histb-pcie.txt38 - phys: List of phandle and phy mode specifier, should be 0.
44 reg = <0xf9860000 0x1000>,
45 <0xf0000000 0x2000>,
46 <0xf2000000 0x01000000>;
51 bus-range = <0 15>;
53 ranges=<0x81000000 0 0 0xf4000000 0 0x00010000
54 0x82000000 0 0xf3000000 0xf3000000 0 0x01000000>;
58 interrupt-map-mask = <0 0 0 0>;
59 interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
65 resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
Dhost-generic-pci.yaml94 property. If no "bus-range" is specified, this will be bus 0 (the
153 bus-range = <0x0 0x1>;
156 reg = <0x0 0x40000000 0x0 0x1000000>;
159 ranges = <0x01000000 0x0 0x01000000 0x0 0x01000000 0x0 0x00010000>,
160 <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x3f000000>;
162 #interrupt-cells = <0x1>;
165 interrupt-map = < 0x0 0x0 0x0 0x1 &gic 0x0 0x4 0x1>,
166 < 0x800 0x0 0x0 0x1 &gic 0x0 0x5 0x1>,
167 <0x1000 0x0 0x0 0x1 &gic 0x0 0x6 0x1>,
168 <0x1800 0x0 0x0 0x1 &gic 0x0 0x7 0x1>;
[all …]
Dfsl,imx6q-pcie.txt22 - fsl,tx-deemph-gen1: Gen1 De-emphasis value. Default: 0
23 - fsl,tx-deemph-gen2-3p5db: Gen2 (3.5db) De-emphasis value. Default: 0
67 reg = <0x01ffc000 0x04000>,
68 <0x01f00000 0x80000>;
73 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000
74 0x81000000 0 0 0x01f80000 0 0x00010000
75 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>;
80 interrupt-map-mask = <0 0 0 0x7>;
81 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
82 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
[all …]
Dcdns,cdns-pcie-ep.yaml42 reg = <0x0 0xfc000000 0x0 0x01000000>,
43 <0x0 0x80000000 0x0 0x40000000>;
Dloongson.yaml57 reg = <0x0 0x1a000000 0x0 0x2000000>;
60 ranges = <0x01000000 0x0 0x00004000 0x0 0x00004000 0x0 0x00004000>,
61 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
D83xx-512x-pci.txt12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
Dxgene-pci.txt35 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */
36 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */
38 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */
39 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */
40 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
41 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
42 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
43 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
44 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
45 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1
[all …]
Dversatile.yaml38 - const: 0x1800
39 - const: 0
40 - const: 0
58 reg = <0x10001000 0x1000>,
59 <0x41000000 0x10000>,
60 <0x42000000 0x100000>;
61 bus-range = <0 0xff>;
67 <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */
68 <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */
69 <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
[all …]
Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
Dxgene-pci-msi.txt8 - reg: physical base address (0x79000000) and length (0x900000) for controller
13 interrupt number 0x10 to 0x1f.
27 reg = <0x00 0x79000000 0x0 0x900000>;
28 interrupts = <0x0 0x10 0x4>
29 <0x0 0x11 0x4>
30 <0x0 0x12 0x4>
31 <0x0 0x13 0x4>
32 <0x0 0x14 0x4>
33 <0x0 0x15 0x4>
34 <0x0 0x16 0x4>
[all …]
Drcar-pci.txt55 reg = <0 0xfe000000 0 0x80000>;
58 bus-range = <0x00 0xff>;
60 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
61 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
62 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
63 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
64 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000
65 0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
66 interrupts = <0 116 4>, <0 117 4>, <0 118 4>;
68 interrupt-map-mask = <0 0 0 0>;
[all …]
Dti,j721e-pci-host.yaml48 const: 0x104c
51 const: 0xb00d
88 reg = <0x00 0x02900000 0x00 0x1000>,
89 <0x00 0x02907000 0x00 0x400>,
90 <0x00 0x0d000000 0x00 0x00800000>,
91 <0x00 0x10000000 0x00 0x00001000>;
102 bus-range = <0x0 0xf>;
103 vendor-id = <0x104c>;
104 device-id = <0xb00d>;
105 msi-map = <0x0 &gic_its 0x0 0x10000>;
[all …]
Dralink,rt3883-pci.txt38 address. The value must be 0. As such, 'interrupt-map' nodes do not
53 address. The value must be 0.
105 reg = <0x10140000 0x20000>;
114 #address-cells = <0>;
128 bus-range = <0 255>;
130 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
131 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
134 interrupt-map-mask = <0xf800 0 0 7>;
137 0x8800 0 0 1 &pciintc 18
138 0x8800 0 0 2 &pciintc 18
[all …]
/Documentation/devicetree/bindings/mtd/
Dintel,ixp4xx-flash.txt20 reg = <0x50000000 0x01000000>;
Dcortina,gemini-flash.txt21 reg = <0x30000000 0x01000000>;
/Documentation/firmware-guide/acpi/
Ddebug.rst41 ACPI_UTILITIES 0x00000001
42 ACPI_HARDWARE 0x00000002
43 ACPI_EVENTS 0x00000004
44 ACPI_TABLES 0x00000008
45 ACPI_NAMESPACE 0x00000010
46 ACPI_PARSER 0x00000020
47 ACPI_DISPATCHER 0x00000040
48 ACPI_EXECUTER 0x00000080
49 ACPI_RESOURCES 0x00000100
50 ACPI_CA_DEBUGGER 0x00000200
[all …]
/Documentation/devicetree/bindings/remoteproc/
Dst-rproc.txt29 reg = <0x42000000 0x01000000>;
40 st,syscfg = <&syscfg_core 0x228>;
/Documentation/devicetree/bindings/misc/
Difm-csi.txt22 csi@3,0 {
24 reg = <3 0 0x00100000>; /* CS 3, 1 MiB range */
28 gpios = <&gpio_simple 23 0 /* image_capture */
29 &gpio_simple 26 0 /* image_reset */
30 &gpio_simple 29 0>; /* image_master_en */
34 ifm,csi-wait-cycles = <0>;
40 ranges = <0 0 0xff000000 0x01000000
41 3 0 0xe3000000 0x00100000>;
/Documentation/devicetree/bindings/clock/
Dallwinner,sun8i-a83t-de2-clk.yaml66 reg = <0x01000000 0x100000>;
/Documentation/devicetree/bindings/bus/
Dsocionext,uniphier-system-bus.yaml45 implementation defined. Some SoCs can use 0x00000000-0x0fffffff and
46 0x40000000-0x4fffffff, while other SoCs only 0x40000000-0x4fffffff.
53 bank 0 to 0x42000000-0x43ffffff, bank 5 to 0x46000000-0x46ffffff
55 bank 0 to 0x48000000-0x49ffffff, bank 5 to 0x44000000-0x44ffffff
61 "^.*@[1-5],[1-9a-f][0-9a-f]+$":
77 // - the Ethernet device is connected at the offset 0x01f00000 of CS1 and
78 // mapped to 0x43f00000 of the parent bus.
79 // - the UART device is connected at the offset 0x00200000 of CS5 and
80 // mapped to 0x46200000 of the parent bus.
84 reg = <0x58c00000 0x400>;
[all …]
/Documentation/devicetree/bindings/pinctrl/
Dqcom,ipq6018-pinctrl.yaml61 - pattern: "^gpio([1-9]|[1-7][0-9]|80)$"
138 reg = <0x01000000 0x300000>;
144 gpio-ranges = <&tlmm 0 80>;

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