Home
last modified time | relevance | path

Searched +full:0 +full:x0f (Results 1 – 25 of 36) sorted by relevance

12

/Documentation/devicetree/bindings/ata/
Dahci-ceva.txt8 - ceva,p0-cominit-params: OOB timing value for COMINIT parameter for port 0.
16 - ceva,p0-comwake-params: OOB timing value for COMWAKE parameter for port 0.
24 - ceva,p0-burst-params: Burst timing value for COM parameter for port 0.
32 - ceva,p0-retry-params: Retry interval timing value for port 0.
45 reg = <0xfd0c0000 0x200>;
47 interrupts = <0 133 4>;
49 ceva,p0-cominit-params = /bits/ 8 <0x0F 0x25 0x18 0x29>;
50 ceva,p0-comwake-params = /bits/ 8 <0x04 0x0B 0x08 0x0F>;
51 ceva,p0-burst-params = /bits/ 8 <0x0A 0x08 0x4A 0x06>;
52 ceva,p0-retry-params = /bits/ 16 <0x0216 0x7F06>;
[all …]
/Documentation/input/devices/
Dcma3000_d0x.rst76 Input driver version is 1.0.0
77 Input device ID: bus 0x18 vendor 0x0 product 0x0 version 0x0
82 Event type 0 (Sync)
84 Event code 0 (X)
100 Value 0
101 Min 0
111 0: power down mode
132 X: (X & 0x70) * 100 ms (MDTMR)
133 (X & 0x0F) * 2.5 ms (FFTMR 400 Hz)
134 (X & 0x0F) * 10 ms (FFTMR 100 Hz)
[all …]
Datarikbd.rst32 is obtained by ORing 0x80 with the make code.
34 The special codes 0xF6 through 0xFF are reserved for use as follows:
39 0xF6 status report
40 0xF7 absolute mouse position record
41 0xF8-0xFB relative mouse position records (lsbs determined by
43 0xFC time-of-day
44 0xFD joystick report (both sticks)
45 0xFE joystick 0 event
46 0xFF joystick 1 event
114 LEFT=0x74 & RIGHT=0x75).
[all …]
/Documentation/devicetree/bindings/iio/adc/
Dqcom,pm8xxx-xoadc.txt15 0x197.
28 so legal values are 0x00, 0x01 or 0x02. The second cell
29 is the main analog mux setting (0x00..0x0f). The combination
33 - #size-cells: should be set to <0>
49 reg = <0x00 0x0c>;
53 reg = <0x00 0x0d>;
57 reg = <0x00 0x0f>;
62 1:1 ratio converters that sample 625, 1250 and 0 milliV and create
65 Optional subnodes: any channels other than channels [0x00 0x0c],
66 [0x00 0x0d] and [0x00 0x0f] are optional.
[all …]
Dst,stmpe-adc.yaml42 st,norequest-mask = <0x0F>; /* dont use ADC CH3-0 */
/Documentation/devicetree/bindings/iio/accel/
Dkionix,kxcjk1013.txt20 reg = <0x0F>;
21 mount-matrix = "0", "1", "0",
22 "1", "0", "0",
23 "0", "0", "1";
/Documentation/devicetree/bindings/sound/
Dcs42l73.txt12 - chgfreq : Charge Pump Frequency values 0x00-0x0F
19 reg = <0x4a>;
20 reset_gpio = <&gpio 10 0>;
21 chgfreq = <0x05>;
Dcs42l52.txt15 Allowable values of 0x00 through 0x0F. These are raw values written to the
30 0 = 0.5 x VA
41 reg = <0x4a>;
42 reset-gpio = <&gpio 10 0>;
43 cirrus,chgfreq-divisor = <0x05>;
Dcs42l56.txt18 Allowable values of 0x00 through 0x0F. These are raw values written to the
31 0 = 0.5 x VA
40 0 = Adapt to Volume Mode. Voltage level determined by the sum of the relevant volume settings.
47 0 = 1.8Hz
57 reg = <0x4b>;
58 cirrus,gpio-nreset = <&gpio 10 0>;
59 cirrus,chgfreq-divisor = <0x05>;
Dcs42l42.txt27 0 = (Default) Non-inverted
33 0 - 0ms,
45 0 - 0ms,
59 0ms - 200ms,
67 0ms - 20ms,
80 Each 0-63
89 reg = <0x48>;
96 reset-gpios = <&axi_gpio_0 1 0>;
100 cirrus,ts-inv = <0x00>;
101 cirrus,ts-dbnc-rise = <0x05>;
[all …]
/Documentation/devicetree/bindings/display/bridge/
Dtoshiba,tc358775.yaml28 description: i2c address of the bridge, 0x0f
57 const: 0
59 port@0:
76 - port@0
99 reg = <0x078b8000 0x500>;
102 #size-cells = <0>;
106 reg = <0x0f>;
116 #size-cells = <0>;
118 port@0 {
119 reg = <0>;
[all …]
Dtoshiba,tc358767.txt5 - reg: i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins
15 - toshiba,hpd-pin: TC358767 GPIO pin number to which HPD is connected to (0 or 1)
18 - port@0: DSI input port
28 reg = <0x68>;
36 #size-cells = <0>;
/Documentation/devicetree/bindings/iio/magnetometer/
Dak8974.txt26 reg = <0x0f>;
29 interrupts = <0 IRQ_TYPE_EDGE_RISING>,
/Documentation/devicetree/bindings/pci/
D83xx-512x-pci.txt12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
/Documentation/devicetree/bindings/soundwire/
Dqcom,sdw.txt83 Definition: should be 0 or 1 to indicate the block packing mode.
84 0 to indicate Blocks are per Channel
100 Definition: should be in range 0 to 7 to identify which data lane
110 for each port. Values between 0 and 15 are valid.
119 sub-frame for each port. Values between 0 and 15 are valid.
127 0 for reduced port
147 reg = <0xc85 0x20>;
152 qcom,dports-type = <0>;
155 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>;
156 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >;
[all …]
/Documentation/devicetree/bindings/media/i2c/
Dtc358743.txt18 - clock-lanes: should be <0>
32 reg = <0x0f>;
43 clock-lanes = <0>;
/Documentation/devicetree/bindings/iio/light/
Dsharp,gp2ap002.yaml72 #size-cells = <0>;
76 reg = <0x44>;
82 sharp,proximity-far-hysteresis = /bits/ 8 <0x2f>;
83 sharp,proximity-close-hysteresis = /bits/ 8 <0x0f>;
/Documentation/devicetree/bindings/leds/backlight/
Dlp855x.txt23 reg = <0x2c>;
25 dev-ctrl = /bits/ 8 <0x00>;
30 rom-addr = /bits/ 8 <0x14>;
31 rom-val = /bits/ 8 <0xcf>;
36 rom-addr = /bits/ 8 <0x15>;
37 rom-val = /bits/ 8 <0xc7>;
42 rom-addr = /bits/ 8 <0x19>;
43 rom-val = /bits/ 8 <0x0f>;
50 reg = <0x2c>;
53 dev-ctrl = /bits/ 8 <0x85>;
[all …]
/Documentation/devicetree/bindings/media/
Dqcom,msm8996-venus.yaml131 reg = <0x00c00000 0xff000>;
139 iommus = <&venus_smmu 0x00>,
140 <&venus_smmu 0x01>,
141 <&venus_smmu 0x0a>,
142 <&venus_smmu 0x07>,
143 <&venus_smmu 0x0e>,
144 <&venus_smmu 0x0f>,
145 <&venus_smmu 0x08>,
146 <&venus_smmu 0x09>,
147 <&venus_smmu 0x0b>,
[all …]
/Documentation/devicetree/bindings/input/touchscreen/
Dstmpe.txt9 0 -> 1 sample
14 0 -> 10 us
23 0 -> 10 us
32 (fraction-z ([0..7]) = Count of the fractional part)
34 0 -> 20 mA (typical 35mA max)
39 0 -> 36 clocks
47 0 -> 10bit ADC
50 0 -> internal
53 0 -> 1.625 MHz
68 pinctrl-0 = <&pinctrl_touch_int>;
[all …]
/Documentation/networking/
Dplip.rst126 Parallel Transfer Mode 0 Cable
193 PLIP Mode 0 transfer protocol
197 standard in Mode 0. That standard specifies the following protocol::
199 send header nibble '0x8'
207 <wait for rx. '0x1?'> <send 0x10+(octet&0x0F)>
208 <wait for rx. '0x0?'> <send 0x00+((octet>>4)&0x0F)>
210 To start a transfer the transmitting machine outputs a nibble 0x08.
217 (OUT is bit 0-4, OUT.j is bit j from OUT. IN likewise)
221 OUT := high nibble, OUT.4 := 0
222 WAIT FOR IN.4 = 0
/Documentation/userspace-api/media/v4l/
Dvidioc-g-enc-index.rst62 :header-rows: 0
63 :stub-columns: 0
89 :header-rows: 0
90 :stub-columns: 0
121 :header-rows: 0
122 :stub-columns: 0
126 - 0x00
129 - 0x01
132 - 0x02
135 - 0x0F
[all …]
/Documentation/driver-api/rapidio/
Dtsi721.rst44 DMA channels (0 ... 6) will be registered with DmaEngine core.
47 driver. Default value is 0x7f (use all channels).
54 0 = 128B, 1 = 256B, 2 = 512B, 3 = 1024B, 4 = 2048B and 5 = 4096B.
59 messaging MBOXes are managed by this device driver. Mask bits 0 - 3
61 corresponding bit is set to '1'. Default value is 0x0f (= all).
90 1.1.0 DMA operations re-worked to support data scatter/gather lists larger
92 1.0.0 Initial driver release.
/Documentation/userspace-api/media/cec/
Dcec-pin-error-inj.rst69 # <op> CEC message opcode (0-255) or 'any'
71 # <bit> CEC message bit (0-159)
72 # 10 bits per 'byte': bits 0-7: data, bit 8: EOM, bit 9: ACK
73 # <poll> CEC poll message used to test arbitration lost (0x00-0xff, default 0x0f)
74 # <usecs> microseconds (0-10000000, default 1000)
105 '``0x82,toggle rx-nack``' will only NACK if an Active Source message was
114 0x9e tx-add-bytes 1
115 0x9e tx-early-eom
116 0x9f tx-add-bytes 2
124 0x9e tx-add-bytes 1
[all …]
/Documentation/hwmon/
Dlm93.rst10 Addresses scanned: I2C 0x2c-0x2e
18 Addresses scanned: I2C 0x2c-0x2e
33 Set to non-zero to force some initializations (default is 0).
35 A "0" allows SMBus block data transactions if the host supports them. A "1"
36 disables SMBus block data transactions. The default is 0.
38 Configures in7 and in8 limit type, where 0 means absolute and non-zero
44 is "0,0".
46 A "0" configures the VID pins for V(ih) = 2.1V min, V(il) = 0.8V max.
50 inputs are not working, try changing this. The default value is "0".
90 from 0-255 where 0 indicates no throttling, and 255 indicates > 99.6%.
[all …]

12