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/Documentation/devicetree/bindings/crypto/
Dhisilicon,hip07-sec.txt9 Region 0 has registers to control the backend processing engines.
16 Interrupt 0 is for the SEC unit error queue.
29 reg = <0x400 0xd0000000 0x0 0x10000
30 0x400 0xd2000000 0x0 0x10000
31 0x400 0xd2010000 0x0 0x10000
32 0x400 0xd2020000 0x0 0x10000
33 0x400 0xd2030000 0x0 0x10000
34 0x400 0xd2040000 0x0 0x10000
35 0x400 0xd2050000 0x0 0x10000
36 0x400 0xd2060000 0x0 0x10000
[all …]
/Documentation/devicetree/bindings/display/ti/
Dti,j721e-dss.yaml27 - description: common_s0 DSS Shared common 0
83 - description: common_s0 DSS Shared common 0
107 const: 0
109 port@0:
159 reg = <0x04a00000 0x10000>, /* common_m */
160 <0x04a10000 0x10000>, /* common_s0*/
161 <0x04b00000 0x10000>, /* common_s1*/
162 <0x04b10000 0x10000>, /* common_s2*/
163 <0x04a20000 0x10000>, /* vidl1 */
164 <0x04a30000 0x10000>, /* vidl2 */
[all …]
/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra186-pmc.txt29 reg = <0 0x0c360000 0 0x10000>,
30 <0 0x0c370000 0 0x10000>,
31 <0 0x0c380000 0 0x10000>,
32 <0 0x0c390000 0 0x10000>;
89 reg = <0 0x0c360000 0 0x10000>,
90 <0 0x0c370000 0 0x10000>,
91 <0 0x0c380000 0 0x10000>,
92 <0 0x0c390000 0 0x10000>;
122 pinctrl-0 = <&sdmmc1_3v3>;
130 pinctrl-0 = <&hdmi_off>;
/Documentation/devicetree/bindings/mtd/partitions/
Dbrcm,bcm963xx-imagetag.txt18 reg = <0x1e000000 0x2000000>;
26 cfe@0 {
27 reg = <0x0 0x10000>;
32 reg = <0x10000 0x7d0000>;
37 reg = <0x7e0000 0x10000>;
42 reg = <0x7f0000 0x10000>;
/Documentation/devicetree/bindings/mips/cavium/
Dbootbus.txt52 - cavium,pages: A cell specifying the PAGES parameter (0 = 8 bytes, 1
71 reg = <0x11800 0x00000000 0x0 0x200>;
76 ranges = <0 0 0x0 0x1f400000 0xc00000>,
77 <1 0 0x10000 0x30000000 0>,
78 <2 0 0x10000 0x40000000 0>,
79 <3 0 0x10000 0x50000000 0>,
80 <4 0 0x0 0x1d020000 0x10000>,
81 <5 0 0x0 0x1d040000 0x10000>,
82 <6 0 0x0 0x1d050000 0x10000>,
83 <7 0 0x10000 0x90000000 0>;
[all …]
/Documentation/devicetree/bindings/net/
Dmscc-ocelot.txt18 - "portX" with X from 0 to the number of last port index available on that
31 - #size-cells: Must be 0
46 reg = <0x1010000 0x10000>,
47 <0x1030000 0x10000>,
48 <0x1080000 0x100>,
49 <0x10e0000 0x10000>,
50 <0x11e0000 0x100>,
51 <0x11f0000 0x100>,
52 <0x1200000 0x100>,
53 <0x1210000 0x100>,
[all …]
Dhisilicon-hip04-net.txt43 reg = <0x28f1000 0x1000>;
45 #size-cells = <0>;
47 phy0: ethernet-phy@0 {
49 reg = <0>;
50 marvell,reg-init = <18 0x14 0 0x8001>;
56 marvell,reg-init = <18 0x14 0 0x8001>;
62 reg = <0x28c0000 0x10000>;
67 reg = <0x28b0000 0x10000>;
68 interrupts = <0 413 4>;
70 port-handle = <&ppe 31 0 31>;
[all …]
Dsocionext-netsec.txt19 - #size-cells: Must be <0>.
40 reg = <0 0x522d0000 0x0 0x10000>, <0 0x10000000 0x0 0x10000>;
51 #size-cells = <0>;
/Documentation/devicetree/bindings/soc/qcom/
Drpmh-rsc.txt52 "drv-0", "drv-1", "drv-2" etc and "tcs-offset". The
91 For a TCS whose RSC base address is is 0x179C0000 and is at a DRV id of 2, the
92 register offsets for DRV2 start at 0D00, the register calculations are like
94 DRV0: 0x179C0000
95 DRV2: 0x179C0000 + 0x10000 = 0x179D0000
96 DRV2: 0x179C0000 + 0x10000 * 2 = 0x179E0000
97 TCS-OFFSET: 0xD00
102 reg = <0x179c0000 0x10000>,
103 <0x179d0000 0x10000>,
104 <0x179e0000 0x10000>;
[all …]
/Documentation/devicetree/bindings/media/
Dnxp,imx8mq-vpu.yaml67 reg = <0x38300000 0x10000>,
68 <0x38310000 0x10000>,
69 <0x38320000 0x10000>;
/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx7d-pinctrl.txt13 reg = <0x302c0000 0x10000>;
19 reg = <0x30330000 0x10000>;
42 PAD_CTL_PUS_100K_DOWN (0 << 5)
49 PAD_CTL_SRE_FAST (0 << 2)
50 PAD_CTL_DSE_X1 (0 << 0)
51 PAD_CTL_DSE_X4 (1 << 0)
52 PAD_CTL_DSE_X2 (2 << 0)
53 PAD_CTL_DSE_X6 (3 << 0)
63 pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>;
68 reg = <0x302c0000 0x10000>;
[all …]
/Documentation/devicetree/bindings/virtio/
Diommu.txt16 0b00000000 bbbbbbbb dddddfff 00000000. The other cells
37 reg = <0x00000800 0 0 0 0>;
45 iommu-map = <0x0 &iommu0 0x0 0x8>
46 <0x9 &iommu0 0x9 0xfff7>;
54 * with endpoint IDs 0x10000 - 0x1ffff
56 iommu-map = <0x0 &iommu0 0x10000 0x10000>;
61 /* The IOMMU manages this platform device with endpoint ID 0x20000 */
62 iommus = <&iommu0 0x20000>;
/Documentation/devicetree/bindings/usb/
Dcdns,usb3.yaml85 reg = <0x00 0x6000000 0x00 0x10000>,
86 <0x00 0x6010000 0x00 0x10000>,
87 <0x00 0x6020000 0x00 0x10000>;
Dti,j721e-usb.yaml38 If present, it restricts the controller to USB2.0 mode of
85 reg = <0x00 0x4104000 0x00 0x100>;
96 reg = <0x00 0x6000000 0x00 0x10000>,
97 <0x00 0x6010000 0x00 0x10000>,
98 <0x00 0x6020000 0x00 0x10000>;
100 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
102 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
/Documentation/devicetree/bindings/sound/
Dxlnx,i2s.txt19 reg = <0x0 0xa0080000 0x0 0x10000>;
20 xlnx,dwidth = <0x18>;
25 reg = <0x0 0xa0090000 0x0 0x10000>;
26 xlnx,dwidth = <0x18>;
Dsirf-audio-codec.txt15 reg = <0xb0040000 0x10000>;
/Documentation/devicetree/bindings/ata/
Dcavium-compact-flash.txt24 compact-flash@5,0 {
26 reg = <5 0 0x10000>, <6 0 0x10000>;
/Documentation/devicetree/bindings/mailbox/
Dmailbox.txt36 mboxes = <&mailbox 0 &mailbox 1>;
43 reg = <0x50000000 0x10000>;
47 ranges = <0 0x50000000 0x10000>;
49 cl_shmem: shmem@0 {
51 reg = <0x0 0x200>;
57 mboxes = <&mailbox 0>;
/Documentation/devicetree/bindings/dma/
Dapm-xgene-dma.txt27 clocks = <&socplldiv2 0>;
28 reg = <0x0 0x1f27c000 0x0 0x1000>;
36 reg = <0x0 0x1f270000 0x0 0x10000>,
37 <0x0 0x1f200000 0x0 0x10000>,
38 <0x0 0x1b000000 0x0 0x400000>,
39 <0x0 0x1054a000 0x0 0x100>;
40 interrupts = <0x0 0x82 0x4>,
41 <0x0 0xb8 0x4>,
42 <0x0 0xb9 0x4>,
43 <0x0 0xba 0x4>,
[all …]
Dmmp-dma.txt28 * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq,
33 reg = <0xd4000000 0x10000>;
34 interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
46 reg = <0xd4000000 0x10000>;
69 reg = <0xd42a0800 0x100>;
77 reg = <0xd42a0800 0x100>;
/Documentation/devicetree/bindings/interrupt-controller/
Dfsl,ls-extirq.txt13 - #address-cells: Must be 0.
19 - interrupt-map-mask: Must be <0xffffffff 0>.
24 reg = <0x0 0x1570000 0x0 0x10000>;
28 ranges = <0x0 0x0 0x1570000 0x10000>;
33 #address-cells = <0>;
35 reg = <0x1ac 4>;
37 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
38 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
39 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
40 <3 0 &gic GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/Documentation/devicetree/bindings/gpio/
Dgpio-mpc8xxx.txt12 0 = active high
24 reg = <0x1100 0x080>;
25 interrupts = <78 0x8>;
32 reg = <0x0 0x2300000 0x0 0x10000>;
33 interrupts = <0 36 0x4>; /* Level high type */
46 reg = <0x0 0x2300000 0x0 0x10000>;
/Documentation/devicetree/bindings/mtd/
Dcadence-nand-controller.txt11 - #size-cells : should be 0.
27 - reg: shall contain the native Chip Select ids from 0 to max supported by
38 #size-cells = <0>;
39 reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
43 interrupts = <2 0>;
44 nand@0 {
45 reg = <0>;
/Documentation/devicetree/bindings/pci/
Dpci-armada8k.txt32 reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;
40 bus-range = <0 0xff>;
41 ranges = <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000 /* downstream I/O */
42 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>; /* non-prefetchable memory */
43 interrupt-map-mask = <0 0 0 0>;
44 interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
/Documentation/devicetree/bindings/powerpc/fsl/
Draideng.txt11 - compatible: Should contain "fsl,raideng-v1.0" as the value
13 major number whereas 0 represents minor number. The
22 compatible = "fsl,raideng-v1.0";
25 reg = <0x320000 0x10000>;
26 ranges = <0 0x320000 0x10000>;
33 - compatible: Should contain "fsl,raideng-v1.0-job-queue" as the value
42 compatible = "fsl,raideng-v1.0-job-queue";
43 reg = <0x1000 0x1000>;
44 ranges = <0x0 0x1000 0x1000>;
51 - compatible: Must contain "fsl,raideng-v1.0-job-ring" as the value
[all …]

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