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/Documentation/devicetree/bindings/memory-controllers/
Datmel,ebi.txt103 reg = <0x10000000 0x10000000
104 0x40000000 0x30000000>;
105 ranges = <0x0 0x0 0x10000000 0x10000000
106 0x1 0x0 0x40000000 0x10000000
107 0x2 0x0 0x50000000 0x10000000
108 0x3 0x0 0x60000000 0x10000000>;
112 pinctrl-0 = <&pinctrl_ebi_addr>;
114 nor: flash@0,0 {
118 reg = <0x0 0x0 0x1000000>;
124 atmel,smc-ncs-rd-setup-ns = <0>;
[all …]
/Documentation/devicetree/bindings/arm/stm32/
Dst,mlahb.yaml61 reg = <0x10000000 0x40000>;
63 dma-ranges = <0x00000000 0x38000000 0x10000>,
64 <0x10000000 0x10000000 0x60000>,
65 <0x30000000 0x30000000 0x60000>;
68 reg = <0x10000000 0x40000>;
/Documentation/devicetree/bindings/mtd/
Datmel-nand.txt38 device (always 0)
39 3rd entry: the memory region size (always 0x800000)
77 reg = <0x70000000 0x8000000>;
82 reg = <0xffffc070 0x490>,
83 <0xffffc500 0x100>;
91 reg = <0x10000000 0x10000000
92 0x40000000 0x30000000>;
93 ranges = <0x0 0x0 0x10000000 0x10000000
94 0x1 0x0 0x40000000 0x10000000
95 0x2 0x0 0x50000000 0x10000000
[all …]
Dhisilicon,fmc-spi-nor.txt7 - size-cells : Should be 0.
16 #size-cells = <0>;
17 reg = <0x10000000 0x1000>, <0x14000000 0x1000000>;
20 spi-nor@0 {
22 reg = <0>;
Dflctl-nand.txt26 reg = <0xe6a30000 0x100>;
27 interrupts = <0x0d80>;
35 system@0 {
37 reg = <0x0 0x8000000>;
42 reg = <0x8000000 0x10000000>;
47 reg = <0x18000000 0x8000000>;
/Documentation/devicetree/bindings/pci/
Daltera-pcie.txt31 reg = <0xc0000000 0x20000000>,
32 <0xff220000 0x00004000>;
35 interrupts = <0 40 4>;
38 bus-range = <0x0 0xFF>;
43 interrupt-map-mask = <0 0 0 7>;
44 interrupt-map = <0 0 0 1 &pcie_0 1>,
45 <0 0 0 2 &pcie_0 2>,
46 <0 0 0 3 &pcie_0 3>,
47 <0 0 0 4 &pcie_0 4>;
48 ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
[all …]
Dxilinx-pcie.txt28 address. The value must be 0.
47 reg = < 0x50000000 0x1000000 >;
49 interrupts = < 0 52 4 >;
50 interrupt-map-mask = <0 0 0 7>;
51 interrupt-map = <0 0 0 1 &pcie_intc 1>,
52 <0 0 0 2 &pcie_intc 2>,
53 <0 0 0 3 &pcie_intc 3>,
54 <0 0 0 4 &pcie_intc 4>;
55 ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
59 #address-cells = <0>;
[all …]
D83xx-512x-pci.txt12 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
14 /* IDSEL 0x0E -mini PCI */
15 0x7000 0x0 0x0 0x1 &ipic 18 0x8
16 0x7000 0x0 0x0 0x2 &ipic 18 0x8
17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
18 0x7000 0x0 0x0 0x4 &ipic 18 0x8
20 /* IDSEL 0x0F - PCI slot */
21 0x7800 0x0 0x0 0x1 &ipic 17 0x8
22 0x7800 0x0 0x0 0x2 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
[all …]
Dv3-v360epc-pci.txt18 each be exactly 256MB (0x10000000) in size.
38 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
42 bus-range = <0x00 0xff>;
43 ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
44 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
45 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
46 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
47 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
48 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
49 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
[all …]
Dversatile.yaml38 - const: 0x1800
39 - const: 0
40 - const: 0
58 reg = <0x10001000 0x1000>,
59 <0x41000000 0x10000>,
60 <0x42000000 0x100000>;
61 bus-range = <0 0xff>;
67 <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */
68 <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */
69 <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
[all …]
Dxilinx-versal-cpm.yaml47 const: 0
79 interrupts = <0 72 4>;
81 interrupt-map-mask = <0 0 0 7>;
82 interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
83 <0 0 0 2 &pcie_intc_0 1>,
84 <0 0 0 3 &pcie_intc_0 2>,
85 <0 0 0 4 &pcie_intc_0 3>;
86 bus-range = <0x00 0xff>;
87 ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
88 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
[all …]
Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
/Documentation/devicetree/bindings/mips/lantiq/
Dfpi-bus.txt20 ranges = <0x0 0x10000000 0xf000000>;
21 reg = <0x1f400000 0x1000>,
22 <0x10000000 0xf000000>;
24 lantiq,offset-endianness = <0x4c>;
/Documentation/devicetree/bindings/c6x/
Demifa.txt35 reg = <0x70000000 0x100>;
36 ranges = <0x2 0x0 0xa0000000 0x00000008
37 0x3 0x0 0xb0000000 0x00400000
38 0x4 0x0 0xc0000000 0x10000000
39 0x5 0x0 0xD0000000 0x10000000>;
43 ti,emifa-ce-config = <0x00240120
44 0x00240120
45 0x00240122
46 0x00240122>;
48 flash@3,0 {
[all …]
/Documentation/parisc/
Ddebugging.rst15 address you can lookup in System.map, add __PAGE_OFFSET (0x10000000
30 than __PAGE_OFFSET (0x10000000) which mean a virtual address didn't
/Documentation/devicetree/bindings/rtc/
Dmaxim,ds1742.txt11 reg = <0x10000000 0x800>;
/Documentation/devicetree/bindings/net/
Dcirrus,cs89x0.txt11 reg = <0x10000000 0x400>;
/Documentation/devicetree/bindings/bus/
Darm,integrator-ap-lm.yaml15 determine if a logic module is connected at index 0, 1, 2 or 3. The logic
35 "^bus(@[0-9a-f]*)?$":
37 and are named with bus. The first module is at 0xc0000000, the second
38 at 0xd0000000 and so on until the top of the memory of the system at
39 0xffffffff. All information about the memory used by the module is
55 ranges = <0xc0000000 0xc0000000 0x40000000>;
60 ranges = <0x00000000 0xc0000000 0x10000000>;
61 /* The Logic Modules sees the Core Module 0 RAM @80000000 */
62 dma-ranges = <0x00000000 0x80000000 0x10000000>;
68 reg = <0x00100000 0x1000>;
[all …]
/Documentation/devicetree/bindings/clock/
Dingenic,cgu.yaml34 pattern: "^clock-controller@[0-9a-f]+$"
104 reg = <0x10000000 0x100>;
107 ranges = <0x0 0x10000000 0x100>;
116 reg = <0x3c 0x10>;
122 #phy-cells = <0>;
/Documentation/devicetree/bindings/gpu/
Dnvidia,gk20a.txt46 reg = <0x0 0x57000000 0x0 0x01000000>,
47 <0x0 0x58000000 0x0 0x01000000>;
64 reg = <0x0 0x57000000 0x0 0x01000000>,
65 <0x0 0x58000000 0x0 0x01000000>;
82 reg = <0x0 0x17000000 0x0 0x1000000>,
83 <0x0 0x18000000 0x0 0x1000000>;
100 reg = <0x17000000 0x10000000>,
101 <0x18000000 0x10000000>;
/Documentation/devicetree/bindings/powerpc/fsl/
Dsrio.txt9 Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0.
20 be set to 0x11000.
83 reg = <0xf 0xfe0c0000 0 0x11000>;
94 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
102 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
/Documentation/devicetree/bindings/arm/samsung/
Dexynos-chipid.yaml26 enum: [0, 1, 2, 3]
38 reg = <0x10000000 0x100>;
/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,topckgen.txt32 reg = <0 0x10000000 0 0x1000>;
/Documentation/firmware-guide/acpi/
Ddebug.rst41 ACPI_UTILITIES 0x00000001
42 ACPI_HARDWARE 0x00000002
43 ACPI_EVENTS 0x00000004
44 ACPI_TABLES 0x00000008
45 ACPI_NAMESPACE 0x00000010
46 ACPI_PARSER 0x00000020
47 ACPI_DISPATCHER 0x00000040
48 ACPI_EXECUTER 0x00000080
49 ACPI_RESOURCES 0x00000100
50 ACPI_CA_DEBUGGER 0x00000200
[all …]
/Documentation/devicetree/bindings/ptp/
Dtimestamper.txt21 reg = <0x10000000 0x80>;
27 timestamper = <&tstamper 0>;
41 appear on time stamp channel 0 (zero), and those from phy@2 appear on

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