Searched +full:0 +full:x10001 (Results 1 – 3 of 3) sorted by relevance
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in31 the reg property contained in bits 7 down to 049 this property is required and must be set to 0.52 required and matches the CPUID[11:0] register bits.54 Bits [11:0] in the reg cell must be set to55 bits [11:0] in CPU ID register.57 All other bits in the reg cell must be set to 0.60 required and matches the CPU MPIDR[23:0] register63 Bits [23:0] in the reg cell must be set to64 bits [23:0] in MPIDR.[all …]
82 between 0 and infinite time, until a wake-up event occurs.107 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)147 0| 1 time(ms)152 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope332 #size-cells = <0>;335 cpu@0 {338 reg = <0x0 0x0>;347 reg = <0x0 0x1>;356 reg = <0x0 0x100>;365 reg = <0x0 0x101>;[all …]
87 (ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes89 sequential N value, starting from 0).187 #size-cells = <0>;276 CPU0: cpu@0 {279 reg = <0x0 0x0>;281 cpu-release-addr = <0 0x20000000>;287 reg = <0x0 0x1>;289 cpu-release-addr = <0 0x20000000>;295 reg = <0x0 0x100>;297 cpu-release-addr = <0 0x20000000>;[all …]