Searched +full:0 +full:x20 (Results 1 – 25 of 188) sorted by relevance
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-lp55xx.yaml | 42 - 0 # automode
56 - 0 # D1~9 are connected to VDD
65 const: 0
68 "(^led@[0-9a-f]$|led)":
75 Current setting at each LED channel (mA x10, 0 if LED is not connected)
76 minimum: 0
89 - 0 # LED output D1
115 #size-cells = <0>;
119 #size-cells = <0>;
121 reg = <0x32>;
[all …]
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| /Documentation/devicetree/bindings/mailbox/ |
| D | xlnx,zynqmp-ipi-mailbox.txt | 59 * tx(0) or rx(1) channel
83 interrupts = <0 29 4>;
84 xlnx,ipi-id = <0>;
91 reg = <0xff990400 0x20>,
92 <0xff990420 0x20>,
93 <0xff990080 0x20>,
94 <0xff9900a0 0x20>;
104 reg = <0xff990440 0x20>,
105 <0xff990460 0x20>,
106 <0xff990280 0x20>,
[all …]
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| /Documentation/devicetree/bindings/clock/ |
| D | lsi,axm5516-clks.txt | 18 reg = <0x20 0x10020000 0 0x20000>;
23 reg = <0x20 0x10080000 0 0x1000>;
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| D | ti-clkctrl.txt | 33 cm_l4per@0 {
36 reg = <0x20 0x1b0>;
45 #define OMAP4_CLKCTRL_OFFSET 0x20
50 #define OMAP4_GPTIMER10_CLKTRL OMAP4_CLKCTRL_INDEX(0x28)
51 #define OMAP4_GPTIMER11_CLKTRL OMAP4_CLKCTRL_INDEX(0x30)
52 #define OMAP4_GPTIMER2_CLKTRL OMAP4_CLKCTRL_INDEX(0x38)
54 #define OMAP4_GPIO2_CLKCTRL OMAP_CLKCTRL_INDEX(0x60)
59 clocks = <&cm_l4per_clkctrl OMAP4_GPIO2_CLKCTRL 0
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | zinitix.txt | 6 - reg : I2C address of the chip. Should be 0x20
27 reg = <0x20>;
31 pinctrl-0 = <&tsp_default>;
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| D | cypress,cy8ctma140.yaml | 20 const: 0x20
58 #size-cells = <0>;
61 reg = <0x20>;
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| /Documentation/devicetree/bindings/power/ |
| D | pd-samsung.yaml | 42 const: 0
58 reg = <0x10023c80 0x20>;
59 #power-domain-cells = <0>;
65 reg = <0x10044060 0x20>;
66 #power-domain-cells = <0>;
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| /Documentation/devicetree/bindings/timer/ |
| D | arm,twd.txt | 31 reg = <0x2c000600 0x20>;
32 interrupts = <1 13 0xf01>;
51 reg = <0x2c000620 0x20>;
52 interrupts = <1 14 0xf01>;
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| D | socionext,milbeaut-timer.txt | 14 reg = <0x1e000050 0x20>
15 interrupts = <0 91 4>;
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| D | marvell,orion-timer.txt | 12 reg = <0x20300 0x20>;
15 clocks = <&core_clk 0>;
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| /Documentation/devicetree/bindings/reset/ |
| D | hisilicon,hi3660-reset.txt | 27 reg = <0x0 0xffd7e000 0x0 0x1000>;
42 resets = <&iomcu_rst 0x20 3>; /* offset: 0x20; bit: 3 */
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| /Documentation/devicetree/bindings/ |
| D | resource-names.txt | 27 ranges = <0 0 0x48000000 0x00001000>, /* MPU path */
28 <1 0 0x49000000 0x00001000>; /* L3 path */
31 reg = <0 0x10 0x10>, <0 0x20 0x10>,
32 <1 0x10 0x10>, <1 0x20 0x10>;
41 reg = <0 0x40 0x10>, <1 0x40 0x10>;
49 reg = <0x4a064000 0x800>, <0x4a064800 0x200>,
50 <0x4a064c00 0x200>;
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-eic-sprd.txt | 50 reg = <0 0x40210000 0 0x80>;
60 reg = <0 0x40210080 0 0x20>;
70 reg = <0 0x402100a0 0 0x20>;
80 reg = <0 0x402100c0 0 0x20>;
90 reg = <0x300>;
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | brcm,bcm6345-l1-intc.txt | 47 reg = <0x10000020 0x20>,
48 <0x10000040 0x20>;
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| /Documentation/leds/ |
| D | leds-mlxcpld.rst | 28 - CPLD reg offset: 0x20
29 - Bits [3:0]
32 - CPLD reg offset: 0x20
36 - CPLD reg offset: 0x21
37 - Bits [3:0]
40 - CPLD reg offset: 0x21
44 - CPLD reg offset: 0x22
45 - Bits [3:0]
48 - CPLD reg offset: 0x22
56 - [0,0,0,0] = LED OFF
[all …]
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| /Documentation/hwmon/ |
| D | ltc3815.rst | 30 at address 0x20 on I2C bus #1::
33 # echo ltc3815 0x20 > /sys/bus/i2c/devices/i2c-1/new_device
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| /Documentation/devicetree/bindings/net/can/ |
| D | xilinx_can.txt | 34 reg = <0xe0008000 0x1000>;
35 interrupts = <0 28 4>;
37 tx-fifo-depth = <0x40>;
38 rx-fifo-depth = <0x40>;
43 clocks = <&clkc 0>, <&clkc 1>;
45 reg = <0x40000000 0x10000>;
47 interrupts = <0 59 1>;
48 tx-fifo-depth = <0x40>;
49 rx-fifo-depth = <0x40>;
54 clocks = <&clkc 0>, <&clkc 1>;
[all …]
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| /Documentation/devicetree/bindings/power/reset/ |
| D | axxia-reset.txt | 14 reg = <0x20 0x10030000 0 0x2000>;
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| /Documentation/devicetree/bindings/rtc/ |
| D | orion-rtc.txt | 16 reg = <0xd0010300 0x20>;
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | counter.txt | 13 reg = <0x4a304000 0x20>;
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| /Documentation/devicetree/bindings/perf/ |
| D | arm-ccn.txt | 21 reg = <0x20 0x00000000 0 0x1000000>;
22 interrupts = <0 181 4>;
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| /Documentation/devicetree/bindings/arm/marvell/ |
| D | armada-cpu-reset.txt | 13 reg = <0x20800 0x20>;
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| /Documentation/devicetree/bindings/media/ |
| D | meson-ir.txt | 18 reg = <0xc8100480 0x20>;
19 interrupts = <0 15 1>;
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| /Documentation/devicetree/bindings/iio/magnetometer/ |
| D | pni,rm3100.txt | 17 reg = <0x20>;
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| /Documentation/devicetree/bindings/fpga/ |
| D | altera-socfpga-a10-fpga-mgr.txt | 15 reg = <0xffd03000 0x100
16 0xffcfe400 0x20>;
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