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/Documentation/devicetree/bindings/arm/
Dcpus.yaml30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
49 this property is required and must be set to 0.
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
55 bits [11:0] in CPU ID register.
57 All other bits in the reg cell must be set to 0.
60 required and matches the CPU MPIDR[23:0] register
63 Bits [23:0] in the reg cell must be set to
64 bits [23:0] in MPIDR.
[all …]
/Documentation/devicetree/bindings/cpu/
Dcpu-topology.txt87 (ie socket/cluster/core/thread) (where N = {0, 1, ...} is the node number; nodes
89 sequential N value, starting from 0).
187 #size-cells = <0>;
276 CPU0: cpu@0 {
279 reg = <0x0 0x0>;
281 cpu-release-addr = <0 0x20000000>;
287 reg = <0x0 0x1>;
289 cpu-release-addr = <0 0x20000000>;
295 reg = <0x0 0x100>;
297 cpu-release-addr = <0 0x20000000>;
[all …]
/Documentation/devicetree/bindings/pci/
Dlayerscape-pci.txt36 The second entry must be '0' or '1' based on physical PCIe controller index.
46 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
47 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
51 fsl,pcie-scfg = <&scfg 0>;
57 bus-range = <0x0 0xff>;
58 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
59 0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000 /* prefetchable memory */
60 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
62 interrupt-map-mask = <0 0 0 7>;
63 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
[all …]
Dv3-v360epc-pci.txt18 each be exactly 256MB (0x10000000) in size.
38 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
42 bus-range = <0x00 0xff>;
43 ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
44 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
45 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
46 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
47 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
48 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
49 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
[all …]
Dmediatek-pcie.txt31 where N starting from 0 to one less than the number of root ports.
76 reg = <0 0x1a000000 0 0x1000>;
84 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
85 <0 0x1a142000 0 0x1000>, /* Port0 registers */
86 <0 0x1a143000 0 0x1000>, /* Port1 registers */
87 <0 0x1a144000 0 0x1000>; /* Port2 registers */
92 interrupt-map-mask = <0xf800 0 0 0>;
93 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
94 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
95 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
[all …]
Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
Dbrcm,iproc-pcie.txt77 reg = <0x18012000 0x1000>;
80 interrupt-map-mask = <0 0 0 0>;
81 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
83 linux,pci-domain = <0>;
85 bus-range = <0x00 0xff>;
90 ranges = <0x81000000 0 0 0x28000000 0 0x00010000
91 0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
93 phys = <&phy 0 5>;
97 brcm,pcie-ob-axi-offset = <0x00000000>;
115 reg = <0x18013000 0x1000>;
[all …]
Daltera-pcie.txt31 reg = <0xc0000000 0x20000000>,
32 <0xff220000 0x00004000>;
35 interrupts = <0 40 4>;
38 bus-range = <0x0 0xFF>;
43 interrupt-map-mask = <0 0 0 7>;
44 interrupt-map = <0 0 0 1 &pcie_0 1>,
45 <0 0 0 2 &pcie_0 2>,
46 <0 0 0 3 &pcie_0 3>,
47 <0 0 0 4 &pcie_0 4>;
48 ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000
[all …]
Duniphier-pcie.txt52 reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
53 <0x2fff0000 0x10000>;
60 bus-range = <0x0 0xff>;
64 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000
66 0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;
69 interrupts = <0 224 4>, <0 225 4>;
70 interrupt-map-mask = <0 0 0 7>;
71 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
72 <0 0 0 2 &pcie_intc 1>, /* INTB */
73 <0 0 0 3 &pcie_intc 2>, /* INTC */
[all …]
/Documentation/firmware-guide/acpi/
Ddebug.rst41 ACPI_UTILITIES 0x00000001
42 ACPI_HARDWARE 0x00000002
43 ACPI_EVENTS 0x00000004
44 ACPI_TABLES 0x00000008
45 ACPI_NAMESPACE 0x00000010
46 ACPI_PARSER 0x00000020
47 ACPI_DISPATCHER 0x00000040
48 ACPI_EXECUTER 0x00000080
49 ACPI_RESOURCES 0x00000100
50 ACPI_CA_DEBUGGER 0x00000200
[all …]
/Documentation/devicetree/bindings/spi/
Dspi-nxp-fspi.txt18 - <0>: Bus A, CS 0
20 - <2>: Bus B, CS 0
27 reg = <0x0 0x20c0000 0x0 0x10000>, <0x0 0x20000000 0x0 0x10000000>;
29 interrupts = <0 25 0x4>; /* Level high type */
33 mt35xu512aba0: flash@0 {
34 reg = <0>;
Dspi-mxic.txt7 - #size-cells: should be 0
22 reg = <0x43c30000 0x10000>, <0xa0000000 0x20000000>;
24 clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 18>;
27 #size-cells = <0>;
29 flash@0 {
31 reg = <0>;
Dspi-fsl-qspi.txt19 <0>: Bus A, CS 0
21 <2>: Bus B, CS 0
28 reg = <0x40044000 0x1000>, <0x20000000 0x10000000>;
30 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
35 flash0: s25fl128s@0 {
40 reg = <0>;
48 pinctrl-0 = <&pinctrl_qspi2>;
51 flash0: n25q256a@0 {
56 reg = <0>;
Dspi-sifive.yaml60 enum: [0, 1, 2, 3, 4, 5, 6, 7, 8]
75 reg = <0x10040000 0x1000>, <0x20000000 0x10000000>;
80 #size-cells = <0>;
/Documentation/devicetree/bindings/mtd/
Daspeed-smc.txt21 - #size-cells : must be 0 corresponding to chip select child binding
38 reg = < 0x1e620000 0x94
39 0x20000000 0x02000000 >;
41 #size-cells = <0>;
43 flash@0 {
44 reg = < 0 >;
/Documentation/devicetree/bindings/clock/
Drockchip,rk3036-cru.txt39 reg = <0x20000000 0x1000>;
51 reg = <0x20060000 0x100>;
Drockchip,rk3228-cru.txt41 reg = <0x20000000 0x1000>;
53 reg = <0x10110000 0x100>;
Drockchip,rk3128-cru.txt41 reg = <0x20000000 0x1000>;
53 reg = <0x20068000 0x100>;
Drockchip,rk3188-cru.txt44 reg = <0x20000000 0x1000>;
56 reg = <0x10124000 0x400>;
Dsprd,sc9860-clk.txt53 clocks = <&pmu_gate 0>;
59 reg = <0 0x20000000 0 0x400>;
60 clocks = <&ext_26m>, <&pll 0>,
61 <&pmu_gate 0>;
Drockchip,rk3288-cru.txt50 reg = <0x20000000 0x1000>;
62 reg = <0x10124000 0x400>;
/Documentation/devicetree/bindings/bus/
Drenesas,bsc.yaml57 ranges = <0 0 0x20000000>;
58 reg = <0xfec10000 0x400>;
59 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
/Documentation/devicetree/bindings/arm/sunxi/
Dallwinner,sun4i-a10-mbus.yaml64 reg = <0x01c01000 0x1000>;
68 dma-ranges = <0x00000000 0x40000000 0x20000000>;
/Documentation/devicetree/bindings/dma/
Dst,stm32-mdma.yaml17 0x0: Low
18 0x1: Medium
19 0x2: High
20 0x3: Very high
22 -bit 0-1: Source increment mode
23 0x0: Source address pointer is fixed
24 0x2: Source address pointer is incremented after each data transfer
25 0x3: Source address pointer is decremented after each data transfer
27 0x0: Destination address pointer is fixed
28 0x2: Destination address pointer is incremented after each data transfer
[all …]
/Documentation/devicetree/bindings/powerpc/fsl/
Dsrio.txt9 Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0.
20 be set to 0x11000.
83 reg = <0xf 0xfe0c0000 0 0x11000>;
94 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
102 ranges = <0 0 0xc 0x30000000 0 0x10000000>;

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