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/Documentation/devicetree/bindings/memory-controllers/
Dti-da8xx-ddrctl.txt19 reg = <0xb0000000 0xe8>;
/Documentation/devicetree/bindings/clock/
Dbitmain,bm1880-clk.yaml57 reg = <0xe8 0x0c>, <0x800 0xb0>;
68 reg = <0x58018000 0x2000>;
71 interrupts = <0 9 4>;
/Documentation/hwmon/
Dmlxreg-fan.rst21 pwm1 0xe3
22 fan1 (tacho1) 0xe4
23 fan2 (tacho2) 0xe5
24 fan3 (tacho3) 0xe6
25 fan4 (tacho4) 0xe7
26 fan5 (tacho5) 0xe8
27 fan6 (tacho6) 0xe9
28 fan7 (tacho7) 0xea
29 fan8 (tacho8) 0xeb
30 fan9 (tacho9) 0xec
[all …]
Dpc87360.rst27 - 0: None
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
58 PC87364 - 3 3 - 0xE4
59 PC87365 11 3 3 2 0xE5
60 PC87366 11 3 3 3-4 0xE9
64 standard Super I/O addresses is used (0x2E/0x2F or 0x4E/0x4F)
111 PWM (pulse width modulation) values range from 0 to 255, with 0 meaning
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dqe.txt49 ranges = <0 e0100000 00100000>;
51 brg-frequency = <0>;
54 0x04 0x05 0x0C 0x0D 0x14 0x15 0x1C 0x1D
55 0x24 0x25 0x2C 0x2D 0x34 0x35 0x88 0x89
56 0x98 0x99 0xA8 0xA9 0xB8 0xB9 0xC8 0xC9
57 0xD8 0xD9 0xE8 0xE9>;
74 ranges = <0 00010000 0000c000>;
76 data-only@0{
79 reg = <0 c000>;
96 #address-cells = <0>;
[all …]
/Documentation/devicetree/bindings/pci/
Dmvebu-pci.txt23 0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
32 registers area. This range entry translates the '0x82000000 0 r' PCI
33 address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
34 of the internal register window (as identified by MBUS_ID(0xf0,
35 0x01)).
39 0x8t000000 s 0 MBUS_ID(w, a) 0 1 0
79 value is 0.
93 bus-range = <0x00 0xff>;
97 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
98 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
[all …]
/Documentation/devicetree/bindings/bus/
Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/Documentation/filesystems/ext4/
Dsuper.rst12 number is either 0 or a power of 3, 5, or 7. If the flag is not set,
29 * - 0x0
33 * - 0x4
37 * - 0x8
41 * - 0xC
45 * - 0x10
49 * - 0x14
53 is typically 0 for all other block sizes.
54 * - 0x18
58 * - 0x1C
[all …]
/Documentation/input/devices/
Dsentelic.rst21 4. Issuing the "Get device ID" command (0xF2) and waits for the response;
22 5. FSP will respond 0x04.
27 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
37 Bit2 => Middle Button, 1 is pressed, 0 is not pressed.
38 Bit1 => Right Button, 1 is pressed, 0 is not pressed.
39 Bit0 => Left Button, 1 is pressed, 0 is not pressed.
45 0 = 4th mouse button is not pressed.
47 0 = 5th mouse button is not pressed.
51 - Set bit 1 in register 0x40 to 1
59 Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
[all …]
/Documentation/driver-api/media/drivers/
Dcx2341x-devel.rst23 ivtvctl -O min=0x02000000,max=0x020000ff
32 (Base Address Register 0). The addresses here are offsets relative to the
37 0x00000000-0x00ffffff Encoder memory space
38 0x00000000-0x0003ffff Encode.rom
44 0x01000000-0x01ffffff Decoder memory space
45 0x01000000-0x0103ffff Decode.rom
47 0x0114b000-0x0115afff Audio.rom (deprecated?)
49 0x02000000-0x0200ffff Register Space
54 The registers occupy the 64k space starting at the 0x02000000 offset from BAR0.
59 DMA Registers 0x000-0xff:
[all …]