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Searched full:100000000 (Results 1 – 25 of 25) sorted by relevance

/Documentation/devicetree/bindings/ata/
Dqcom-sata.txt26 100Mhz (100000000) for SATA_RXOOB_CLK
27 100Mhz (100000000) for SATA_PMALIVE_CLK
44 assigned-clock-rates = <100000000>, <100000000>;
Dpata-arasan.txt14 100000000
Dapm-xgene.txt35 clock-frequency = <100000000>;
/Documentation/devicetree/bindings/mtd/
Dlpc32xx-slc.txt35 nxp,whold = <100000000>;
36 nxp,wsetup = <100000000>;
40 nxp,rsetup = <100000000>;
/Documentation/devicetree/bindings/devfreq/
Dexynos-bus.txt207 opp-100000000 {
208 opp-hz = /bits/ 64 <100000000>;
301 opp-100000000 {
302 opp-hz = /bits/ 64 <100000000>;
325 opp-100000000 {
326 opp-hz = /bits/ 64 <100000000>;
346 opp-100000000 {
347 opp-hz = /bits/ 64 <100000000>;
367 opp-100000000 {
368 opp-hz = /bits/ 64 <100000000>;
/Documentation/devicetree/bindings/gpu/
Darm,mali-bifrost.yaml119 opp-100000000 {
120 opp-hz = /bits/ 64 <100000000>;
Darm,mali-midgard.yaml173 opp-100000000 {
174 opp-hz = /bits/ 64 <100000000>;
/Documentation/devicetree/bindings/display/rockchip/
Dcdn-dp-rockchip.txt20 - assigned-clock-rates : the DP core clk frequency, shall be: 100000000
45 assigned-clock-rates = <100000000>;
/Documentation/devicetree/bindings/rtc/
Dxgene-rtc.txt18 clock-frequency = <100000000>;
/Documentation/devicetree/bindings/ddr/
Dlpddr3-timings.txt39 min-freq = <100000000>;
Dlpddr3.txt81 min-freq = <100000000>;
/Documentation/devicetree/bindings/arm/hisilicon/controller/
Dhi3798cv200-perictrl.yaml60 assigned-clock-rates = <100000000>;
/Documentation/devicetree/bindings/net/
Dimx-dwmac.txt50 assigned-clock-rates = <0>, <100000000>, <125000000>;
/Documentation/devicetree/bindings/mmc/
Dmmci.txt58 max-frequency = <100000000>;
/Documentation/devicetree/bindings/timer/
Darm,arch_timer.yaml108 clock-frequency = <100000000>;
/Documentation/accounting/
Ddelay-accounting.rst103 7876 92005750 100000000 24001500
/Documentation/devicetree/bindings/iio/addac/
Dadi,ad74413r.yaml52 default: 100000000
/Documentation/devicetree/bindings/ufs/
Dufshcd-pltfrm.txt81 freq-table-hz = <100000000 200000000>, <0 0>, <0 0>, <0 0>;
/Documentation/devicetree/bindings/spi/
Dspi-mux.yaml71 spi-max-frequency = <100000000>;
/Documentation/devicetree/bindings/pci/
Drockchip-pcie-host.txt96 assigned-clock-rates = <100000000>;
/Documentation/filesystems/
Dceph.rst72 setfattr -n ceph.quota.max_bytes -v 100000000 /some/dir
/Documentation/devicetree/bindings/arm/
Dcpus.yaml473 cpu@100000000 {
Didle-states.yaml407 cpu@100000000 {
/Documentation/devicetree/bindings/cpu/
Dcpu-topology.txt340 CPU8: cpu@100000000 {
/Documentation/scheduler/
Dsched-deadline.rst756 # schedtool -E -t 10000000:100000000 -e ./my_cpuhog_app
763 # schedtool -E -t 10000000:100000000 my_app_pid