Searched full:63 (Results 1 – 25 of 159) sorted by relevance
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | ciu2.txt | 13 the CIU and may have a value between 0 and 63. The second cell is
14 the bit within the bank and may also have a value between 0 and 63.
21 * 1) Controller register (0..63)
22 * 2) Bit within the register (0..63)
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| D | ciu.txt | 14 within the bank and may have a value between 0 and 63.
22 * 2) Bit within the register (0..63)
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| D | dma-engine.txt | 20 interrupts = <0 63>;
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-event_source-devices-hv_gpci | 14 partition_id = "config:32-63"
16 sibling_part_id = "config:32-63"
17 hw_chip_id = "config:32-63"
18 offset = "config:32-63"
19 phys_processor_idx = "config:32-63"
21 starting_index = "config:32-63"
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| /Documentation/devicetree/bindings/net/ |
| D | cavium-pip.txt | 63 local-mac-address = [ 00 0f b7 10 63 60 ];
69 local-mac-address = [ 00 0f b7 10 63 61 ];
75 local-mac-address = [ 00 0f b7 10 63 62 ];
81 local-mac-address = [ 00 0f b7 10 63 63 ];
95 local-mac-address = [ 00 0f b7 10 63 64 ];
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| /Documentation/sound/cards/ |
| D | audigy-mixer.rst | 243 * 0 - mono, A destination (FX-bus 0-63), default 0
244 * 1 - mono, B destination (FX-bus 0-63), default 1
245 * 2 - mono, C destination (FX-bus 0-63), default 2
246 * 3 - mono, D destination (FX-bus 0-63), default 3
247 * 4 - mono, E destination (FX-bus 0-63), default 0
248 * 5 - mono, F destination (FX-bus 0-63), default 0
249 * 6 - mono, G destination (FX-bus 0-63), default 0
250 * 7 - mono, H destination (FX-bus 0-63), default 0
251 * 8 - left, A destination (FX-bus 0-63), default 0
252 * 9 - left, B destination (FX-bus 0-63), default 1
[all …]
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| /Documentation/devicetree/bindings/media/ |
| D | coda.txt | 24 vpu: vpu@63ff4000 {
28 clocks = <&clks 63>, <&clks 63>;
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| D | si470x.txt | 18 si470x@63 {
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| D | si4713.txt | 21 fmtx: si4713@63 {
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| /Documentation/core-api/ |
| D | packing.rst | 44 perspective, bit 63 always means bit offset 7 of byte 7, albeit only
55 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
71 56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 40 41 42 43 44 45 46 47 32 33 34 35 36 37 38 39
84 39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 40 55 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56
98 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
110 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
125 56 57 58 59 60 61 62 63 48 49 50 51 52 53 54 55 40 41 42 43 44 45 46 47 32 33 34 35 36 37 38 39
136 39 38 37 36 35 34 33 32 47 46 45 44 43 42 41 40 55 54 53 52 51 50 49 48 63 62 61 60 59 58 57 56
147 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl-mt7622.txt | 78 to 63.
153 PIN 63: "MDI_TP_P3"
210 63, 64, 65, 66, 67, 68,
214 "esw_p2_p3_p4" "eth" 59, 60, 61, 62, 63, 64,
216 "rgmii_via_esw" "eth" 59, 60, 61, 62, 63, 64,
218 "rgmii_via_gmac1" "eth" 59, 60, 61, 62, 63, 64,
292 "spic0_0" "spi" 63, 64, 65, 66
396 PIN 63: "SPI_CS"
432 "snfi" "flash" 62, 63, 64, 65, 66, 67
433 "spi_nor" "flash" 62, 63, 64, 65, 66, 67
[all …]
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| /Documentation/translations/zh_CN/arm64/ |
| D | memory.txt | 39 用户地址空间的 63:48 位为 0，而内核地址空间的相应位为 1。TTBRx 的
40 选择由虚拟地址的 63 位给出。swapper_pg_dir 仅包含内核（全局）映射，
83 |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
92 +-------------------------------------------------> [63] TTBR0/1
98 |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
106 +-------------------------------------------------> [63] TTBR0/1
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| /Documentation/userspace-api/media/v4l/ |
| D | pixfmt-meta-vsp1-hgo.rst | 81 - :cspan:`4` R/Cr/H bin 63 [31:0]
87 - :cspan:`4` G/Y/S bin 63 [31:0]
93 - :cspan:`4` B/Cb/V bin 63 [31:0]
118 - :cspan:`4` max(R,G,B) bin 63 [31:0]
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| /Documentation/arm64/ |
| D | memory.rst | 21 User addresses have bits 63:48 set to 0 while the kernel addresses have
22 the same bits set to 1. TTBRx selection is given by bit 63 of the
71 |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
80 +-------------------------------------------------> [63] TTBR0/1
86 |63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
95 +-------------------------------------------------> [63] TTBR0/1
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| D | tagged-pointers.rst | 14 via TTBR0 (i.e. userspace mappings) have the top byte (bits 63:56) of
63 Due to architecture limitations, bits 63:60 of the fault address
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| /Documentation/virt/kvm/devices/ |
| D | arm-vgic-v3.rst | 38 bits: | 63 .... 52 | 51 .... 16 | 15 - 12 |11 - 0
82 bits: | 63 .... 32 | 31 .... 0 |
110 | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
176 bits: | 63 .... 32 | 31 .... 16 | 15 .... 0 |
182 | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
254 bits: | 63 .... 32 | 31 .... 10 | 9 .... 0 |
283 | 63 .... 56 | 55 .... 48 | 47 .... 40 | 39 .... 32 |
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| D | xive.rst | 107 bits: | 63 .... 2 | 1 | 0
130 bits: | 63 .... 33 | 32 | 31 .. 3 | 2 .. 0
159 bits: | 63 .... 32 | 31 .. 3 | 2 .. 0
221 bits: | 63 .... 32 | 31 .... 0 |
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| /Documentation/devicetree/bindings/clock/ |
| D | st,nomadik.txt | 41 - clock-id: must be the clock ID from 0 to 63 according to
104 63: RNGCCLK
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| /Documentation/devicetree/bindings/spi/ |
| D | nvidia,tegra114-spi.txt | 31 to corresponding slave devices. Valid tap values are from 0 thru 63.
36 to corresponding slave devices. Valid tap values are from 0 thru 63.
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| /Documentation/infiniband/ |
| D | opa_vnic.rst | 66 63 LT (=1, Link Transfer Head Flit)
74 48-63 Reserved
79 32-63 Ethernet Packet
82 0-63 Ethernet packet (pad extended)
88 62-63 LT (=01, Link Transfer Tail Flit)
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| /Documentation/scsi/ |
| D | aha152x.rst | 146 namely the address space is limited to up to 255 heads, up to 63 sectors
158 63 for sectors and then divides the capacity of the disk by 255*63
175 ie. either (C/32/64) or (C/63/255)). This can be extended translation
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| /Documentation/devicetree/bindings/timer/ |
| D | img,pistachio-gptimer.txt | 22 <GIC_SHARED 63 IRQ_TYPE_LEVEL_HIGH>;
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| /Documentation/trace/ |
| D | stm.rst | 24 48 to 63 and channels 0 to 127.
43 48 63
48 masters 48 through 63 and channel allocation pool has channels 0
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| /Documentation/devicetree/bindings/w1/ |
| D | fsl-imx-owire.yaml | 40 owire@63fa4000 {
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| /Documentation/devicetree/bindings/phy/ |
| D | marvell,mmp3-hsic-phy.yaml | 42 reset-gpios = <&gpio 63 GPIO_ACTIVE_HIGH>;
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