Searched +full:8 +full:- +full:cpu (Results 1 – 25 of 295) sorted by relevance
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| /Documentation/devicetree/bindings/mips/ |
| D | cpu_irq.txt | 1 MIPS CPU interrupt controller
3 On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
6 With the irq_domain in place we can describe how the 8 IRQs are wired to the
13 - compatible : Should be "mti,cpu-interrupt-controller"
16 cpu-irq: cpu-irq {
17 #address-cells = <0>;
19 interrupt-controller;
20 #interrupt-cells = <1>;
22 compatible = "mti,cpu-interrupt-controller";
26 compatible = "ralink,rt2880-intc";
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| D | mscc.txt | 7 - compatible: "mscc,ocelot"
12 o CPU chip regs:
19 - compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
20 - reg : Should contain registers location and length
24 compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
29 o CPU system control:
32 the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
33 endianness, CPU bus control, CPU status.
36 - compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
37 - reg : Should contain registers location and length
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| /Documentation/scheduler/ |
| D | sched-stats.rst | 11 12 which was in the kernel from 2.6.13-2.6.19 (version 13 never saw a kernel
12 release). Some counters make more sense to be per-runqueue; other to be
13 per-domain. Note that domains (and their associated information) will only
17 statistics for each cpu listed, and there may well be more than one
33 Note that any such script will necessarily be version-specific, as the main
37 CPU statistics
38 --------------
39 cpu<N> 1 2 3 4 5 6 7 8 9
55 6) # of times try_to_wake_up() was called to wake up the local cpu
60 8) sum of all time spent waiting to run by tasks on this processor (in
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| /Documentation/core-api/ |
| D | packing.rst | 6 -----------------
10 One can memory-map a pointer to a carefully crafted struct over the hardware
13 due to potential endianness mismatches between the CPU and the hardware device.
23 were performed byte-by-byte. Also the code can easily get cluttered, and the
24 high-level idea might get lost among the many bit shifts required.
25 Many drivers take the bit-shifting approach and then attempt to reduce the
30 ------------
34 - Packing a CPU-usable number into a memory buffer (with hardware
36 - Unpacking a memory buffer (which has hardware constraints/quirks)
37 into a CPU-usable number.
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| /Documentation/devicetree/bindings/mips/img/ |
| D | xilfpga.txt | 14 the ARTIX-7 FPGA by Xilinx.
18 - microAptiv UP core m14Kc
19 - 50MHz clock speed
20 - 128Mbyte DDR RAM at 0x0000_0000
21 - 8Kbyte RAM at 0x1000_0000
22 - axi_intc at 0x1020_0000
23 - axi_uart16550 at 0x1040_0000
24 - axi_gpio at 0x1060_0000
25 - axi_i2c at 0x10A0_0000
26 - custom_gpio at 0x10C0_0000
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
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| D | jcore,aic.txt | 1 J-Core Advanced Interrupt Controller
5 - compatible: Should be "jcore,aic1" for the (obsolete) first-generation aic
6 with 8 interrupt lines with programmable priorities, or "jcore,aic2" for
9 - reg: Memory region(s) for configuration. For SMP, there should be one
10 region per cpu, indexed by the sequential, zero-based hardware cpu
13 - interrupt-controller: Identifies the node as an interrupt controller
15 - #interrupt-cells: Specifies the number of cells needed to encode an
21 aic: interrupt-controller@200 {
24 interrupt-controller;
25 #interrupt-cells = <1>;
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| D | brcm,bcm2836-l1-intc.txt | 1 BCM2836 per-CPU interrupt controller
3 The BCM2836 has a per-cpu interrupt controller for the timer, PMU
5 peripheral (GPU) events, which chain to the BCM2835-style interrupt
10 - compatible: Should be "brcm,bcm2836-l1-intc"
11 - reg: Specifies base physical address and size of the
13 - interrupt-controller: Identifies the node as an interrupt controller
14 - #interrupt-cells: Specifies the number of cells needed to encode an
26 8: GPU_FAST
32 compatible = "brcm,bcm2836-l1-intc";
34 interrupt-controller;
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| /Documentation/RCU/ |
| D | rcubarrier.rst | 8 RCU (read-copy update) is a synchronization mechanism that can be thought
9 of as a replacement for read-writer locking (among other things), but with
10 very low-overhead readers that are immune to deadlock, priority inversion,
11 and unbounded latency. RCU read-side critical sections are delimited
12 by rcu_read_lock() and rcu_read_unlock(), which, in non-CONFIG_PREEMPT
18 pre-existing readers have finished. These old versions are needed because
20 rather expensive, and RCU is thus best suited for read-mostly situations.
25 pre-existing readers have completed. An updater wishing to delete an
33 But the above code cannot be used in IRQ context -- the call_rcu()
35 rcu_head struct placed within the RCU-protected data structure and
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| /Documentation/driver-api/thermal/ |
| D | intel_powerclamp.rst | 6 - Arjan van de Ven <arjan@linux.intel.com>
7 - Jacob Pan <jacob.jun.pan@linux.intel.com>
12 - Goals and Objectives
15 - Idle Injection
16 - Calibration
19 - Effectiveness and Limitations
20 - Power vs Performance
21 - Scalability
22 - Calibration
23 - Comparison with Alternative Techniques
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| /Documentation/devicetree/bindings/arm/marvell/ |
| D | ap80x-system-controller.txt | 5 7K/8K/931x SoCs. It contains system controllers, which provide several
6 registers giving access to numerous features: clocks, pin-muxing and
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the AP80x system controller
18 -------
24 - 0: reference clock of CPU cluster 0
25 - 1: reference clock of CPU cluster 1
26 - 2: fixed PLL at 1200 Mhz
27 - 3: MSS clock, derived from the fixed PLL
31 - compatible: must be one of:
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| /Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 collection of features that give more granular control over CPU performance.
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
47 # intel-speed-select --help
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| /Documentation/ia64/ |
| D | err_inject.rst | 39 #cpu, loop, interval, err_type_info, err_struct_info, err_data_buffer
41 # cpu: logical cpu number the error will be inject in.
50 #corrected, data cache, hier-2, physical addr(assigned by tool code).
55 #corrected, data cache, hier-2, physical addr(assigned by tool code).
60 #recoverable, DTR0, hier-2.
111 #define ERR_DATA_BUFFER_SIZE 3 // Three 8-byte.
114 #define PATH_FORMAT "/sys/devices/system/cpu/cpu%d/err_inject/"
121 int log_info(int cpu, const char *fmt, ...)
128 sprintf(fn, "%d.log", cpu);
132 return -1;
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| D | irq-redir.rst | 10 that described in Documentation/core-api/irq/irq-affinity.rst for i386 systems.
13 IRQ target is one particular CPU and cannot be a mask of several
14 CPUs. Only the first non-zero bit is taken into account.
20 The target CPU has to be specified as a hexadecimal CPU mask. The
21 first non-zero bit is the selected CPU. This format has been kept for
25 interrupts to CPU #3 (logical CPU number) (2^3=0x08)::
27 echo "8" >/proc/irq/41/smp_affinity
29 Set the default route for IRQ number 41 to CPU 6 in lowest priority
38 gives the target CPU mask for the specified interrupt vector. If the CPU
49 IO-SAPIC interrupts are initialized with CPU#0 as their default target
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| /Documentation/devicetree/bindings/nios2/ |
| D | nios2.txt | 11 - compatible: Compatible property value should be "altr,nios2-1.0".
12 - reg: Contains CPU index.
13 - interrupt-controller: Specifies that the node is an interrupt controller
14 - #interrupt-cells: Specifies the number of cells needed to encode an
16 - clock-frequency: Contains the clock frequency for CPU, in Hz.
17 - dcache-line-size: Contains data cache line size.
18 - icache-line-size: Contains instruction line size.
19 - dcache-size: Contains data cache size.
20 - icache-size: Contains instruction cache size.
21 - altr,pid-num-bits: Specifies the number of bits to use to represent the process
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| /Documentation/hwmon/ |
| D | smsc47m192.rst | 10 Addresses scanned: I2C 0x2c - 0x2d
23 - Hartmut Rick <linux@rick.claranet.de>
25 - Special thanks to Jean Delvare for careful checking
30 -----------
33 of the SMSC LPC47M192 and compatible Super-I/O chips.
35 These chips support 3 temperature channels and 8 voltage inputs
36 as well as CPU voltage VID input.
42 Voltages and temperatures are measured by an 8-bit ADC, the resolution
52 bit 4 of the encoded CPU voltage. This means that you either get
53 a +12V voltage measurement or a 5 bit CPU VID, but not both.
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| D | w83793.rst | 10 Addresses scanned: I2C 0x2c - 0x2f
15 - Yuan Mu (Winbond Electronics)
16 - Rudolf Marek <r.marek@assembler.cz>
20 -----------------
36 -----------
42 6 remote temperatures, up to 8 sets of PWM fan controls, SmartFan
44 sets of 6-pin CPU VID input.
48 voltage0-2 is 2mV, resolution of voltage3/4/5 is 16mV, 8mV for voltage6,
49 24mV for voltage7/8. Temp1-4 have a 0.25 degree Celsius resolution,
50 temp5-6 have a 1 degree Celsiis resolution.
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| /Documentation/virt/kvm/ |
| D | nested-vmx.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 ---------
10 On Intel processors, KVM uses Intel's VMX (Virtual-Machine eXtensions)
15 The "Nested VMX" feature adds this missing capability - of running guest
25 https://www.usenix.org/events/osdi10/tech/full_papers/Ben-Yehuda.pdf
29 -----------
31 Single-level virtualization has two levels - the host (KVM) and the guests.
38 ------------------
41 the "nested=1" option to the kvm-intel module.
44 emulated CPU type (qemu64) does not list the "VMX" CPU feature, so it must be
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| /Documentation/devicetree/bindings/opp/ |
| D | allwinner,sun50i-h6-operating-points.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner H6 CPU OPP Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 For some SoCs, the CPU frequency subset and voltage value of each
18 sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
23 const: allwinner,sun50i-h6-operating-points
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| /Documentation/devicetree/bindings/rng/ |
| D | sparc_sun_oracle_rng.txt | 4 - reg : base address to sample from
5 - compatible : should contain one of the following
7 - 'SUNW,n2-rng' for Niagara 2 Platform (SUN UltraSPARC T2 CPU)
8 - 'SUNW,vf-rng' for Victoria Falls Platform (SUN UltraSPARC T2 Plus CPU)
9 …- 'SUNW,kt-rng' for Rainbow/Yosemite Falls Platform (SUN SPARC T3/T4), (UltraSPARC KT/Niagara 3 - …
11 - 'ORCL,m4-rng' for SPARC T5/M5
12 - 'ORCL,m7-rng' for SPARC T7/M7
15 /* linux LDOM on SPARC T5-2 */
18 rng-#units: 00000002
19 compatible: 'ORCL,m4-rng'
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| /Documentation/devicetree/bindings/sound/ |
| D | st,sti-asoc-card.txt | 3 The sti ASoC Sound Card can be used, for all sti SoCs using internal sti-sas
8 Documentation/devicetree/bindings/sound/simple-card.yaml.
10 1) sti-uniperiph-dai: audio dai device.
11 ---------------------------------------
14 - compatible: "st,stih407-uni-player-hdmi", "st,stih407-uni-player-pcm-out",
15 "st,stih407-uni-player-dac", "st,stih407-uni-player-spdif",
16 "st,stih407-uni-reader-pcm_in", "st,stih407-uni-reader-hdmi",
18 - st,syscfg: phandle to boot-device system configuration registers
20 - clock-names: name of the clocks listed in clocks property in the same order
22 - reg: CPU DAI IP Base address and size entries, listed in same
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| D | nokia,rx51.txt | 4 - compatible: Should contain "nokia,n900-audio"
5 - nokia,cpu-dai: phandle for the McBSP node
6 - nokia,audio-codec: phandles for the main TLV320AIC3X node and the
8 - nokia,headphone-amplifier: phandle for the TPA6130A2 node
9 - tvout-selection-gpios: GPIO for tvout selection
10 - jack-detection-gpios: GPIO for jack detection
11 - eci-switch-gpios: GPIO for ECI (Enhancement Control Interface) switch
12 - speaker-amplifier-gpios: GPIO for speaker amplifier
17 compatible = "nokia,n900-audio";
19 nokia,cpu-dai = <&mcbsp2>;
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| /Documentation/devicetree/bindings/ipmi/ |
| D | aspeed-kcs-bmc.txt | 5 used to perform in-band IPMI communication with their host.
9 - compatible : should be one of
10 "aspeed,ast2400-kcs-bmc"
11 "aspeed,ast2500-kcs-bmc"
12 - interrupts : interrupt generated by the controller
13 - kcs_chan : The LPC channel number in the controller
14 - kcs_addr : The host CPU IO map address
18 - compatible : should be one of
19 "aspeed,ast2400-kcs-bmc-v2"
20 "aspeed,ast2500-kcs-bmc-v2"
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| /Documentation/devicetree/bindings/net/ |
| D | hisilicon-hns-nic.txt | 4 - compatible: "hisilicon,hns-nic-v1" or "hisilicon,hns-nic-v2".
5 "hisilicon,hns-nic-v1" is for hip05.
6 "hisilicon,hns-nic-v2" is for Hi1610 and Hi1612.
7 - ae-handle: accelerator engine handle for hns,
9 see Documentation/devicetree/bindings/net/hisilicon-hns-dsaf.txt
10 - port-id: is the index of port provided by DSAF (the accelerator). DSAF can
11 connect to 8 PHYs. Port 0 to 1 are both used for administration purpose. They
16 In NIC mode of DSAF, all 6 PHYs are taken as ethernet ports to the CPU. The
17 port-id can be 2 to 7. Here is the diagram:
18 +-----+---------------+
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| /Documentation/admin-guide/ |
| D | perf-security.rst | 7 --------
19 1. System hardware and software configuration data, for example: a CPU
30 faults, CPU migrations), architectural hardware performance counters
31 (PMC) [8]_ and machine specific registers (MSR) [9]_ that provide
50 -------------------------------
66 independently enabled and disabled on per-thread basis for processes and
100 ---------------------------------
102 Mechanisms of capabilities, privileged capability-dumb files [6]_ and
115 # ls -alhF
116 -rwxr-xr-x 2 root root 11M Oct 19 15:12 perf
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