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/Documentation/devicetree/bindings/sound/
Dnvidia,tegra30-ahub.txt1 NVIDIA Tegra30 AHUB (Audio Hub)
4 - compatible : For Tegra30, must contain "nvidia,tegra30-ahub". For Tegra114,
5 must contain "nvidia,tegra114-ahub". For Tegra124, must contain
6 "nvidia,tegra124-ahub". Otherwise, must contain "nvidia,<chip>-ahub",
9 the AHUB's register blocks.
10 - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
12 - interrupts : Should contain AHUB interrupt
58 AHUB client modules need to specify the IDs of their CIFs (Client InterFaces).
59 For RX CIFs, the numbers indicate the register number within AHUB routing
61 For TX CIFs, the numbers indicate the bit position within the AHUB routing
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Dnvidia,tegra210-ahub.yaml4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
7 title: Tegra210 AHUB Device Tree Bindings
10 The Audio Hub (AHUB) comprises a collection of hardware accelerators
22 pattern: "^ahub@[0-9a-f]*$"
27 - nvidia,tegra210-ahub
28 - nvidia,tegra186-ahub
30 - const: nvidia,tegra194-ahub
31 - const: nvidia,tegra186-ahub
40 const: ahub
77 ahub@702d0800 {
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Dnvidia,tegra30-i2s.txt15 - nvidia,ahub-cif-ids : The list of AHUB CIF IDs for this port, rx (playback)
16 first, tx (capture) second. See nvidia,tegra30-ahub.txt for values.
23 nvidia,ahub-cif-ids = <4 4>;
Dnvidia,tegra210-admaif.yaml10 ADMAIF is the interface between ADMA and AHUB. Each ADMA channel
11 that sends/receives data to/from AHUB must interface through an
12 ADMAIF channel. ADMA channel sending data to AHUB pairs with ADMAIF
13 Tx channel and ADMA channel receiving data from AHUB pairs with
Dnvidia,tegra210-i2s.yaml42 modules in AHUB. The Tegra I2S driver sets this clock rate as