Searched full:armv7 (Results 1 – 11 of 11) sorted by relevance
| /Documentation/devicetree/bindings/arm/ |
| D | pmu.yaml | 83 Indicates that the ARMv7 Secure Debug Enable Register
85 any setup required that is only possible in ARMv7 secure
86 state. If not present the ARMv7 SDER will not be touched,
90 not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
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| /Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 28 - arm,armv7-timer
31 - arm,armv7-timer
78 supported for 32-bit systems which follow the ARMv7 architected reset
103 "arm,armv7-timer";
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| D | arm,arch_timer_mmio.yaml | 23 - arm,armv7-timer-mem
52 supported for 32-bit systems which follow the ARMv7 architected reset
102 compatible = "arm,armv7-timer-mem";
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| D | arm,armv7m-systick.txt | 3 ARMv7-M includes a system timer, known as SysTick. Current driver only
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| /Documentation/devicetree/bindings/arm/mstar/ |
| D | mstar,l3bridge.yaml | 8 title: MStar/SigmaStar Armv7 SoC l3bridge
14 MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface
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| /Documentation/arm/ |
| D | marvel.rst | 114 Sheeva ARMv7 compatible PJ4B
165 Sheeva ARMv7 compatible Dual-core or Quad-core PJ4B-MP
258 Sheeva ARMv7 comatible Quad-core PJ4C
281 ARMv7 compatible
318 - Core: ARMv7 compatible Sheeva PJ4 core
358 - Core: ARMv7 compatible Sheeva PJ4 88sv581x core
362 - Core: Dual-core ARMv7 compatible Sheeva PJ4C core
365 - Core: ARMv7 compatible Sheeva PJ4 core
368 - Core: Dual-core ARMv7 compatible Sheeva PJ4B-MP core
371 - Core: quad-core ARMv7 Cortex-A7
[all …]
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| D | swp_emulation.rst | 7 ARMv7 multiprocessing extensions introduce the ability to disable these
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| D | kernel_mode_neon.rst | 10 '-march=armv7-a -mfpu=neon -mfloat-abi=softfp'
92 '-march=armv7-a -mfpu=neon -mfloat-abi=softfp';
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| /Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 49 - ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
53 but ARMv7-a defines "PCSR samples are offset by a value that depends on the
54 instruction set state". For ARMv7-a, the driver checks furthermore if CPU
56 detailed description for offset is in ARMv7-a ARM (ARM DDI 0406C.b) chapter
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| /Documentation/devicetree/bindings/iommu/ |
| D | samsung,sysmmu.yaml | 18 ARMv7 translation tables with minimum set of page properties including access
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| /Documentation/arm/samsung/ |
| D | bootloader-interface.rst | 15 SBOOT or any other firmware for ARMv7 and ARMv8 initializing the board before
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