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/Documentation/devicetree/bindings/cpu/
Dcpu-topology.txt2 CPU topology binding description
20 For instance in a system where CPUs support SMT, "cpu" nodes represent all
22 In systems where SMT is not supported "cpu" nodes represent all cores present
25 CPU topology bindings allow one to associate cpu nodes with hierarchical groups
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
32 The cpu nodes, as per bindings defined in [4], represent the devices that
35 A topology description containing phandles to cpu nodes that are not compliant
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
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/Documentation/ABI/testing/
Dsysfs-devices-system-cpu1 What: /sys/devices/system/cpu/
5 A collection of both global and individual CPU attributes
7 Individual CPU attributes are contained in subdirectories
8 named by the kernel's logical CPU number, e.g.:
10 /sys/devices/system/cpu/cpu#/
12 What: /sys/devices/system/cpu/kernel_max
13 /sys/devices/system/cpu/offline
14 /sys/devices/system/cpu/online
15 /sys/devices/system/cpu/possible
16 /sys/devices/system/cpu/present
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/Documentation/driver-api/
Dio_ordering.rst18 CPU A: spin_lock_irqsave(&dev_lock, flags)
19 CPU A: val = readl(my_status);
20 CPU A: ...
21 CPU A: writel(newval, ring_ptr);
22 CPU A: spin_unlock_irqrestore(&dev_lock, flags)
24 CPU B: spin_lock_irqsave(&dev_lock, flags)
25 CPU B: val = readl(my_status);
26 CPU B: ...
27 CPU B: writel(newval2, ring_ptr);
28 CPU B: spin_unlock_irqrestore(&dev_lock, flags)
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/Documentation/translations/zh_CN/
Dio_ordering.txt35 CPU A: spin_lock_irqsave(&dev_lock, flags)
36 CPU A: val = readl(my_status);
37 CPU A: ...
38 CPU A: writel(newval, ring_ptr);
39 CPU A: spin_unlock_irqrestore(&dev_lock, flags)
41 CPU B: spin_lock_irqsave(&dev_lock, flags)
42 CPU B: val = readl(my_status);
43 CPU B: ...
44 CPU B: writel(newval2, ring_ptr);
45 CPU B: spin_unlock_irqrestore(&dev_lock, flags)
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/Documentation/scheduler/
Dsched-bwc.rst5 [ This document only discusses CPU bandwidth control for SCHED_NORMAL.
9 specification of the maximum CPU bandwidth available to a group or hierarchy.
13 microseconds of CPU time. That quota is assigned to per-cpu run queues in
21 is transferred to cpu-local "silos" on a demand basis. The amount transferred
26 Quota and period are managed within the cpu subsystem via cgroupfs.
28 cpu.cfs_quota_us: the total available run-time within a period (in microseconds)
29 cpu.cfs_period_us: the length of a period (in microseconds)
30 cpu.stat: exports throttling statistics [explained further below]
34 cpu.cfs_period_us=100ms
35 cpu.cfs_quota=-1
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Dsched-capacity.rst5 1. CPU Capacity
16 CPU capacity is a measure of the performance a CPU can reach, normalized against
17 the most performant CPU in the system. Heterogeneous systems are also called
18 asymmetric CPU capacity systems, as they contain CPUs of different capacities.
20 Disparity in maximum attainable performance (IOW in maximum CPU capacity) stems
32 CPU performance is usually expressed in Millions of Instructions Per Second
36 capacity(cpu) = work_per_hz(cpu) * max_freq(cpu)
41 Two different capacity values are used within the scheduler. A CPU's
43 attainable performance level. A CPU's ``capacity`` is its ``capacity_orig`` to
47 Note that a CPU's ``capacity`` is solely intended to be used by the CFS class,
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/Documentation/devicetree/bindings/arm/
Dcpu-capacity.txt15 2 - CPU capacity definition
18 CPU capacity is a number that provides the scheduler information about CPUs
25 CPU capacities are obtained by running a suitable benchmark. This binding makes
29 * A "single-threaded" or CPU affine benchmark
30 * Divided by the running frequency of the CPU executing the benchmark
31 * Not subject to dynamic frequency scaling of the CPU
36 CPU capacities are obtained by running the Dhrystone benchmark on each CPU at
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
48 maximum frequency available to the cpu is then used to calculate the capacity
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Dcpus.yaml14 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15 defining properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
34 cpus and cpu node bindings definition
38 requires the cpus and cpu nodes to be present and contain the properties
55 bits [11:0] in CPU ID register.
60 required and matches the CPU MPIDR[23:0] register
192 - brcm,bcm11351-cpu-method
218 cpu-release-addr:
228 cpu-idle-states:
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Didle-states.yaml19 to power gating) according to OS PM policies. The CPU states representing the
25 power states an ARM CPU can be put into are identified by the following list:
33 The power states described in the SBSA document define the basic CPU states on
54 The following diagram depicts the CPU execution phases and related timing
67 Diagram 1: CPU idle state execution phases
69 EXEC: Normal CPU execution.
74 (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
84 EXIT: Period during which the CPU is brought back to operational
94 CPU being able to execute normal code again. If not specified, this is assumed
99 An idle CPU requires the expected min-residency time to select the most
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Dcoresight-cpu-debug.txt1 * CoreSight CPU Debug Component:
3 CoreSight CPU debug component are compliant with the ARMv8 architecture
7 and eventually the debug module connects with CPU for debugging. And the
9 to sample CPU program counter, secure state and exception level, etc;
10 usually every CPU has one dedicated debug module to be connected.
14 - compatible : should be "arm,coresight-cpu-debug"; supplemented with
26 processor core is clocked by the internal CPU clock, so it
27 is enabled with CPU clock by default.
29 - cpu : the CPU phandle the debug module is affined to. Do not assume it
38 constrain idle states to ensure registers in the CPU power
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/Documentation/x86/
Dtopology.rst84 A per-CPU variable containing:
114 CPU.
152 The alternative Linux CPU enumeration depends on how the BIOS enumerates the
154 That has the "advantage" that the logical Linux CPU numbers of threads 0 stay
160 [package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
166 [package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
167 -> [core 1] -> [thread 0] -> Linux CPU 1
171 [package 0] -> [core 0] -> [thread 0] -> Linux CPU 0
172 -> [thread 1] -> Linux CPU 1
173 -> [core 1] -> [thread 0] -> Linux CPU 2
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/Documentation/devicetree/bindings/cpufreq/
Dbrcm,stb-avs-cpu-freq.txt4 A total of three DT nodes are required. One node (brcm,avs-cpu-data-mem)
5 references the mailbox register used to communicate with the AVS CPU[1]. The
6 second node (brcm,avs-cpu-l2-intr) is required to trigger an interrupt on
7 the AVS CPU. The interrupt tells the AVS CPU that it needs to process a
8 command sent to it by a driver. Interrupting the AVS CPU is mandatory for
12 so a driver can react to interrupts generated by the AVS CPU whenever a command
15 [1] The AVS CPU is an independent co-processor that runs proprietary
22 Node brcm,avs-cpu-data-mem
26 - compatible: must include: brcm,avs-cpu-data-mem and
27 should include: one of brcm,bcm7271-avs-cpu-data-mem or
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Dcpufreq-mediatek.txt7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
9 source (usually MAINPLL) when the original CPU PLL is under
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
59 cpu0: cpu@0 {
60 device_type = "cpu";
65 clock-names = "cpu", "intermediate";
69 cpu@1 {
70 device_type = "cpu";
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/Documentation/core-api/
Dcpu_hotplug.rst2 CPU hotplug in the Kernel
18 insertion and removal require support for CPU hotplug.
21 provisioning reasons, or for RAS purposes to keep an offending CPU off
22 system execution path. Hence the need for CPU hotplug support in the
25 A more novel use of CPU-hotplug support is its use today in suspend resume
58 CPU maps
71 after a CPU is available for kernel scheduling and ready to receive
72 interrupts from devices. Its cleared when a CPU is brought down using
74 migrated to another target CPU.
84 You really don't need to manipulate any of the system CPU maps. They should
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Dthis_cpu_ops.rst8 this_cpu operations are a way of optimizing access to per cpu
11 the cpu permanently stored the beginning of the per cpu area for a
14 this_cpu operations add a per cpu variable offset to the processor
15 specific per cpu base and encode that operation in the instruction
16 operating on the per cpu variable.
32 synchronization is not necessary since we are dealing with per cpu
37 Please note that accesses by remote processors to a per cpu area are
69 per cpu area. It is then possible to simply use the segment override
70 to relocate a per cpu relative address to the proper per cpu area for
71 the processor. So the relocation to the per cpu base is encoded in the
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/Documentation/admin-guide/
Dkernel-per-CPU-kthreads.rst2 Reducing OS jitter due to per-cpu kthreads
5 This document lists per-CPU kthreads in the Linux kernel and presents
6 options to control their OS jitter. Note that non-per-CPU kthreads are
7 not listed here. To reduce OS jitter from non-per-CPU kthreads, bind
8 them to a "housekeeping" CPU dedicated to such work.
23 - /sys/devices/system/cpu/cpuN/online: Control CPU N's hotplug state,
26 - In order to locate kernel-generated OS jitter on CPU N:
46 that does not require per-CPU kthreads. This will prevent these
52 3. Rework the eHCA driver so that its per-CPU kthreads are
65 some other CPU.
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Dcputopology.rst2 How CPU topology info is exported via sysfs
5 Export CPU topology info via sysfs. Items (attributes) are similar
7 /sys/devices/system/cpu/cpuX/topology/:
17 the CPU die ID of cpuX. Typically it is the hardware platform's
23 the CPU core ID of cpuX. Typically it is the hardware platform's
92 where they reflect the cpu and cache hierarchy.
97 #define topology_physical_package_id(cpu)
98 #define topology_die_id(cpu)
99 #define topology_core_id(cpu)
100 #define topology_book_id(cpu)
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/Documentation/power/
Dsuspend-and-cpuhotplug.rst2 Interaction of Suspend code (S3) with the CPU hotplug infrastructure
8 I. Differences between CPU hotplug and Suspend-to-RAM
11 How does the regular CPU hotplug code differ from how the Suspend-to-RAM
17 interactions involving the freezer and CPU hotplug and also tries to explain
21 What happens when regular CPU hotplug and Suspend-to-RAM race with each other
66 Common | before taking down the CPU |
79 Disable regular cpu hotplug
99 | Decrease cpu_hotplug_disabled, thereby enabling regular cpu hotplug
117 Regular CPU hotplug call path
121 /sys/devices/system/cpu/cpu*/online
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/Documentation/devicetree/bindings/arm/cpu-enable-method/
Dal,alpine-smp2 Secondary CPU enable-method "al,alpine-smp" binding
17 "al,alpine-cpu-resume" and "al,alpine-nb-service".
20 * Alpine CPU resume registers
22 The CPU resume register are used to define required resume address after
26 - compatible : Should contain "al,alpine-cpu-resume".
32 The System-Fabric Service Registers allow various operation on CPU and
47 cpu@0 {
49 device_type = "cpu";
53 cpu@1 {
55 device_type = "cpu";
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/Documentation/vm/
Dmmu_notifier.rst10 For secondary TLB (non CPU TLB) like IOMMU TLB or device TLB (when device use
11 thing like ATS/PASID to get the IOMMU to walk the CPU page table to access a
41 CPU-thread-0 {try to write to addrA}
42 CPU-thread-1 {try to write to addrB}
43 CPU-thread-2 {}
44 CPU-thread-3 {}
48 CPU-thread-0 {COW_step0: {mmu_notifier_invalidate_range_start(addrA)}}
49 CPU-thread-1 {COW_step0: {mmu_notifier_invalidate_range_start(addrB)}}
50 CPU-thread-2 {}
51 CPU-thread-3 {}
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/Documentation/trace/coresight/
Dcoresight-cpu-debug.rst2 Coresight CPU Debug Module
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
20 to sample CPU program counter, secure state and exception level, etc; usually
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
24 will dump related registers for every CPU; finally this is good for assistant
43 - The driver supports a CPU running in either AArch64 or AArch32 mode. The
54 instruction set state". For ARMv7-a, the driver checks furthermore if CPU
61 state". So on ARMv8 if EDDEVID1.PCSROffset is 0b0010 and the CPU operates
62 in AArch32 state, EDPCSR is not sampled; when the CPU operates in AArch64
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/Documentation/arm/
Dcluster-pm-race-avoidance.rst5 This file documents the algorithm which is used to coordinate CPU and
48 Each cluster and CPU is assigned a state, as follows:
67 The CPU or cluster is not coherent, and is either powered off or
71 The CPU or cluster has committed to moving to the UP state.
76 The CPU or cluster is active and coherent at the hardware
77 level. A CPU in this state is not necessarily being used
81 The CPU or cluster has committed to moving to the DOWN
86 Each CPU has one of these states assigned to it at any point in time.
87 The CPU states are described in the "CPU state" section, below.
95 To help distinguish the CPU states from cluster states in this
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/Documentation/RCU/
Dstallwarn.rst4 Using RCU's CPU Stall Detector
7 This document first discusses what sorts of issues RCU's CPU stall
13 What Causes RCU CPU Stall Warnings?
16 So your kernel printed an RCU CPU stall warning. The next question is
17 "What caused it?" The following problems can result in RCU CPU stall
20 - A CPU looping in an RCU read-side critical section.
22 - A CPU looping with interrupts disabled.
24 - A CPU looping with preemption disabled.
26 - A CPU looping with bottom halves disabled.
28 - For !CONFIG_PREEMPT kernels, a CPU looping anywhere in the kernel
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/Documentation/devicetree/bindings/csky/
Dcpus.txt2 C-SKY CPU Bindings
6 the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
7 defining properties for every cpu.
13 cpus and cpu node bindings definition
18 Description: Container of cpu nodes
33 - cpu node
42 Definition: must be "cpu"
46 Definition: CPU index
62 cpu@0 {
63 device_type = "cpu";
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/Documentation/translations/zh_CN/arm64/
Dbooting.txt41 这个术语来定义在将控制权交给 Linux 内核前 CPU 上执行的所有软件。
153 - 主 CPU 通用寄存器设置
159 - CPU 模式
162 CPU 必须处于 EL2（推荐，可访问虚拟化扩展）或非安全 EL1 模式下。
178 CNTFRQ 必须设定为计时器的频率，且 CNTVOFF 必须设定为对所有 CPU
183 通过内核启动的所有 CPU 在内核入口地址上必须处于相同的一致性域中。
207 以上对于 CPU 模式、高速缓存、MMU、架构计时器、一致性、系统寄存器的
208 必要条件描述适用于所有 CPU。所有 CPU 必须在同一异常级别跳入内核。
210 引导装载程序必须在每个 CPU 处于以下状态时跳入内核入口：
212 - 主 CPU 必须直接跳入内核映像的第一条指令。通过此 CPU 传递的设备树
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