Searched full:cortex (Results 1 – 25 of 80) sorted by relevance
1234
| /Documentation/devicetree/bindings/arm/ |
| D | pmu.yaml | 27 - arm,cortex-a5-pmu
28 - arm,cortex-a7-pmu
29 - arm,cortex-a8-pmu
30 - arm,cortex-a9-pmu
31 - arm,cortex-a12-pmu
32 - arm,cortex-a15-pmu
33 - arm,cortex-a17-pmu
34 - arm,cortex-a32-pmu
35 - arm,cortex-a34-pmu
36 - arm,cortex-a35-pmu
[all …]
|
| D | scu.txt | 3 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
9 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
11 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
17 "arm,cortex-a9-scu"
18 "arm,cortex-a5-scu"
26 compatible = "arm,cortex-a9-scu";
|
| D | cpus.yaml | 119 - arm,cortex-a5
120 - arm,cortex-a7
121 - arm,cortex-a8
122 - arm,cortex-a9
123 - arm,cortex-a12
124 - arm,cortex-a15
125 - arm,cortex-a17
126 - arm,cortex-a32
127 - arm,cortex-a34
128 - arm,cortex-a35
[all …]
|
| D | arm,realview.yaml | 14 11, Cortex A-8 and Cortex A-9 CPUs. This included new features compared to
38 - description: ARM RealView Platform Baseboard for Cortex-A8 (HBI-0178,
40 Cortex CPU family, including a Cortex-A8 test chip.
43 - description: ARM RealView Platform Baseboard Explore for Cortex-A9
44 (HBI-0182 and HBI-0183) was the reference platform for the Cortex-A9
|
| D | arm,vexpress-juno.yaml | 15 multicore Cortex-A class systems. The Versatile Express family contains both
45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
51 - description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores
53 and Jazelle support in the Cortex A5 family. See ARM DUI 0541C.
57 - description: Coretile Express A15x2 (V2P-CA15) has 2 Cortex A15 CPU
63 - description: CoreTile Express A15x4 (V2P-CA15, HBI-0237A) has 4 Cortex
70 - description: Coretile Express A15x2 A7x3 (V2P-CA15_A7) has 2 Cortex A15
71 CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
76 - description: LogicTile Express 20MG (V2F-1XV7) has 2 Cortex A53 CPU
84 AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53
|
| D | idle-states.yaml | 337 compatible = "arm,cortex-a57";
346 compatible = "arm,cortex-a57";
355 compatible = "arm,cortex-a57";
364 compatible = "arm,cortex-a57";
373 compatible = "arm,cortex-a57";
382 compatible = "arm,cortex-a57";
391 compatible = "arm,cortex-a57";
400 compatible = "arm,cortex-a57";
409 compatible = "arm,cortex-a53";
418 compatible = "arm,cortex-a53";
[all …]
|
| D | cpu-capacity.txt | 121 compatible = "arm,cortex-a57";
132 compatible = "arm,cortex-a57";
143 compatible = "arm,cortex-a53";
154 compatible = "arm,cortex-a53";
165 compatible = "arm,cortex-a53";
176 compatible = "arm,cortex-a53";
206 compatible = "arm,cortex-a15";
213 compatible = "arm,cortex-a15";
220 compatible = "arm,cortex-a15";
227 compatible = "arm,cortex-a15";
|
| D | actions.yaml | 18 # The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
36 # The Actions Semi S700 is a quad-core ARM Cortex-A53 SoC.
47 # The Actions Semi S900 is a quad-core ARM Cortex-A53 SoC.
|
| D | calxeda.yaml | 12 Bindings for boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC
13 or Cortex-A15 based ECX-2000 SOCs
|
| /Documentation/devicetree/bindings/timer/ |
| D | arm,twd.txt | 3 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
13 "arm,cortex-a9-twd-timer"
14 "arm,cortex-a5-twd-timer"
38 "arm,cortex-a9-twd-wdt"
39 "arm,cortex-a5-twd-wdt"
|
| D | arm,global_timer.yaml | 13 Cortex-A9 are often associated with a per-core Global timer.
19 - arm,cortex-a5-global-timer
20 - arm,cortex-a9-global-timer
43 compatible = "arm,cortex-a9-global-timer";
|
| /Documentation/translations/zh_CN/arm64/ |
| D | silicon-errata.txt | 63 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
64 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
65 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
66 | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
67 | ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 |
68 | ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 |
69 | ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
70 | ARM | Cortex-A57 | #852523 | N/A |
71 | ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
|
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic.yaml | 30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
45 - arm,cortex-a15-gic
46 - arm,cortex-a7-gic
54 - const: arm,cortex-a15-gic
124 - const: PERIPHCLKEN # for "arm,cortex-a15-gic"
125 - items: # for "arm,cortex-a9-gic"
185 compatible = "arm,cortex-a9-gic";
[all …]
|
| /Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 278 compatible = "arm,cortex-a57";
286 compatible = "arm,cortex-a57";
294 compatible = "arm,cortex-a57";
302 compatible = "arm,cortex-a57";
310 compatible = "arm,cortex-a57";
318 compatible = "arm,cortex-a57";
326 compatible = "arm,cortex-a57";
334 compatible = "arm,cortex-a57";
342 compatible = "arm,cortex-a57";
350 compatible = "arm,cortex-a57";
[all …]
|
| /Documentation/devicetree/bindings/arm/cpu-enable-method/ |
| D | al,alpine-smp | 12 Compatible CPUs: "arm,cortex-a15"
48 compatible = "arm,cortex-a15";
54 compatible = "arm,cortex-a15";
60 compatible = "arm,cortex-a15";
66 compatible = "arm,cortex-a15";
|
| D | nuvoton,npcm750-smp | 10 Compatible CPUs: "arm,cortex-a9"
14 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
26 compatible = "arm,cortex-a9";
35 compatible = "arm,cortex-a9";
|
| /Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-dt.txt | 31 compatible = "arm,cortex-a9";
45 compatible = "arm,cortex-a9";
51 compatible = "arm,cortex-a9";
57 compatible = "arm,cortex-a9";
|
| D | cpufreq-mediatek.txt | 61 compatible = "arm,cortex-a7";
71 compatible = "arm,cortex-a7";
77 compatible = "arm,cortex-a7";
83 compatible = "arm,cortex-a7";
181 compatible = "arm,cortex-a53";
193 compatible = "arm,cortex-a53";
205 compatible = "arm,cortex-a57";
217 compatible = "arm,cortex-a57";
|
| /Documentation/arm/ |
| D | sunxi.rst | 20 * ARM Cortex-A8 based SoCs
47 * Single ARM Cortex-A7 based SoCs
54 * Dual ARM Cortex-A7 based SoCs
71 * Quad ARM Cortex-A7 based SoCs
123 * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
130 * Octa ARM Cortex-A7 based SoCs
141 * Quad ARM Cortex-A53 based SoCs
|
| /Documentation/arm/stm32/ |
| D | stm32f746-overview.rst | 8 The STM32F746 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @216MHz
30 …/www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32f7-serie…
|
| D | stm32f769-overview.rst | 8 The STM32F769 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @216MHz
32 …/www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-pe…
|
| D | stm32mp157-overview.rst | 8 The STM32MP157 is a Cortex-A MPU aimed at various applications.
11 - Dual core Cortex-A7 application core
|
| D | stm32f429-overview.rst | 8 The STM32F429 is a Cortex-M4 MCU aimed at various applications.
11 - ARM Cortex-M4 up to 180MHz with FPU
|
| /Documentation/devicetree/bindings/arm/stm32/ |
| D | st,mlahb.yaml | 15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
17 using different buses (see [2]): balancing the Cortex-M firmware accesses
34 remote Cortex-M processor. Each memory region, is declared with
36 - param 1: device base address (Cortex-M processor address)
|
| /Documentation/devicetree/bindings/arm/ux500/ |
| D | boards.txt | 55 compatible = "arm,cortex-a9-gic";
64 compatible = "arm,cortex-a9-scu";
69 compatible = "arm,cortex-a9-twd-timer";
|
1234