Searched full:dma (Results 1 – 25 of 598) sorted by relevance
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dma.txt | 1 * Freescale DMA Controllers
3 ** Freescale Elo DMA Controller
4 This is a little-endian 4-channel DMA controller, used in Freescale mpc83xx
9 - compatible : must include "fsl,elo-dma"
10 - reg : DMA General Status Register, i.e. DGSR which contains
11 status for all the 4 DMA channels
13 DMA channels and the address space of the DMA controller
15 - interrupts : interrupt specifier for DMA IRQ
17 - DMA channel nodes:
18 - compatible : must include "fsl,elo-dma-channel"
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| /Documentation/devicetree/bindings/dma/ |
| D | fsl-imx-dma.txt | 1 * Freescale Direct Memory Access (DMA) Controller for i.MX
3 This document will only describe differences to the generic DMA Controller and
4 DMA request bindings as described in dma/dma.txt .
6 * DMA controller
9 - compatible : Should be "fsl,<chip>-dma". chip can be imx1, imx21 or imx27
10 - reg : Should contain DMA registers location and length
11 - interrupts : First item should be DMA interrupt, second one is optional and
12 should contain DMA Error interrupt
13 - #dma-cells : Has to be 1. imx-dma does not support anything else.
16 - #dma-channels : Number of DMA channels supported. Should be 16.
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| D | ti-dma-crossbar.txt | 1 Texas Instruments DMA Crossbar (DMA request router)
4 - compatible: "ti,dra7-dma-crossbar" for DRA7xx DMA crossbar
7 - #dma-cells: Should be set to to match with the DMA controller's dma-cells
8 for ti,dra7-dma-crossbar and <3> for ti,am335x-edma-crossbar.
9 - dma-requests: Number of DMA requests the crossbar can receive
10 - dma-masters: phandle pointing to the DMA controller
12 The DMA controller node need to have the following poroperties:
13 - dma-requests: Number of DMA requests the controller can handle
16 - ti,dma-safe-map: Safe routing value for unused request lines
17 - ti,reserved-dma-request-ranges: DMA request ranges which should not be used
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| D | arm-pl330.txt | 1 * ARM PrimeCell PL330 DMA Controller
3 The ARM PrimeCell PL330 DMA controller can move blocks of memory contents
13 - dma-coherent : Present if dma operations are coherent
14 - #dma-cells: must be <1>. used to represent the number of integer
16 - dma-channels: contains the total number of DMA channels supported by the DMAC
17 - dma-requests: contains the total number of DMA requests supported by the DMAC
22 - reset-names: must contain at least "dma", and optional is "dma-ocp".
30 #dma-cells = <1>;
31 #dma-channels = <8>;
32 #dma-requests = <32>;
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| D | mpc512x-dma.txt | 1 * Freescale MPC512x and MPC8308 DMA Controller
3 The DMA controller in Freescale MPC512x and MPC8308 SoCs can move
7 Refer to "Generic DMA Controller and DMA request bindings" in
8 the dma/dma.txt file for a more detailed description of binding.
11 - compatible: should be "fsl,mpc5121-dma" or "fsl,mpc8308-dma";
12 - reg: should contain the DMA controller registers location and length;
13 - interrupt for the DMA controller: syntax of interrupt client node
15 - #dma-cells: the length of the DMA specifier, must be <1>.
16 Each channel of this DMA controller has a peripheral request line,
22 dma0: dma@14000 {
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| D | dma-router.yaml | 4 $id: http://devicetree.org/schemas/dma/dma-router.yaml#
7 title: DMA Router Generic Binding
13 - $ref: "dma-common.yaml#"
16 DMA routers are transparent IP blocks used to route DMA request
17 lines from devices to the DMA controller. Some SoCs (like TI DRA7x)
18 have more peripherals integrated with DMA requests than what the DMA
23 pattern: "^dma-router(@.*)?$"
25 dma-masters:
28 Array of phandles to the DMA controllers the router can direct
31 dma-requests:
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| D | owl-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/owl-dma.yaml#
7 title: Actions Semi Owl SoCs DMA controller
10 The OWL DMA is a general-purpose direct memory access controller capable of
11 supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
18 - $ref: "dma-controller.yaml#"
23 - actions,s900-dma
24 - actions,s700-dma
32 DMA channels.
35 "#dma-cells":
38 dma-channels:
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| D | sprd-dma.txt | 1 * Spreadtrum DMA controller
3 This binding follows the generic DMA bindings defined in dma.txt.
6 - compatible: Should be "sprd,sc9860-dma".
7 - reg: Should contain DMA registers location and length.
9 - #dma-cells: must be <1>. Used to represent the number of integer
11 - #dma-channels : Number of DMA channels supported. Should be 32.
12 - clock-names: Should contain the clock of the DMA controller.
18 apdma: dma-controller@20100000 {
19 compatible = "sprd,sc9860-dma";
22 #dma-cells = <1>;
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| D | brcm,bcm2835-dma.txt | 1 * BCM2835 DMA controller
3 The BCM2835 DMA controller has 16 channels in total.
11 - compatible: Should be "brcm,bcm2835-dma".
12 - reg: Should contain DMA registers location and length.
13 - interrupts: Should contain the DMA interrupts associated
14 to the DMA channels in ascending order.
17 Use "dma-shared-all" for the common interrupt line
18 that is shared by all dma channels.
19 - #dma-cells: Must be <1>, the cell in the dmas property of the
21 - brcm,dma-channel-mask: Bit mask representing the channels
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| D | lpc1850-dmamux.txt | 1 NXP LPC18xx/43xx DMA MUX (DMA request router)
6 - #dma-cells: Should be set to <3>.
7 * 1st cell contain the master dma request signal
11 - dma-requests: Number of DMA requests for the mux
12 - dma-masters: phandle pointing to the DMA controller
14 The DMA controller node need to have the following poroperties:
15 - dma-requests: Number of DMA requests the controller can handle
19 dmac: dma@40002000 {
26 #dma-cells = <2>;
27 dma-channels = <8>;
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| D | moxa,moxart-dma.txt | 1 MOXA ART DMA Controller
3 See dma.txt first
7 - compatible : Must be "moxa,moxart-dma"
11 - #dma-cells : Should be 1, a single cell holding a line request number
15 dma: dma@90500000 {
16 compatible = "moxa,moxart-dma";
19 #dma-cells = <1>;
25 DMA clients connected to the MOXA ART DMA controller must use the format
26 described in the dma.txt file, using a two-cell specifier for each channel:
30 1. A phandle pointing to the DMA controller.
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| D | fsl-mxs-dma.txt | 1 * Freescale MXS DMA
4 - compatible : Should be "fsl,<chip>-dma-apbh" or "fsl,<chip>-dma-apbx"
6 - interrupts : Should contain the interrupt numbers of DMA channels.
8 - #dma-cells : Must be <1>. The number cell specifies the channel ID.
9 - dma-channels : Number of channels supported by the DMA controller
12 - interrupt-names : Name of DMA channel interrupts
19 dma_apbh: dma-apbh@80004000 {
20 compatible = "fsl,imx28-dma-apbh";
30 #dma-cells = <1>;
31 dma-channels = <16>;
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| D | allwinner,sun50i-a64-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/allwinner,sun50i-a64-dma.yaml#
7 title: Allwinner A64 DMA Controller Device Tree Bindings
14 - $ref: "dma-controller.yaml#"
17 "#dma-cells":
23 - const: allwinner,sun50i-a64-dma
24 - const: allwinner,sun50i-h6-dma
26 - const: allwinner,sun8i-r40-dma
27 - const: allwinner,sun50i-a64-dma
48 - "#dma-cells"
54 - dma-channels
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| D | renesas,shdma.txt | 3 Sh-/r-mobile and R-Car systems often have multiple identical DMA controller
4 instances, capable of serving any of a common set of DMA slave devices, using
6 SHDMA DT nodes to be placed under a DMA multiplexer node. All such compatible
7 DMAC instances have the same number of channels and use the same DMA
8 descriptors. Therefore respective DMA DT bindings can also all be placed in the
12 * DMA multiplexer
16 - #dma-cells: should be <1>, see "dmas" property below
19 - dma-channels: number of DMA channels
20 - dma-requests: number of DMA request signals
22 * DMA controller
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| D | k3dma.txt | 1 * Hisilicon K3 DMA controller
3 See dma.txt first
7 - "hisilicon,k3-dma-1.0"
8 - "hisilicon,hisi-pcm-asp-dma-1.0"
9 - reg: Should contain DMA registers location and length.
11 - #dma-cells: see dma.txt, should be 1, para number
12 - dma-channels: physical channels supported
13 - dma-requests: virtual channels supported, each virtual channel
20 dma0: dma@fcd02000 {
21 compatible = "hisilicon,k3-dma-1.0";
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| D | ingenic,dma.yaml | 4 $id: http://devicetree.org/schemas/dma/ingenic,dma.yaml#
7 title: Ingenic SoCs DMA Controller DT bindings
13 - $ref: "dma-controller.yaml#"
18 - ingenic,jz4740-dma
19 - ingenic,jz4725b-dma
20 - ingenic,jz4770-dma
21 - ingenic,jz4780-dma
22 - ingenic,x1000-dma
23 - ingenic,x1830-dma
36 "#dma-cells":
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| D | zxdma.txt | 1 * ZTE ZX296702 DMA controller
4 - compatible: Should be "zte,zx296702-dma"
5 - reg: Should contain DMA registers location and length.
7 - #dma-cells: see dma.txt, should be 1, para number
8 - dma-channels: physical channels supported
9 - dma-requests: virtual channels supported, each virtual channel
16 dma: dma-controller@09c00000{
17 compatible = "zte,zx296702-dma";
21 #dma-cells = <1>;
22 dma-channels = <24>;
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| D | renesas,nbpfaxi.txt | 1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
3 * DMA controller
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
51 #dma-cells = <2>;
52 dma-channels = <8>;
53 dma-requests = <8>;
56 * DMA client
60 dmas and dma-names are required, as described in dma.txt.
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| D | apm-xgene-dma.txt | 1 Applied Micro X-Gene SoC DMA nodes
3 DMA nodes are defined to describe on-chip DMA interfaces in
6 Required properties for DMA interfaces:
7 - compatible: Should be "apm,xgene-dma".
8 - device_type: set to "dma".
11 1st - DMA control and status register address space.
15 - interrupts: DMA has 5 interrupts sources. 1st interrupt is
16 DMA error reporting interrupt. 2nd, 3rd, 4th and 5th interrupts
17 are completion interrupts for each DMA channels.
21 - dma-coherent : Present if dma operations are coherent
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| D | st,stm32-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
7 title: STMicroelectronics STM32 DMA Controller bindings
10 The STM32 DMA is a general-purpose direct memory access controller capable of
11 supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12 DMA clients connected to the STM32 DMA controller must use the format
13 described in the dma.txt file, using a four-cell specifier for each
14 channel: a phandle to the DMA controller plus the following four integer cells:
17 3. A 32bit mask specifying the DMA channel configuration which are device
33 4. A 32bit bitfield value specifying DMA features which are device dependent:
34 -bit 0-1: DMA FIFO threshold selection
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| D | dma-common.yaml | 4 $id: http://devicetree.org/schemas/dma/dma-common.yaml#
7 title: DMA Engine Generic Binding
13 Generic binding to provide a way for a driver using DMA Engine to
14 retrieve the DMA request or channel information that goes from a
15 hardware device to a DMA controller.
20 "#dma-cells":
25 Used to provide DMA controller specific information.
27 dma-channel-mask:
29 Bitmask of available DMA channels in ascending order that are
40 dma-channels:
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-dma.txt | 1 Keystone Navigator DMA Controller
3 This document explains the device tree bindings for the packet dma
4 on keystone devices. The Keystone Navigator DMA driver sets up the dma
8 CRYPTO Engines etc has its own instance of dma hardware. QMSS has also
9 an internal packet DMA module which is used as an infrastructure DMA
12 Navigator DMA cloud layout:
17 |-> DMA instance #0
19 |-> DMA instance #1
23 |-> DMA instance #n
25 Navigator DMA properties:
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| /Documentation/devicetree/bindings/usb/ |
| D | ux500-usb.txt | 11 - dmas : A list of dma channels;
12 dma-controller, event-line, fixed-channel, flags
13 - dma-names : An ordered list of channel names affiliated to the above
25 dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
26 <&dma 38 0 0x0>, /* Logical - MemToDev */
27 <&dma 37 0 0x2>, /* Logical - DevToMem */
28 <&dma 37 0 0x0>, /* Logical - MemToDev */
29 <&dma 36 0 0x2>, /* Logical - DevToMem */
30 <&dma 36 0 0x0>, /* Logical - MemToDev */
31 <&dma 19 0 0x2>, /* Logical - DevToMem */
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| /Documentation/driver-api/ |
| D | dma-buf.rst | 4 The dma-buf subsystem provides the framework for sharing buffers for
5 hardware (DMA) access across multiple device drivers and subsystems, and
11 The three main components of this are: (1) dma-buf, representing a
17 Shared DMA Buffers
20 This document serves as a guide to device-driver writers on what is the dma-buf
23 Any device driver which wishes to be a part of DMA buffer sharing, can do so as
49 Any exporters or users of the dma-buf buffer sharing framework must have a
55 Mostly a DMA buffer file descriptor is simply an opaque object for userspace,
59 - Since kernel 3.12 the dma-buf FD supports the llseek system call, but only
64 If llseek on dma-buf FDs isn't support the kernel will report -ESPIPE for all
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| /Documentation/core-api/ |
| D | dma-isa-lpc.rst | 2 DMA with ISA and LPC devices
7 This document describes how to do DMA transfers using the old ISA DMA
9 uses the same DMA system so it will be around for quite some time.
14 To do ISA style DMA you need to include two headers::
16 #include <linux/dma-mapping.h>
17 #include <asm/dma.h>
19 The first is the generic DMA API used to convert virtual addresses to
20 bus addresses (see :doc:`/core-api/dma-api` for details).
22 The second contains the routines specific to ISA DMA transfers. Since
30 The ISA DMA controller has some very strict requirements on which
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