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/Documentation/ABI/testing/
Dsysfs-bus-coresight-devices-etm3x1 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/enable_source
11 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_idx
18 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_acctype
29 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_range
37 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_single
45 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_start
53 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/addr_stop
61 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_idx
67 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_event
74 What: /sys/bus/coresight/devices/<memory_map>.[etm|ptm]/cntr_val
[all …]
Dsysfs-bus-coresight-devices-etm4x1 What: /sys/bus/coresight/devices/etm<N>/enable_source
11 What: /sys/bus/coresight/devices/etm<N>/cpu
17 What: /sys/bus/coresight/devices/etm<N>/nr_pe_cmp
24 What: /sys/bus/coresight/devices/etm<N>/nr_addr_cmp
31 What: /sys/bus/coresight/devices/etm<N>/nr_cntr
38 What: /sys/bus/coresight/devices/etm<N>/nr_ext_inp
44 What: /sys/bus/coresight/devices/etm<N>/numcidc
51 What: /sys/bus/coresight/devices/etm<N>/numvmidc
58 What: /sys/bus/coresight/devices/etm<N>/nrseqstate
65 What: /sys/bus/coresight/devices/etm<N>/nr_resource
[all …]
/Documentation/trace/coresight/
Dcoresight.rst41 | # ETM # ::::: | # PTM # ::::: ::::: @ |
76 &&&&&&&&& IIIIIII ETM = Embedded Trace Macrocell
89 the basic tracing functionality, enabling components such ETM/PTM, funnel,
101 ETM:
157 replicator 20030000.tpiu 2201c000.ptm 2203c000.etm 2203e000.etm
158 20010000.etb 20040000.funnel 2201d000.ptm 2203d000.etm
210 20010000.etf 20040000.funnel 20100000.stm 22040000.etm
211 22140000.etm 230c0000.funnel 23240000.etm 20030000.tpiu
213 23040000.etm 23140000.etm 23340000.etm
223 e.g, ETM bound to CPU0 is named "etm0"
[all …]
Dcoresight-ect.rst26 # ETM #----------->: : ^ #######
47 defined, unless the CPU/ETM combination is a v8 architecture, in which case
69 The ``cti_cpu<N>`` named CTIs are associated with a CPU, and any ETM used by
Dcoresight-etm4x-reference.rst13 Root: ``/sys/bus/coresight/devices/etm<N>``
65 CPU ID that this ETM is attached to.
635 ETM. The table below describes the bits, using the defines from the driver
700 implemented by the ETM [IDR0]
782 *Note a)* On startup the ETM is programmed to trace the complete address space
/Documentation/devicetree/bindings/arm/
Dcoresight-cti.yaml33 architecture core and optional ETM.
36 between CTI and the CPU core and ETM if present. In the case of a v8
235 # v8 architecturally defined CTI - CPU + ETM connections generated by the
249 # Implementation defined CTI - CPU + ETM connections explicitly defined..
Dcoresight.txt71 * cpu: the cpu phandle this ETM/PTM is affined to. Do not
107 context. This property is currently only used for the ETM 4.x driver.
109 * Optional properties for ETM/PTMs:
111 * arm,cp14: must be present if the system accesses ETM/PTM management
/Documentation/devicetree/bindings/clock/
Dimx23-clock.yaml58 etm 39
Dimx28-clock.yaml75 etm 56
/Documentation/admin-guide/
Dsysrq.rst139 ``v`` Causes ETM buffer dump [ARM-specific]