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Searched full:harts (Results 1 – 4 of 4) sorted by relevance

/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.txt23 a PLIC interrupt property will typically list the HLICs for all present HARTs
Dsifive,plic-1.0.0.yaml17 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
/Documentation/devicetree/bindings/riscv/
Dcpus.yaml23 having four harts.