Searched full:interrupts (Results 1 – 25 of 2188) sorted by relevance
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| /Documentation/devicetree/bindings/scsi/ |
| D | hisilicon-sas.txt | 21 - interrupts : For v1 hw: Interrupts for phys, completion queues, and fatal
22 sources; the interrupts are ordered in 3 groups, as follows:
23 - Phy interrupts
24 - Completion queue interrupts
25 - Fatal interrupts
26 Phy interrupts : Each phy has 3 interrupt sources:
30 The phy interrupts are ordered into groups of 3 per phy
32 Completion queue interrupts : each completion queue has 1
34 The interrupts are ordered in increasing order.
35 Fatal interrupts : the fatal interrupts are ordered as follows:
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| /Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 19 - interrupts : Should be single bit error interrupt, then double bit error
27 - interrupts : Should be single bit error interrupt, then double bit error
41 interrupts = <0 36 1>, <0 37 1>;
48 interrupts = <0 178 1>, <0 179 1>;
63 - interrupts : Should be single bit error interrupt, then double bit error
75 - interrupts : Should be single bit error interrupt, then double bit error
82 - interrupts : Should be single bit error interrupt, then double bit error
90 - interrupts : Should be single bit error interrupt, then double bit error
98 - interrupts : Should be single bit error interrupt, then double bit error
106 - interrupts : Should be single bit error interrupt, then double bit error
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | microchip,pic32-evic.txt | 5 It handles all internal and external interrupts. This controller exists outside
6 of the CPU and is the arbitrator of all interrupts (including interrupts from
9 External interrupts have a software configurable edge polarity. Non external
10 interrupts have a type and polarity that is determined by the source of the
27 internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and
28 IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use
33 - microchip,external-irqs: u32 array of external interrupts with software
56 interrupts = <113 IRQ_TYPE_LEVEL_HIGH>;
65 interrupts = <3 IRQ_TYPE_EDGE_RISING>;
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| D | riscv,cpu-intc.txt | 6 Some of these CSRs are used to control local interrupts connected to the core.
8 interrupts that hart.
11 attached to every HLIC: software interrupts, the timer interrupt, and external
12 interrupts. Software interrupts are used to send IPIs between cores. The
15 interrupts connect all other device interrupts to the HLIC, which are routed
22 need to define how their interrupts map to the relevant HLICs. This means
29 RISC-V supervisor ISA manual, with only the following three interrupts being
36 device interrupts.
40 definition of the hart whose CSRs control these local interrupts.
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| D | ti,pruss-intc.yaml | 15 which are then mapped to 10 possible output interrupts through two levels
18 interrupts (0, 1) are fed exclusively to the internal PRU cores, with the
23 differences on the output interrupts 2 through 9. If this property is not
24 defined, it implies that all the PRUSS INTC output interrupts 2 through 9
29 different possible output interrupts. The additional output interrupts (10
51 interrupts:
55 All the interrupts generated towards the main host processor in the SoC.
76 host_event (target) [cell 3] as the value of the interrupts property in
78 interrupts through 2 levels of many-to-one mapping i.e. events to channel
79 mapping and channels to host interrupts so through this property entire
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| D | interrupts.txt | 7 Nodes that describe devices which generate interrupts must contain an
8 "interrupts" property, an "interrupts-extended" property, or both. If both are
13 which the interrupts are routed; see section 2 below for details.
17 interrupts = <5 0>, <6 0>;
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
25 The "interrupts-extended" property is a special form; useful when a node needs
31 interrupts-extended = <&intc1 5 1>, <&intc2 1 0>;
64 interrupts = <31>; /* Cascaded to vic */
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| D | marvell,orion-intc.txt | 22 /* Dove has 64 first level interrupts */
31 - interrupts: bridge interrupt of the main interrupt controller
36 - marvell,#interrupts: number of interrupts provided by bridge interrupt
45 interrupts = <0>;
46 /* Dove bridge provides 5 interrupts */
47 marvell,#interrupts = <5>;
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| D | snps,dw-apb-ictl.txt | 16 - interrupts: interrupt reference to primary interrupt controller
20 - 0 maps to bit 0 of low interrupts,
21 - 1 maps to bit 1 of low interrupts,
22 - 32 maps to bit 0 of high interrupts,
23 - 33 maps to bit 1 of high interrupts,
24 - (optional) fast interrupts start at 64.
34 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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| D | loongson,htvec.yaml | 14 receiving vectorized interrupts from PCH's interrupt controller.
23 interrupts:
26 description: Eight parent interrupts that receive chained interrupts.
36 - interrupts
52 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
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| D | loongson,htpic.yaml | 17 interrupts from PCH PIC connected on HyperTransport bus.
26 interrupts:
30 Four parent interrupts that receive chained interrupts.
40 - interrupts
56 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
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| D | qca,ath79-cpu-intc.txt | 5 qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.
15 Please refer to interrupts.txt in this directory for details of the common
20 - qca,ddr-wb-channel-interrupts: List of the interrupts needing a write
23 each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt
34 qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
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| /Documentation/devicetree/bindings/usb/ |
| D | twlxxxx-usb.txt | 5 - interrupts : Two interrupt numbers to the cpu should be specified. First
6 interrupt number is the otg interrupt number that raises ID interrupts when
8 usb interrupt number that raises VBUS interrupts when the controller has to
15 interrupts = < 4 10 >;
25 - interrupts : The interrupt numbers to the cpu should be specified. First
26 interrupt number is the otg interrupt number that raises ID interrupts
27 and VBUS interrupts. The second interrupt number is optional.
38 interrupts = < 10 4 >;
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| /Documentation/devicetree/bindings/timer/ |
| D | samsung,exynos4210-mct.yaml | 15 up-counter and can generate 4 interrupts when the counter reaches one of the
38 interrupts:
40 Interrupts should be put in specific order. This is, the local timer
41 interrupts should be specified after the four global timer interrupts
63 - interrupts
71 // interrupts, so two local timer interrupts have been specified,
72 // in addition to four global timer interrupts.
82 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
91 // In this example, the timer interrupts are connected to two separate
92 // interrupt controllers. Hence, an interrupts-extended is needed.
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| D | allwinner,sun4i-a10-timer.yaml | 24 interrupts:
26 List of timers interrupts
40 interrupts:
52 interrupts:
64 interrupts:
76 interrupts:
83 - interrupts
93 interrupts = <22>,
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | dma.txt | 15 - interrupts : interrupt specifier for DMA IRQ
24 - interrupts : interrupt specifier for DMA channel IRQ
26 the interrupts property of the parent node)
36 interrupts = <71 8>;
43 interrupts = <71 8>;
50 interrupts = <71 8>;
57 interrupts = <71 8>;
64 interrupts = <71 8>;
88 - interrupts : interrupt specifier for DMA channel IRQ
103 interrupts = <20 2>;
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| D | mpic-msgr.txt | 18 - interrupts: Specifies a list of interrupt-specifiers which are available
19 for receiving interrupts. Interrupt-specifier consists of two cells: first
26 are allowed to receive interrupts. The value is a bit mask where a set
27 bit at bit 'n' indicates that message register 'n' can receive interrupts.
50 // Message registers 0 and 2 in this block can receive interrupts on
52 interrupts = <0xb0 2 0xb2 2>;
59 // Message registers 0 and 2 in this block can receive interrupts on
61 interrupts = <0xb4 2 0xb6 2>;
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| D | srio-rmu.txt | 56 - interrupts
59 Definition: Specifies the interrupts generated by this device. The
60 value of the interrupts property consists of one interrupt
86 - interrupts
89 Definition: Specifies the interrupts generated by this device. The
90 value of the interrupts property consists of one interrupt
116 - interrupts
119 Definition: Specifies the interrupts generated by this device. The
120 value of the interrupts property consists of one interrupt
140 interrupts = <
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| /Documentation/virt/kvm/devices/ |
| D | s390_flic.rst | 7 FLIC handles floating (non per-cpu) interrupts, i.e. I/O, service and some
8 machine check interruptions. All interrupts are stored in a per-vm list of
9 pending interrupts. FLIC performs operations on this list.
14 - add interrupts (KVM_DEV_FLIC_ENQUEUE)
15 - inspect currently pending interrupts (KVM_FLIC_GET_ALL_IRQS)
16 - purge all pending floating interrupts (KVM_DEV_FLIC_CLEAR_IRQS)
21 - inject adapter interrupts on a specified adapter (KVM_DEV_FLIC_AIRQ_INJECT)
27 the list of pending interrupts.
34 Copies all floating interrupts into a buffer provided by userspace.
42 All interrupts remain pending, i.e. are not deleted from the list of
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| /Documentation/driver-api/serial/ |
| D | driver.rst | 20 responsible for handling interrupts for the port, and providing any
79 Interrupts: caller dependent.
100 Interrupts: locally disabled.
121 Interrupts: locally disabled.
135 Interrupts: locally disabled.
144 Interrupts: locally disabled.
178 Interrupts: caller dependent.
186 Interrupts: locally disabled.
191 Enable the modem status interrupts.
194 interrupts should be disabled when the shutdown method is
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| /Documentation/devicetree/bindings/regulator/ |
| D | qcom-labibb-regulator.yaml | 26 interrupts:
32 - interrupts
39 interrupts:
45 - interrupts
60 interrupts = <0x3 0x0 IRQ_TYPE_EDGE_RISING>;
65 interrupts = <0x3 0x2 IRQ_TYPE_EDGE_RISING>;
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| /Documentation/devicetree/bindings/dma/ |
| D | mmp-dma.txt | 9 - interrupts: Either contain all of the per-channel DMA interrupts
34 interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
47 interrupts = <47>;
58 - interrupts: Either contain all of the per-channel DMA interrupts
70 interrupts = <18 19>;
78 interrupts = <46>;
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| /Documentation/devicetree/bindings/net/ |
| D | samsung-sxgbe.txt | 6 - interrupts: Should contain the SXGBE interrupts
7 These interrupts are ordered by fixed and follows variable
8 trasmit DMA interrupts, receive DMA interrupts and lpi interrupt.
11 index 1 to 25 - 8 variable trasmit interrupts, variable 16 receive interrupts
40 interrupts = <0 209 4>, <0 185 4>, <0 186 4>, <0 187 4>,
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | samsung-pinctrl.txt | 43 interrupts = <0 16 0>;
117 External GPIO and Wakeup Interrupts:
119 The controller supports two types of external interrupts over gpio. The first
120 is the external gpio interrupt and second is the external wakeup interrupts.
121 The difference between the two is that the external wakeup interrupts can be
124 A. External GPIO Interrupts: For supporting external gpio interrupts, the
127 - interrupts: interrupt specifier for the controller. The format and value of
131 of pins supporting GPIO interrupts:
144 B. External Wakeup Interrupts: For supporting external wakeup interrupts, a
148 Only one pin-controller device node can include external wakeup interrupts
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| /Documentation/devicetree/bindings/gpio/ |
| D | brcm,brcmstb-gpio.txt | 30 - interrupts:
33 - interrupts-extended:
34 Alternate form of specifying interrupts and parents that allows for
35 multiple parents. This takes precedence over 'interrupts' and
49 See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
66 interrupts = <0x6>;
78 interrupts = <0x6>;
79 interrupts-extended = <&irq0_aon_intc 0x6>,
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| /Documentation/devicetree/bindings/sound/ |
| D | xlnx,audio-formatter.txt | 8 - interrupt-names: Names specified to list of interrupts in same
9 order mentioned under "interrupts".
13 - interrupts-parent: Phandle for interrupt controller.
14 - interrupts: List of Interrupt numbers.
25 interrupts = <0 104 4>, <0 105 4>;
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