Searched full:lrclk (Results 1 – 14 of 14) sorted by relevance
| /Documentation/devicetree/bindings/pinctrl/ |
| D | cirrus,lochnagar.yaml | 96 codec-aif1-rxdat, codec-aif1-lrclk, codec-aif1-txdat,
97 codec-aif2-bclk, codec-aif2-rxdat, codec-aif2-lrclk,
99 codec-aif3-lrclk, codec-aif3-txdat, dsp-aif1-bclk,
100 dsp-aif1-rxdat, dsp-aif1-lrclk, dsp-aif1-txdat,
101 dsp-aif2-bclk, dsp-aif2-rxdat, dsp-aif2-lrclk,
102 dsp-aif2-txdat, psia1-bclk, psia1-rxdat, psia1-lrclk,
103 psia1-txdat, psia2-bclk, psia2-rxdat, psia2-lrclk,
105 gf-aif3-lrclk, gf-aif3-txdat, gf-aif4-bclk,
106 gf-aif4-rxdat, gf-aif4-lrclk, gf-aif4-txdat,
107 gf-aif1-bclk, gf-aif1-rxdat, gf-aif1-lrclk,
[all …]
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| D | marvell,armada-370-pinctrl.txt | 23 mpp7 7 gpo, ge0(txd1), tdm(dtx), audio(lrclk)
66 mpp45 45 gpo, dev(ad6), audio(lrclk)
91 mpp61 61 gpo, dev(we1), uart1(txd), audio(lrclk)
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| D | marvell,kirkwood-pinctrl.txt | 53 mpp41 41 gpio, audio(lrclk)
139 mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
188 mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
204 mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
253 mpp25 25 gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
274 mpp41 41 gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
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| D | marvell,armada-375-pinctrl.txt | 22 mpp6 6 gpio, dev(ad0), led(p1), audio(lrclk)
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| D | marvell,armada-39x-pinctrl.txt | 71 audio(lrclk) [2], sd0(d5), ua2(rxd)
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| D | marvell,armada-38x-pinctrl.txt | 67 mpp49 49 gpio, sata2(prsnt) [2], sata3(prsnt) [2], tdm(fsync), audio(lrclk), sd0(d5),…
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| /Documentation/devicetree/bindings/sound/ |
| D | wm8960.txt | 12 - wlf,shared-lrclk: This is a boolean property. If present, the LRCM bit of
18 DACLRC pin. If shared-lrclk is present, no need to enable DAC for captrue.
41 wlf,shared-lrclk;
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| D | cs35l33.txt | 54 LRCLK cycles. If this property is set to 0, 1, 2, or 3 then the memory
55 depths will be 1, 4, 8, 16 LRCLK cycles. The default is 16 LRCLK cycles.
57 cirrus,release-rate : The number of consecutive LRCLK periods before
58 allowing release condition tracking updates. The number of LRCLK periods
83 - cirrus,vp-hg-rate : The rate (number of LRCLK periods) at which the VPhg is
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| D | amlogic,axg-tdm-iface.txt | 8 * "lrclk": sample clock
21 clock-names = "mclk", "sclk", "lrclk";
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| D | amlogic,axg-tdm-formatters.txt | 17 * "lrclk" : sample clock
35 "lrclk", "lrclk_sel";
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| D | max9892x.txt | 27 smaller frames sizes such as 32 BCLKS per LRCLK or
28 48 BCLKS per LRCLK.
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| D | sgtl5000.yaml | 54 lrclk-strength:
56 The LRCLK pad strength. Possible values are: 0, 1, 2 and 3 as per the
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| D | cs4271.txt | 24 The CS4271 requires its LRCLK and MCLK to be stable before its RESET
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| /Documentation/sound/soc/ |
| D | dai.rst | 31 (SYSCLK). LRCLK is the same as the sample rate. A few devices support separate
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