Searched full:mhz (Results 1 – 25 of 212) sorted by relevance
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| /Documentation/userspace-api/media/dvb/ |
| D | fe-bandwidth-t.rst | 30 - .. _BANDWIDTH-1-712-MHZ:
34 - 1.712 MHz
38 - .. _BANDWIDTH-5-MHZ:
42 - 5 MHz
46 - .. _BANDWIDTH-6-MHZ:
50 - 6 MHz
54 - .. _BANDWIDTH-7-MHZ:
58 - 7 MHz
62 - .. _BANDWIDTH-8-MHZ:
66 - 8 MHz
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| /Documentation/fb/ |
| D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
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| /Documentation/devicetree/bindings/mfd/ |
| D | omap-usb-host.txt | 40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
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| D | stmpe.txt | 28 0 -> 1.625 MHz 2 || 3 -> 6.5 MHz
29 1 -> 3.25 MHz
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| /Documentation/devicetree/bindings/arm/ |
| D | cpu-capacity.txt | 38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
128 capacity-dmips-mhz = <1024>;
139 capacity-dmips-mhz = <1024>;
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| /Documentation/devicetree/bindings/clock/ |
| D | maxim,max9485.txt | 5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
15 - clocks: Input clock, must provice 27.000 MHz
34 xo-27mhz: xo-27mhz {
45 clocks = <&xo-27mhz>;
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| D | armada3700-periph-clock.txt | 36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
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| /Documentation/admin-guide/pm/ |
| D | intel-speed-select.rst | 154 base-frequency(MHz):2600
168 condition is met, then base frequency of 2600 MHz can be maintained. To
183 base-frequency(MHz):2800
211 This matches the base-frequency (MHz) field value displayed from the
261 Which shows that the base frequency now increased from 2600 MHz at performance
262 level 0 to 2800 MHz at performance level 4. As a result, any workload, which can
263 use fewer CPUs, can see a boost of 200 MHz compared to performance level 0.
402 Specify clos min in MHz with [--min|-n]
403 Specify clos max in MHz with [--max|-m]
412 clos min is not specified, default: 0 MHz
[all …]
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-slave-mt27xx.txt | 16 - <&topckgen CLK_TOP_UNIVPLL1_D2>: specify parent clock 312MHZ.
18 - <&topckgen CLK_TOP_UNIVPLL1_D4>: specify parent clock 156MHZ.
19 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
20 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
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| D | spi-mt65xx.txt | 27 - <&clk26m>: specify parent clock 26MHZ.
28 - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
30 - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
31 - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
32 - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | toshiba,tc358767.txt | 8 clock rate must be 13 MHz, 19.2 MHz, 26 MHz, or 38.4 MHz.
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| /Documentation/devicetree/bindings/net/ |
| D | micrel.txt | 22 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
23 bit selects 25 MHz mode
25 Setting the RMII Reference Clock Select bit enables 25 MHz rather
26 than 50 MHz clock mode.
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| /Documentation/arm/sunxi/ |
| D | clocks.rst | 8 Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the
11 A: The 24MHz oscillator allows gating to save power. Indeed, if gated
18 24MHz 32kHz
29 24Mhz 32kHz
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| /Documentation/devicetree/bindings/regulator/ |
| D | max8952.txt | 15 - 0: 26 MHz
16 - 1: 13 MHz
17 - 2: 19.2 MHz
18 Defaults to 26 MHz if not specified.
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| D | mps,mpq7920.yaml | 37 1.1MHz, 1.65MHz, 2.2MHz, 2.75MHz
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| /Documentation/devicetree/bindings/usb/ |
| D | rockchip,dwc3.txt | 8 "ref_clk" Controller reference clk, have to be 24 MHz
9 "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz
10 "bus_clk" Master/Core clock, have to be >= 62.5 MHz for SS
11 operation and >= 30MHz for HS operation
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| D | qcom,dwc3.yaml | 48 - description: Master/Core clock, has to be >= 125 MHz
49 for SS operation and >= 60MHz for HS operation.
52 in host mode. Its frequency should be 19.2MHz.
71 - description: Must be 19.2MHz (19200000).
72 - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | uctl.txt | 29 /* 12MHz, 24MHz and 48MHz allowed */
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| /Documentation/scsi/ |
| D | dc395x.rst | 48 0 20 Mhz
49 1 12.2 Mhz
50 2 10 Mhz
51 3 8 Mhz
52 4 6.7 Mhz
54 6 5 Mhz
55 7 4 Mhz
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| /Documentation/userspace-api/media/drivers/ |
| D | max2175.rst | 53 samples/sec with a 10.24 MHz sck.
56 samples/sec with a 32.768 MHz sck.
61 samples/sec with a 14.88375 MHz sck.
64 samples/sec with a 7.441875 MHz sck.
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| /Documentation/devicetree/bindings/rtc/ |
| D | brcm,brcmstb-waketimer.txt | 3 The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
10 - clocks : The phandle to the UPG fixed clock (27Mhz domain)
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| /Documentation/devicetree/bindings/media/spi/ |
| D | sony-cxd2880.txt | 6 - spi-max-frequency: Maximum bus speed, should be set to <55000000> (55MHz).
17 spi-max-frequency = <55000000>; /* 55MHz */
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| /Documentation/devicetree/bindings/ufs/ |
| D | ufshcd-pltfrm.txt | 42 specification allows host to provide one of the 4 frequencies (19.2 MHz,
43 26 MHz, 38.4 MHz, 52MHz) for reference clock. This "ref_clk" entry is
45 Defaults to 26 MHz(as per specification) if not specified by host.
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| /Documentation/ABI/testing/ |
| D | sysfs-platform-dptf | 104 (RW) The PCH FIVR (Fully Integrated Voltage Regulator) switching frequency in MHz,
105 when FIVR clock is 19.2MHz or 24MHz.
112 (RW) The PCH FIVR (Fully Integrated Voltage Regulator) switching frequency in MHz,
113 when FIVR clock is 38.4MHz.
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| /Documentation/admin-guide/media/ |
| D | dvb_intro.rst | 107 Seven 177.500 Mhz
108 SBS 184.500 Mhz
109 Nine 191.625 Mhz
110 Ten 219.500 Mhz
111 ABC 226.500 Mhz
112 Channel 31 557.625 Mhz
133 T 177500000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
134 T 184500000 7MHz AUTO AUTO QAM64 8k 1/8 NONE
135 T 191625000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
136 T 219500000 7MHz AUTO AUTO QAM64 8k 1/16 NONE
[all …]
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