Home
last modified time | relevance | path

Searched full:mipi (Results 1 – 25 of 101) sorted by relevance

12345

/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra114-mipi.txt1 NVIDIA Tegra MIPI pad calibration controller
4 - compatible: "nvidia,tegra<chip>-mipi"
9 - mipi-cal
10 - #nvidia,mipi-calibrate-cells: Should be 1. The cell is a bitmask of the pads
13 User nodes need to contain an nvidia,mipi-calibrate property that has a
19 mipi: mipi@700e3000 {
20 compatible = "nvidia,tegra114-mipi";
23 clock-names = "mipi-cal";
24 #nvidia,mipi-calibrate-cells = <1>;
35 nvidia,mipi-calibrate = <&mipi 0x060>;
/Documentation/devicetree/bindings/phy/
Drockchip-mipi-dphy-rx0.yaml4 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
7 title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings
14 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
19 const: rockchip,rk3399-mipi-dphy-rx0
23 - description: MIPI D-PHY ref clock
24 - description: MIPI D-PHY RX0 cfg clock
53 * MIPI D-PHY RX0 use registers in "general register files", it
65 mipi_dphy_rx0: mipi-dphy-rx0 {
66 compatible = "rockchip,rk3399-mipi-dphy-rx0";
Dallwinner,sun6i-a31-mipi-dphy.yaml4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
7 title: Allwinner A31 MIPI D-PHY Controller Device Tree Bindings
19 - const: allwinner,sun6i-a31-mipi-dphy
21 - const: allwinner,sun50i-a64-mipi-dphy
22 - const: allwinner,sun6i-a31-mipi-dphy
53 compatible = "allwinner,sun6i-a31-mipi-dphy";
Damlogic,meson-axg-mipi-pcie-analog.yaml4 $id: "http://devicetree.org/schemas/phy/amlogic,meson-axg-mipi-pcie-analog.yaml#"
7 title: Amlogic AXG shared MIPI/PCIE analog PHY
14 const: amlogic,axg-mipi-pcie-analog-phy
32 compatible = "amlogic,axg-mipi-pcie-analog-phy";
Dmixel,mipi-dsi-phy.txt3 The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
4 MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
9 - "fsl,imx8mq-mipi-dphy"
23 compatible = "fsl,imx8mq-mipi-dphy";
Dsamsung-phy.txt1 Samsung S5P/Exynos SoC series MIPI CSIS/DSIM DPHY
6 - "samsung,s5pv210-mipi-video-phy"
7 - "samsung,exynos5420-mipi-video-phy"
8 - "samsung,exynos5433-mipi-video-phy"
20 For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
22 0 - MIPI CSIS 0,
23 1 - MIPI DSIM 0,
24 2 - MIPI CSIS 1,
25 3 - MIPI DSIM 1.
26 "samsung,exynos5420-mipi-video-phy" and "samsung,exynos5433-mipi-video-phy"
[all …]
/Documentation/devicetree/bindings/display/exynos/
Dexynos_dsim.txt1 Exynos MIPI DSI Master
5 "samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
6 "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
7 "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
8 "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
9 "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
19 - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V)
20 - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
23 according to DSI host bindings (see MIPI DSI bindings [1])
32 Should contain DSI peripheral nodes (see MIPI DSI bindings [1]).
[all …]
Dexynos-mic.txt3 MIC (mobile image compressor) resides between decon and mipi dsi. Mipi dsi is
6 transferred through mipi dsi. The compressed frame data must be uncompressed in
/Documentation/devicetree/bindings/display/rockchip/
Ddw_mipi_dsi_rockchip.txt1 Rockchip specific extensions to the Synopsys Designware MIPI DSI
8 "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
9 "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
10 "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
26 - power-domains: a phandle to mipi dsi power domain node.
35 mipi_dsi: mipi@ff960000 {
38 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
/Documentation/admin-guide/media/
Dimx7.rst16 - MIPI CSI-2 Receiver
20 MIPI Camera Input ---> MIPI CSI-2 --- > |\
36 imx7-mipi-csi2
39 This is the MIPI CSI-2 receiver entity. It has one sink pad to receive the pixel
40 data from MIPI CSI-2 camera sensor. It has one source pad, corresponding to the
48 sensor with a parallel interface or from MIPI CSI-2 virtual channel 0. It has
55 can interface directly with Parallel and MIPI CSI-2 buses. It has 256 x 64 FIFO
76 On this platform an OV2680 MIPI CSI-2 module is connected to the internal MIPI
83 media-ctl -l "'ov2680 1-0036':0 -> 'imx7-mipi-csis.0':0[1]"
84 media-ctl -l "'imx7-mipi-csis.0':1 -> 'csi-mux':1[1]"
[all …]
Dimx.rst32 camera sensors over Parallel, BT.656/1120, and MIPI CSI-2 buses.
66 - MIPI CSI-2 Receiver for camera sensors with the MIPI CSI-2 bus
84 - Supports parallel, BT.565, and MIPI CSI-2 interfaces.
115 MIPI CSI-2 OV5640 sensor, requires the i.MX6 MIPI CSI-2 receiver. But
117 therefore does not require the MIPI CSI-2 receiver, so it is missing in
137 imx6-mipi-csi2
140 This is the MIPI CSI-2 receiver entity. It has one sink pad to receive
141 the MIPI CSI-2 stream (usually from a MIPI CSI-2 camera sensor). It has
142 four source pads, corresponding to the four MIPI CSI-2 demuxed virtual
146 This entity actually consists of two sub-blocks. One is the MIPI CSI-2
[all …]
/Documentation/devicetree/bindings/display/mediatek/
Dmediatek,dsi.txt5 drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-
16 - phys: phandle link to the MIPI D-PHY controller.
22 MIPI TX Configuration Module
25 The MIPI TX configuration module controls the MIPI D-PHY.
28 - compatible: "mediatek,<chip>-mipi-tx"
45 mipi_tx0: mipi-dphy@10215000 {
46 compatible = "mediatek,mt8173-mipi-tx";
/Documentation/devicetree/bindings/media/
Dimx7-mipi-csi2.txt1 Freescale i.MX7 Mipi CSI2
7 This is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is
12 - compatible : "fsl,imx7-mipi-csi2";
14 - interrupts : should contain MIPI CSIS interrupt;
25 provides power to MIPI CSIS core;
48 - data-lanes : (required) an array specifying active physical MIPI-CSI2
56 mipi_csi: mipi-csi@30750000 {
60 compatible = "fsl,imx7-mipi-csi2";
Dimx.txt27 This is the device node for the MIPI CSI-2 Receiver core in the i.MX
28 SoC. This is a Synopsys Designware MIPI CSI-2 host controller core
37 - compatible : "fsl,imx6-mipi-csi2";
39 - clocks : the MIPI CSI-2 receiver requires three clocks: hsi_tx
46 connecting with a MIPI CSI-2 source, and ports 1
49 MIPI CSI-2 virtual channel outputs.
Dsamsung-mipi-csis.txt1 Samsung S5P/Exynos SoC series MIPI CSI-2 receiver (MIPI CSIS)
11 - interrupts : should contain MIPI CSIS interrupt; the format of the
14 - vddio-supply : MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V);
15 - vddcore-supply : MIPI CSIS Core voltage supply (e.g. 1.1V);
42 - data-lanes : (required) an array specifying active physical MIPI-CSI2
/Documentation/driver-api/soundwire/
Dsummary.rst5 SoundWire is a new interface ratified in 2015 by the MIPI Alliance.
58 The MIPI SoundWire specification uses the term 'device' to refer to a Master
69 Programs all the MIPI-defined Slave registers. Represents a SoundWire
77 Driver controlling the Slave device. MIPI-specified registers are controlled
91 Bus implements API to read standard Master MIPI properties and also provides
133 MIPI specification, so Bus calls the "sdw_master_port_ops" callback
141 The MIPI specification requires each Slave interface to expose a unique
154 board-file, ACPI or DT. The MIPI Software specification defines additional
181 For capabilities, Bus implements API to read standard Slave MIPI properties
198 SoundWire MIPI specification 1.1 is available at:
[all …]
/Documentation/devicetree/bindings/display/bridge/
Dtoshiba,tc358762.yaml7 title: Toshiba TC358762 MIPI DSI to MIPI DPI bridge
13 The TC358762 is bridge device which converts MIPI DSI to MIPI DPI.
42 Video port for MIPI DSI input
64 Video port for MIPI DPI output (panel or connector).
Dlontium,lt9611.yaml7 title: Lontium LT9611 2 Port MIPI to HDMI Bridge
34 description: Regulator for 1.8V MIPI phy power.
52 Primary MIPI port-1 for MIPI input
73 Additional MIPI port-2 for MIPI input, used in combination
74 with primary MIPI port-1 to drive higher resolution displays
Dsnps,dw-mipi-dsi.yaml4 $id: http://devicetree.org/schemas/display/bridge/snps,dw-mipi-dsi.yaml#
7 title: Synopsys DesignWare MIPI DSI host controller
13 This document defines device tree properties for the Synopsys DesignWare MIPI
/Documentation/devicetree/bindings/display/
Dallwinner,sun6i-a31-mipi-dsi.yaml4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
7 title: Allwinner A31 MIPI-DSI Controller Device Tree Bindings
16 - allwinner,sun6i-a31-mipi-dsi
17 - allwinner,sun50i-a64-mipi-dsi
74 const: allwinner,sun6i-a31-mipi-dsi
88 const: allwinner,sun50i-a64-mipi-dsi
100 compatible = "allwinner,sun6i-a31-mipi-dsi";
/Documentation/devicetree/bindings/media/xilinx/
Dxlnx,csi2rxss.yaml7 title: Xilinx MIPI CSI-2 Receiver Subsystem
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
16 The subsystem consists of a MIPI D-PHY in slave mode which captures the
17 data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
21 Please note that this bindings includes only the MIPI CSI-2 Rx controller
28 - xlnx,mipi-csi2-rx-subsystem-5.0
121 connects to MIPI CSI-2 source like sensor.
201 compatible = "xlnx,mipi-csi2-rx-subsystem-5.0";
223 /* MIPI CSI-2 Camera handle */
/Documentation/devicetree/bindings/soundwire/
Dqcom,sdw.txt57 More info in MIPI Alliance SoundWire 1.0 Specifications.
64 More info in MIPI Alliance SoundWire 1.0 Specifications.
72 More info in MIPI Alliance SoundWire 1.0 Specifications.
78 More info in MIPI Alliance SoundWire 1.0 Specifications.
87 More info in MIPI Alliance SoundWire 1.0 Specifications.
95 More info in MIPI Alliance SoundWire 1.0 Specifications.
103 More info in MIPI Alliance SoundWire 1.0 Specifications.
112 More info in MIPI Alliance SoundWire 1.0 Specifications.
121 More info in MIPI Alliance SoundWire 1.0 Specifications.
131 More info in MIPI Alliance SoundWire 1.0 Specifications.
[all …]
/Documentation/devicetree/bindings/media/i2c/
Dtc358743.txt1 * Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
3 The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
4 a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
20 MIPI CSI-2 clock is continuous or non-continuous.
25 For further information on the MIPI CSI-2 endpoint node properties, see
/Documentation/trace/
Dsys-t.rst4 MIPI SyS-T over STP
7 The MIPI SyS-T protocol driver can be used with STM class devices to
11 In order to use the MIPI SyS-T protocol driver with your STM device,
33 Now, with the MIPI SyS-T protocol driver, each policy node in the
52 MIPI SyS-T message header. It is off by default as the STP already
62 * [1] https://www.mipi.org/specifications/sys-t
/Documentation/ABI/testing/
Dconfigfs-stp-policy-p_sys-t8 tagged with this UUID in the MIPI SyS-T packet stream, to
17 Include payload length in the MIPI SyS-T header, boolean.
28 MIPI SyS-T packet metadata, if this many milliseconds have

12345