| /Documentation/devicetree/bindings/misc/ |
| D | pvpanic-mmio.txt | 1 * QEMU PVPANIC MMIO Configuration bindings
4 MMIO Configuration interface on the "virt" machine.
13 - compatible: "qemu,pvpanic-mmio".
14 - reg: the MMIO region used by the device.
24 pvpanic-mmio@9060000 {
25 compatible = "qemu,pvpanic-mmio";
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| /Documentation/devicetree/bindings/security/tpm/ |
| D | tpm_tis_mmio.txt | 1 Trusted Computing Group MMIO Trusted Platform Module
4 is the standard protocol defined to access the TPM via MMIO. Typically
13 "tcg,tpm-tis-mmio". Valid chip strings are:
15 - reg: The location of the MMIO registers, should be at least 0x5000 bytes
21 compatible = "atmel,at97sc3204", "tcg,tpm-tis-mmio";
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| /Documentation/devicetree/bindings/virtio/ |
| D | mmio.txt | 7 - compatible: "virtio,mmio" compatibility string
23 does not access memory through an IOMMU, the "virtio,mmio"
30 compatible = "virtio,mmio";
39 compatible = "virtio,mmio";
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| /Documentation/devicetree/bindings/sram/ |
| D | sram.yaml | 30 - mmio-sram
142 compatible = "mmio-sram";
169 // Therefore reserved section sub-nodes have to be added to the mmio-sram
173 compatible = "mmio-sram";
195 // Therefore a reserved section sub-node has to be added to the mmio-sram
198 compatible = "mmio-sram";
212 compatible = "mmio-sram";
226 compatible = "mmio-sram";
244 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
258 compatible = "mmio-sram";
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| /Documentation/devicetree/bindings/mtd/ |
| D | ti,am654-hbmc.txt | 8 MMIO access to attached flash devices
9 - ranges : Address translation from offset within CS to allocated MMIO
17 for mmio-mux binding details
29 compatible = "mmio-mux";
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| /Documentation/admin-guide/hw-vuln/ |
| D | processor_mmio_stale_data.rst | 2 Processor MMIO Stale Data Vulnerabilities
5 Processor MMIO Stale Data Vulnerabilities are a class of memory-mapped I/O
6 (MMIO) vulnerabilities that can expose data. The sequences of operations for
8 vulnerabilities require the attacker to have access to MMIO, many environments
9 are not affected. System environments using virtualization where MMIO access is
22 one microarchitectural buffer or register to another. Processor MMIO Stale Data
49 processors, MMIO primary reads will return 64 bytes of data to the core fill
57 Some endpoint MMIO registers incorrectly handle writes that are smaller than
117 specific variants of Processor MMIO Stale Data vulnerabilities and mitigation
145 is more critical, or the untrusted software has no MMIO access). Note that
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| /Documentation/devicetree/bindings/arm/ |
| D | fw-cfg.txt | 20 - compatible: "qemu,fw-cfg-mmio".
22 - reg: the MMIO region used by the device.
35 compatible = "qemu,fw-cfg-mmio";
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| D | arm-dsu-pmu.txt | 8 The PMU is accessed via CPU system registers and has no MMIO component.
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| /Documentation/virt/kvm/ |
| D | mmu.rst | 305 - access to untranslatable memory (mmio)
312 accessing MMIO and cached MMIO information is available.
316 MMIO sptes" below)
331 - if this is an mmio request, there is no host page; cache the info to
337 - If this is an mmio request, cache the mmio info to the spte and set some
439 Fast invalidation of MMIO sptes
442 As mentioned in "Reaction to events" above, kvm will cache MMIO
448 MMIO sptes have a few spare bits, which are used to store a
453 When KVM finds an MMIO spte, it checks the generation number of the spte.
455 number, it will ignore the cached MMIO information and handle the page
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| /Documentation/userspace-api/accelerators/ |
| D | ocxl.rst | 66 work with, the size of its MMIO areas, ...
70 MMIO chapter
73 OpenCAPI defines two MMIO areas for each AFU:
75 * the global MMIO area, with registers pertinent to the whole AFU.
76 * a per-process MMIO area, which has a fixed size for each context.
158 MMIO areas, the AFU version, and the PASID for the current context.
175 A process can mmap the per-process MMIO area for interactions with the
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| /Documentation/devicetree/bindings/clock/ |
| D | fixed-mmio-clock.txt | 12 - compatible : shall be "fixed-mmio-clock".
22 compatible = "fixed-mmio-clock";
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| /Documentation/devicetree/bindings/bus/ |
| D | baikal,bt1-apb.yaml | 14 Baikal-T1 CPU or DMAC MMIO requests are handled by the AMBA 3 AXI Interconnect
31 - description: APB EHB MMIO registers
32 - description: APB MMIO region with no any device mapped
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| /Documentation/devicetree/bindings/regmap/ |
| D | regmap.txt | 10 Regmap defaults to little-endian register access on MMIO based
18 of the CPU and a byteswap for MMIO registers (e.g. many Broadcom MIPS
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| /Documentation/powerpc/ |
| D | cxl.rst | 99 MMIO space
102 A portion of the accelerator MMIO space can be directly mapped
141 context. Master contexts have access to the full MMIO space an
143 MMIO space an AFU provides.
147 /dev/cxl/afu0.0d. This will have access to the entire MMIO space
251 An AFU may have an MMIO space to facilitate communication with the
252 AFU. If it does, the MMIO space can be accessed via mmap. The size
257 the MMIO space and slave contexts are allowed to only map the per
258 process MMIO space associated with the context. In dedicated
259 process mode the entire MMIO space can always be mapped.
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| D | pci_iov_resource_on_powernv.rst | 13 This document describes the requirement from hardware for PCI MMIO resource
29 state bits (one for MMIO and one for DMA, they get set together but can be
37 The interesting part is how the various PCIe transactions (MMIO, DMA, ...)
96 maps each segment to a PE#. That allows portions of the MMIO space
101 SR-IOV). We basically use the trick of forcing the bridge MMIO windows
222 The IODA2 platform has 16 M64 windows, which are used to map MMIO
223 range to PE#. Each M64 window defines one MMIO range and this range is
232 device's MMIO range.
236 segments [total_VFs, 255] of the M64 window may map to some MMIO range on
287 In IODA2, the MMIO address determines the PE#. If the address is in an M32
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| /Documentation/PCI/ |
| D | pci.rst | 46 - Request MMIO/IOP resources
62 - Release MMIO/IOP resources
182 - Request MMIO/IOP resources
235 Request MMIO/IOP resources
237 Memory (MMIO), and I/O port addresses should NOT be read directly
253 determine MMIO and IO Port resource availability _after_ calling
257 (for MMIO ranges) and request_region() (for IO Port ranges).
353 This guarantee allows the driver to omit MMIO reads to flush
371 - Disable device from responding to MMIO/IO Port addresses
372 - Release MMIO/IO Port resource(s)
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| /Documentation/ABI/testing/ |
| D | sysfs-class-ocxl | 24 Size of the per-process mmio area, as defined in the
31 Size of the global mmio area, as defined in the
38 Give access the global mmio area for the AFU
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| /Documentation/ia64/ |
| D | aliasing.rst | 49 address space because some machines omit some or all of the MMIO
54 This contains only system memory; it does not contain MMIO space.
108 Since the EFI memory map does not describe MMIO on some
115 only allows mmap of the one megabyte "legacy MMIO" area for a
129 This is an MMIO mmap of PCI functions, which additionally may or
147 but could be accessed this way. For example, registers in MMIO
175 mmap of various MMIO regions from /dev/mem by "X" on Intel platforms
178 The EFI memory map may not report these MMIO regions.
226 0x00000-0xFFFFF WB only (no VGA MMIO hole)
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| /Documentation/mhi/ |
| D | mhi.rst | 25 MMIO section in MHI Internals
28 MMIO (Memory mapped IO) consists of a set of registers in the device hardware,
30 Following are the major components of MMIO register space:
160 to access device MMIO register space.
165 programming MMIO registers.
192 the device's MMIO register space. To initialize the MHI in a device,
198 * Programs MHI MMIO registers and sets device into MHI_M0 state.
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| /Documentation/trace/ |
| D | mmiotrace.rst | 10 MMIO tracing was originally developed by Intel around 2003 for their Fault
12 Jeff Muizelaar created a tool for tracing MMIO accesses with the Nouveau
67 Load the driver you want to trace and use it. Mmiotrace will only catch MMIO
126 MMIO accesses are recorded via page faults. Just before __ioremap() returns,
166 zero if it is not recorded. PID is always zero as tracing MMIO accesses
182 - replaying MMIO logs, i.e., re-executing the recorded writes
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | msi.txt | 5 write to an MMIO address.
14 - The doorbell (the MMIO address written to).
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
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| /Documentation/devicetree/bindings/net/ |
| D | mdio-mux-multiplexer.txt | 4 of a mux producer device. The mux producer can be of any type like mmio mux
9 - compatible : should be "mmio-mux-multiplexer"
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| /Documentation/networking/device_drivers/ethernet/freescale/dpaa2/ |
| D | overview.rst | 121 A DPRC has a mappable MMIO region (an MC portal) that can be used
172 supports and a summary of key resources of the object (MMIO regions
180 - MMIO regions: none
190 - MMIO regions: none
200 from the queues themselves. The DPIO provides an MMIO interface to
202 to the DPIO MMIO region, which includes the target queue number.
207 - MMIO regions: queue operations, buffer management
216 - MMIO regions: none
226 - MMIO regions: MC command portal
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| /Documentation/misc-devices/ |
| D | uacce.rst | 108 * @UACCE_QFRT_MMIO: device mmio region
119 The device mmio region is mapped to the hardware mmio space. It is generally
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,wcnss.txt | 18 - qcom,mmio:
95 qcom,mmio = <&pronto>;
|