Home
last modified time | relevance | path

Searched full:mpcore (Results 1 – 7 of 7) sorted by relevance

/Documentation/devicetree/bindings/arm/marvell/
Darmada-380-mpcore-soc-ctrl.txt1 Marvell Armada 38x CA9 MPcore SoC Controller
6 - compatible: Should be "marvell,armada-380-mpcore-soc-ctrl".
9 datasheet for the CA9 MPcore SoC Control registers
11 mpcore-soc-ctrl@20d20 {
12 compatible = "marvell,armada-380-mpcore-soc-ctrl";
/Documentation/devicetree/bindings/arm/
Dscu.txt3 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
9 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
11 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
13 - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
Darm,realview.yaml15 the earlier CPUs such as TrustZone and multicore (MPCore).
32 - description: ARM RealView Platform Baseboard for ARM 11 MPCore
34 multiprocessing with ARM11 using MPCore using symmetric
Darm,vexpress-juno.yaml46 in MPCore configuration in a test chip on the core tile. See ARM
58 cores in a MPCore configuration in a test chip on the core tile. See
71 CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
Dcpus.yaml51 On ARM 11 MPcore based systems this property is
/Documentation/arm/keystone/
Doverview.rst7 Keystone range of SoCs are based on ARM Cortex-A15 MPCore Processors
/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-host1x.txt356 interrupts = <0 65 0x04 /* mpcore syncpt */
357 0 67 0x04>; /* mpcore general */