Searched full:otp (Results 1 – 22 of 22) sorted by relevance
| /Documentation/devicetree/bindings/nvmem/ |
| D | rockchip-otp.txt | 1 Rockchip internal OTP (One Time Programmable) memory device tree bindings
5 - "rockchip,px30-otp" - for PX30 SoCs.
6 - "rockchip,rk3308-otp" - for RK3308 SoCs.
9 - clock-names: Should be "otp", "apb_pclk" and "phy".
17 otp: otp@ff290000 {
18 compatible = "rockchip,px30-otp";
24 clock-names = "otp", "apb_pclk", "phy";
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| D | lpc1850-otp.txt | 1 * NXP LPC18xx OTP memory
3 Internal OTP (One Time Programmable) memory for NXP LPC18xx/43xx devices.
6 - compatible: Should be "nxp,lpc1850-otp"
15 otp: otp@40045000 {
16 compatible = "nxp,lpc1850-otp";
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| D | brcm,ocotp.txt | 1 Broadcom OTP memory controller
8 - reg: Base address of the OTP controller.
13 otp: otp@301c800 {
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| D | st,stm32-romem.yaml | 11 flash, OTP, read-only HW regs... This contains various information such as:
24 - st,stm32f4-otp
32 st,non-secure-otp:
50 compatible = "st,stm32f4-otp";
61 st,non-secure-otp;
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| D | vf610-ocotp.txt | 1 On-Chip OTP Memory for Freescale Vybrid
8 reg : Address and length of OTP controller and fuse map registers
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| D | imx-ocotp.yaml | 7 title: Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
13 This binding represents the on-chip eFuse OTP controller found on
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| D | mxs-ocotp.yaml | 7 title: On-Chip OTP Memory for Freescale i.MX23/i.MX28
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| /Documentation/devicetree/bindings/regulator/ |
| D | palmas-pmic.txt | 3 The tps659038 for the AM57x class have OTP spins that
5 is not a need to add the OTP spins to the palmas driver. The
35 For ti,palmas-pmic - smps12, smps123, smps3 depending on OTP,
50 ti,smps-range - OTP has the wrong range set for the hardware so override
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| /Documentation/devicetree/bindings/net/wireless/ |
| D | mediatek,mt76.txt | 28 - mediatek,eeprom-merge-otp: Merge EEPROM data with OTP data. Can be used on
30 data should be pulled from the OTP ROM
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| /Documentation/devicetree/bindings/mtd/ |
| D | nand-macronix.txt | 17 - randomizer enable: should be "mxic,enable-randomizer-otp"
25 mxic,enable-randomizer-otp;
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| /Documentation/devicetree/bindings/net/ |
| D | microchip,lan78xx.txt | 3 The LAN78XX devices are usually configured by programming their OTP or with
5 The Device Tree properties, if present, override the OTP and EEPROM.
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| /Documentation/devicetree/bindings/mfd/ |
| D | rohm,bd71847-pmic.yaml | 46 # power outputs go down and OTP is reload. At the SNVS state all other logic
49 # state. When a reset is done via SNVS state the PMIC OTP data is not reload.
52 # power outputs will be returned to HW control by OTP loading. Thus the reset
69 # bootloader or OTP) is not touched.
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| D | rohm,bd71837-pmic.yaml | 40 # down and OTP is reload. At the SNVS state all other logic and external
43 # reset is done via SNVS state the PMIC OTP data is not reload. This causes
46 # outputs will be returned to HW control by OTP loading. Thus the reset
63 # bootloader or OTP) is not touched.
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| D | palmas.txt | 31 hardware, if not set will use muxing in OTP.
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| D | da9063.txt | 18 modified to match the chip's OTP settings).
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| D | da9062.txt | 35 modified to match the chip's OTP settings).
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| D | rohm,bd71828-pmic.yaml | 66 Usage of BD71828 GPIO pins can be changed via OTP. This property can be
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| /Documentation/hwmon/ |
| D | sht15.rst | 48 The humidity calibration coefficients are programmed into an OTP memory on the
67 flag to indicate not to reload from OTP (default to false).
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| /Documentation/devicetree/bindings/arm/samsung/ |
| D | exynos-chipid.yaml | 24 is missing in the CHIPID registers or in the OTP memory.
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| /Documentation/ABI/testing/ |
| D | debugfs-turris-mox-rwtm | 9 device's OTP. The message must be exactly 64 bytes
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| /Documentation/devicetree/bindings/input/ |
| D | ti,palmas-pwrbutton.txt | 18 NOTE: This depends on OTP support and POWERHOLD signal configuration
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| /Documentation/w1/slaves/ |
| D | w1_ds2406.rst | 15 These chips also provide 128 bytes of OTP EPROM, but reading/writing it is
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