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/Documentation/riscv/
Dpatch-acceptance.rst1 .. SPDX-License-Identifier: GPL-2.0
7 --------
8 The RISC-V instruction set architecture is developed in the open:
9 in-progress drafts are available for all to review and to experiment
11 during the development process - sometimes in ways that are
13 challenge for RISC-V Linux maintenance. Linux maintainers disapprove
14 of churn, and the Linux development process prefers well-reviewed and
16 principles to the RISC-V-related code that will be accepted for
20 -------------------------
23 "Frozen" or "Ratified" by the RISC-V Foundation. (Developers may, of
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Dboot-image-header.rst2 Boot image header in RISC-V Linux
8 This document only describes the boot image header details for RISC-V Linux.
13 The following 64-byte header is present in decompressed Linux kernel image::
28 ARM64 header. Thus, both ARM64 & RISC-V header can be combined into one common
34 - This header can also be reused to support EFI stub for RISC-V in future. EFI
40 - version field indicate header version number
50 - The "magic" field is deprecated as of version 0.2. In a future
55 - In current header, the flags field has only one field.
61 - Image size is mandatory for boot loader to load kernel image. Booting will
Dindex.rst2 RISC-V architecture
8 boot-image-header
10 patch-acceptance
Dpmu.rst2 Supporting PMUs on RISC-V platforms
8 ------------
10 As of this writing, perf_event-related features mentioned in The RISC-V ISA
23 Counters are just free-running all the time in our case.
33 hardware-extension for M-S-U model machines to write counters directly.
44 -----------------
47 various methods according to perf's internal convention and PMU-specific
53 the minimal and already-implemented logic can be leveraged, or invent his/her
63 -----------------------
72 into bitmap, so that HW-related control registers or counters can directly be
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/Documentation/translations/it_IT/riscv/
Dpatch-acceptance.rst1 .. include:: ../disclaimer-ita.rst
3 :Original: :doc:`../../../riscv/patch-acceptance`
10 ------------
12 L'insieme di istruzioni RISC-V sono sviluppate in modo aperto: le
15 dei nuovi moduli o estensioni possono cambiare in fase di sviluppo - a
18 supporto RISC-V nel kernel Linux. I manutentori Linux non amano
22 relativo all'architettura RISC-V che verrà accettato per l'inclusione
26 -------------------------------------------------------------------------
29 RISC-V li classifica come "Frozen" o "Retified". (Ovviamente, gli
33 In aggiunta, la specifica RISC-V permette agli implementatori di
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/Documentation/devicetree/bindings/interrupt-controller/
Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
2 ---------------------------------------------
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
13 timer interrupt comes from an architecturally mandated real-time timer that is
16 via the platform-level interrupt controller (PLIC).
18 All RISC-V systems that conform to the supervisor ISA specification are
27 - compatible : "riscv,cpu-intc"
28 - #interrupt-cells : should be <1>. The interrupt sources are defined by the
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Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
12 (PLIC) high-level specification in the RISC-V Privileged Architecture
17 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
20 Each interrupt can be enabled on per-context basis. Any context can claim
28 While the PLIC supports both edge-triggered and level-triggered interrupts,
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/Documentation/devicetree/bindings/riscv/
Dcpus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V bindings for 'cpus' DT nodes
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
28 - items:
29 - enum:
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/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
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/Documentation/powerpc/
Dqe_firmware.rst10 I - Software License for Firmware
12 II - Microcode Availability
14 III - Description and Terminology
16 IV - Microcode Programming Details
18 V - Firmware Structure Layout
20 VI - Sample Code for Creating Firmware Files
25 November 30, 2007: Rev 1.0 - Initial version
27 I - Software License for Firmware
34 II - Microcode Availability
41 III - Description and Terminology
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/Documentation/devicetree/bindings/cpu/
Dcpu-topology.txt6 1 - Introduction
12 - socket
13 - cluster
14 - core
15 - thread
18 symmetric multi-threading (SMT) is supported or not.
29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
39 2 - cpu-map node
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
46 - cpu-map node
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/Documentation/parisc/
Dregisters.rst2 Register Usage for Linux/PA-RISC
11 -----------------
15 CR 1-CR 7(undefined) unused
16 CR 8 (Protection ID) per-process value*
23 CR17-CR22 interruption parameters
40 -----------------------------
44 SR4-SR7 set to 0
51 ---------------------------
58 SR4-SR7 Defines short address space for user/kernel
63 ---------------------
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/Documentation/admin-guide/
DREADME.rst11 --------------
14 Linus Torvalds with assistance from a loosely-knit team of hackers across
17 It has all the features you would expect in a modern fully-fledged Unix,
19 loading, shared copy-on-write executables, proper memory management,
22 It is distributed under the GNU General Public License v2 - see the
26 -----------------------------
28 Although originally developed first for 32-bit x86-based PCs (386 or higher),
31 IBM S/390, MIPS, HP PA-RISC, Intel IA-64, DEC VAX, AMD x86-64 Xtensa, and
34 Linux is easily portable to most general-purpose 32- or 64-bit architectures
40 userspace application - this is called UserMode Linux (UML).
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Ddevices.txt1 0 Unnamed devices (e.g. non-device mounts)
11 6 = /dev/core OBSOLETE - replaced by /proc/kcore
18 12 = /dev/oldmem OBSOLETE - replaced by /proc/vmcore
31 2 char Pseudo-TTY masters
37 Pseudo-tty's are named as follows:
40 the 1st through 16th series of 16 pseudo-ttys each, and
44 These are the old-style (BSD) PTY devices; Unix98
106 3 char Pseudo-TTY slaves
112 These are the old-style (BSD) PTY devices; Unix98
115 3 block First MFM, RLL and IDE hard disk/CD-ROM interface
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Dkernel-parameters.txt5 force -- enable ACPI if default was off
6 on -- enable ACPI but allow fallback to DT [arm64]
7 off -- disable ACPI if default was on
8 noirq -- do not use ACPI for IRQ routing
9 strict -- Be less tolerant of platforms that are not
11 rsdt -- prefer RSDT over (default) XSDT
12 copy_dsdt -- copy DSDT to memory
26 If set to vendor, prefer vendor-specific driver
58 Documentation/firmware-guide/acpi/debug.rst for more information about
121 Disable auto-serialization of AML methods
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/Documentation/devicetree/bindings/
Dvendor-prefixes.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/vendor-prefixes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
19 "^(at25|devbus|dmacap|dsa|exynos|fsi[ab]|gpio-fan|gpio|gpmc|hdmi|i2c-gpio),.*": true
21 "^(pinctrl-single|#pinctrl-single|PowerPC),.*": true
22 "^(pl022|pxa-mmc|rcar_sound|rotary-encoder|s5m8767|sdhci),.*": true
23 "^(simple-audio-card|st-plgpio|st-spics|ts),.*": true
38 "^active-semi,.*":
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/Documentation/crypto/
Ddescore-readme.rst1 .. SPDX-License-Identifier: GPL-2.0
13 ------------------------------------------------------------------------------
15 des - fast & portable DES encryption & decryption.
35 .. README,v 1.15 1992/05/20 00:25:32 how E
42 2. PORTABILITY to any byte-addressable host with a 32bit unsigned C type
43 3. Plug-compatible replacement for KERBEROS's low-level routines.
46 register-starved machines. My discussions with Richard Outerbridge,
51 up in a parameterized fashion so it can easily be modified by speed-daemon
58 compile on a SPARCStation 1 (cc -O4, gcc -O2):
60 this code (byte-order independent):
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/Documentation/networking/
Dfilter.rst1 .. SPDX-License-Identifier: GPL-2.0
3 .. _networking-filter:
10 ------------
17 BPF allows a user-space program to attach a filter onto any socket and
42 The biggest user of this construct might be libpcap. Issuing a high-level
43 filter command like `tcpdump -i em1 port 22` passes through the libpcap
45 via SO_ATTACH_FILTER to the kernel. `tcpdump -i em1 port 22 -ddd`
50 qdisc layer, SECCOMP-BPF (SECure COMPuting [1]_), and lots of other places
53 .. [1] Documentation/userspace-api/seccomp_filter.rst
58 architecture for user-level packet capture. In Proceedings of the
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