Searched full:risc (Results 1 – 25 of 30) sorted by relevance
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| /Documentation/riscv/ |
| D | patch-acceptance.rst | 8 The RISC-V instruction set architecture is developed in the open:
13 challenge for RISC-V Linux maintenance. Linux maintainers disapprove
16 principles to the RISC-V-related code that will be accepted for
23 "Frozen" or "Ratified" by the RISC-V Foundation. (Developers may, of
27 Additionally, the RISC-V specification allows implementors to create
29 to go through any review or ratification process by the RISC-V
32 RISC-V extensions, we'll only to accept patches for extensions that
33 have been officially frozen or ratified by the RISC-V Foundation.
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| D | boot-image-header.rst | 2 Boot image header in RISC-V Linux
8 This document only describes the boot image header details for RISC-V Linux.
28 ARM64 header. Thus, both ARM64 & RISC-V header can be combined into one common
34 - This header can also be reused to support EFI stub for RISC-V in future. EFI
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| D | index.rst | 2 RISC-V architecture
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| D | pmu.rst | 2 Supporting PMUs on RISC-V platforms
10 As of this writing, perf_event-related features mentioned in The RISC-V ISA
156 However as of this writing, none of the RISC-V implementations have designed an
173 Reading is not a problem in RISC-V but writing would need some effort, since
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| /Documentation/translations/it_IT/riscv/ |
| D | patch-acceptance.rst | 12 L'insieme di istruzioni RISC-V sono sviluppate in modo aperto: le
18 supporto RISC-V nel kernel Linux. I manutentori Linux non amano
22 relativo all'architettura RISC-V che verrà accettato per l'inclusione
29 RISC-V li classifica come "Frozen" o "Retified". (Ovviamente, gli
33 In aggiunta, la specifica RISC-V permette agli implementatori di
35 attraverso il processo di revisione della fondazione RISC-V. Per
38 state ufficialmente accettate dalla fondazione RISC-V. (Ovviamente,
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.txt | 1 RISC-V Hart-Level Interrupt Controller (HLIC)
4 RISC-V cores include Control Status Registers (CSRs) which are local to each
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
10 The RISC-V supervisor ISA manual specifies three interrupt sources that are
18 All RISC-V systems that conform to the supervisor ISA specification are
29 RISC-V supervisor ISA manual, with only the following three interrupts being
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| D | sifive,plic-1.0.0.yaml | 12 (PLIC) high-level specification in the RISC-V Privileged Architecture
32 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
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| /Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 7 title: RISC-V bindings for 'cpus' DT nodes
14 This document uses some terminology common to the RISC-V community
18 mandated by the RISC-V ISA: a PC and some registers. This
39 Identifies that the hart uses the RISC-V instruction set
45 hart. These values originate from the RISC-V Privileged
56 Identifies the specific RISC-V instruction set architecture
57 supported by the hart. These are documented in the RISC-V
69 # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
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| /Documentation/filesystems/ |
| D | adfs.rst | 25 on a RISC OS Filecore filesystem, but will allow the data within files
45 the RISC OS file type will be added. Default 0.
95 RISC OS file type suffix
98 RISC OS file types are stored in bits 19..8 of the file load address.
100 To enable non-RISC OS systems to be used to store files without losing
104 naming convention is now also used by RISC OS emulators such as RPCEmu.
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| D | ext2.rst | 11 for NetBSD, FreeBSD, the GNU HURD, Windows 95/98/NT, OS/2 and RISC OS.
395 RISC OS client http://www.esw-heim.tu-clausthal.de/~marco/smorbrod/IscaFS/
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| /Documentation/scsi/ |
| D | wd719x.rst | 14 This script downloads and extracts the firmware, creating wd719x-risc.bin and
22 dd if=wd7296a.sys of=wd719x-risc.bin bs=1 skip=5760 count=14336
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| D | advansys.rst | 8 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
10 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
14 Descriptor Block) requests that can be stored in the RISC chip
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| /Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
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| /Documentation/parisc/ |
| D | index.rst | 4 PA-RISC Architecture
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| D | debugging.rst | 2 PA-RISC Debugging
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| D | registers.rst | 2 Register Usage for Linux/PA-RISC
100 The PA-RISC architecture defines 7 registers as "shadow registers".
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| /Documentation/powerpc/ |
| D | qe_firmware.rst | 61 RISC processor. To replace any current microcode, a full QE reset (which
71 QEs with multiple RISC processors, such as the 8360. Splitting the I-RAM
206 must be one and only one 'microcode' structure for each RISC processor.
207 Therefore, this field also represents the number of RISC processors for this
242 For each RISC processor there is one 'microcode' structure. The first
243 'microcode' structure is for the first RISC, and so on.
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| /Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 29 Currently, only ARM/RISC-V intend to use this cpu topology binding but it may be
42 The ARM/RISC-V CPU topology is defined within the cpu-map node, which is a direct
492 Example 3: HiFive Unleashed (RISC-V 64 bit, 4 core system)
551 [3] RISC-V Linux kernel documentation
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| /Documentation/arm/ |
| D | netwinder.rst | 6 to run Linux. It is based around the StrongARM RISC processor,
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | qe.txt | 20 - fsl,qe-num-riscs: define how many RISC engines the QE has.
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| /Documentation/driver-api/ |
| D | device-io.rst | 95 /* disable risc and host interrupts */
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| /Documentation/admin-guide/ |
| D | kernel-parameters.rst | 134 PARISC The PA-RISC architecture is enabled.
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| D | README.rst | 31 IBM S/390, MIPS, HP PA-RISC, Intel IA-64, DEC VAX, AMD x86-64 Xtensa, and
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | ti,pruss.yaml | 17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
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| /Documentation/crypto/ |
| D | descore-readme.rst | 285 - anything more than 12 bits (bad for RISC and CISC)
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