| /Documentation/devicetree/bindings/spi/ |
| D | brcm,spi-bcm-qspi.txt | 1 Broadcom SPI controller
3 The Broadcom SPI controller is a SPI master found on various SOCs, including
4 BRCMSTB (BCM7XXX), Cygnus, NSP and NS2. The Broadcom Master SPI hw IP consits
6 MSPI : SPI master controller can read and write to a SPI slave device
7 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
14 use SPI protocol.
19 Must be <1>, as required by generic SPI binding.
22 Must be <0>, also as required by generic SPI binding.
26 "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on BRCMSTB SoCs
27 "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi" : Second Instance of MSPI
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| D | spi-mt65xx.txt | 1 Binding for MTK SPI controller
5 - mediatek,mt2701-spi: for mt2701 platforms
6 - mediatek,mt2712-spi: for mt2712 platforms
7 - mediatek,mt6589-spi: for mt6589 platforms
8 - mediatek,mt6765-spi: for mt6765 platforms
9 - mediatek,mt7622-spi: for mt7622 platforms
10 - "mediatek,mt7629-spi", "mediatek,mt7622-spi": for mt7629 platforms
11 - mediatek,mt8135-spi: for mt8135 platforms
12 - mediatek,mt8173-spi: for mt8173 platforms
13 - mediatek,mt8183-spi: for mt8183 platforms
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| D | qcom,spi-qup.txt | 1 Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
6 SPI in master mode supports up to 50MHz, up to four chip selects, programmable
11 "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
12 "qcom,spi-qup-v2.1.1" for 8974 and later
13 "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
23 address on the SPI bus. Should be set to 1.
27 - spi-max-frequency: Specifies maximum SPI clock frequency,
29 Documentation/devicetree/bindings/spi/spi-bus.txt
32 The gpios will be referred to as reg = <index> in the SPI child
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| D | nvidia,tegra114-spi.txt | 1 NVIDIA Tegra114 SPI controller.
4 - compatible : For Tegra114, must contain "nvidia,tegra114-spi".
5 Otherwise, must contain '"nvidia,<chip>-spi", "nvidia,tegra114-spi"' where
7 - reg: Should contain SPI registers location and length.
8 - interrupts: Should contain SPI interrupts.
10 - spi
14 - spi
24 - spi-max-frequency: Definition as per
25 Documentation/devicetree/bindings/spi/spi-bus.txt
29 Tegra SPI master with respect to outgoing Tegra SPI master clock.
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| D | spi-controller.yaml | 4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
7 title: SPI Controller Generic Binding
13 SPI busses can be described with a node for the SPI controller device
14 and a set of child nodes for each SPI slave on the bus. The system SPI
15 controller may be described for use in SPI master mode or in SPI slave mode,
20 pattern: "^spi(@.*|-[0-9a-f])*$"
50 spi-slave:
53 The SPI controller acts as a slave, instead of a master.
59 - spi-slave
76 Compatible of the SPI device.
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| D | spi-samsung.txt | 1 * Samsung SPI Controller
3 The Samsung SPI controller is used to interface with various devices such as flash
4 and display controllers using the SPI communication interface.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
12 - samsung,exynos5433-spi: for exynos5433 compatible controllers
13 - samsung,exynos7-spi: for exynos7 platforms <DEPRECATED>
27 - clocks: specifies the clock IDs provided to the SPI controller; they are
32 the devices the names must be "spi", "spi_busclkN" (where N is determined by
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| D | spi-lantiq-ssc.txt | 1 Lantiq Synchronous Serial Controller (SSC) SPI master driver
4 - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
5 "intel,lgm-spi"
6 - #address-cells: see spi-bus.txt
7 - #size-cells: see spi-bus.txt
8 - reg: address and length of the spi master registers
18 - clocks: spi clock phandle
19 - num-cs: see spi-bus.txt, set to 8 if unset
25 spi: spi@e100800 {
26 compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
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| D | spi-bcm63xx.txt | 1 Binding for Broadcom BCM6348/BCM6358 SPI controller
4 - compatible: must contain one of "brcm,bcm6348-spi", "brcm,bcm6358-spi".
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandle of the SPI clock.
8 - clock-names: has to be "spi".
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
16 Child nodes as per the generic SPI binding.
20 spi@10000800 {
21 compatible = "brcm,bcm6368-spi", "brcm,bcm6358-spi";
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| D | snps,dw-apb-ssi.yaml | 4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
13 - $ref: "spi-controller.yaml#"
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
44 - description: Generic DW SPI Controller
48 - description: Microsemi Ocelot/Jaguar2 SoC SPI Controller
51 - mscc,ocelot-spi
52 - mscc,jaguar2-spi
54 - description: Microchip Sparx5 SoC SPI Controller
55 const: microchip,sparx5-spi
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| D | icpdas-lp8841-spi-rtc.txt | 1 * ICP DAS LP-8841 SPI Controller for RTC
4 memory register, which acts as an SPI master device.
17 - compatible: should be "icpdas,lp8841-spi-rtc"
21 Requirements to SPI slave nodes:
25 - The spi slave node should claim the following flags which are
26 required by the spi controller.
28 - spi-3wire: The master itself has only 3 wire. It cannor work in
31 - spi-cs-high: DS-1302 has active high chip select line. The master
34 - spi-lsb-first: DS-1302 requires least significant bit first
40 spi@901c {
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| D | qcom,spi-geni-qcom.txt | 1 GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
4 (an output FIFO and an input FIFO) for serial peripheral interface (SPI)
7 SPI in master mode supports up to 50MHz, up to four chip selects, programmable
11 - compatible: Must contain "qcom,geni-spi".
12 - reg: Must contain SPI register location and length.
13 - interrupts: Must contain SPI controller interrupts.
17 the SPI bus.
20 SPI Controller nodes must be child of GENI based Qualcomm Universal
24 SPI slave nodes must be children of the SPI master node and conform to SPI bus
25 binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.
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| D | spi-rockchip.yaml | 4 $id: http://devicetree.org/schemas/spi/spi-rockchip.yaml#
7 title: Rockchip SPI Controller
10 The Rockchip SPI controller is used to interface with various devices such
11 as flash and display controllers using the SPI communication interface.
14 - $ref: "spi-controller.yaml#"
23 - const: rockchip,rk3036-spi
24 - const: rockchip,rk3066-spi
25 - const: rockchip,rk3228-spi
26 - const: rockchip,rv1108-spi
29 - rockchip,px30-spi
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| D | spi-sprd.txt | 1 Spreadtrum SPI Controller
4 - compatible: Should be "sprd,sc9860-spi".
5 - reg: Offset and length of SPI controller register space.
6 - interrupts: Should contain SPI interrupt.
8 "spi" for SPI clock,
9 "source" for SPI source (parent) clock,
10 "enable" for SPI module enable clock.
14 address on the SPI bus. Should be set to 1.
18 dma-names: Should contain names of the SPI used DMA channel.
19 dmas: Should contain DMA channels and DMA slave ids which the SPI used
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| D | spi-fsl-lpspi.yaml | 4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
7 title: Freescale Low Power SPI (LPSPI) for i.MX
13 - $ref: "/schemas/spi/spi-controller.yaml#"
18 - fsl,imx7ulp-spi
19 - fsl,imx8qxp-spi
29 - description: SoC SPI per clock
30 - description: SoC SPI ipg clock
37 fsl,spi-only-use-cs1-sel:
39 spi common code does not support use of CS signals discontinuously.
58 spi@40290000 {
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| D | spi-davinci.txt | 1 Davinci SPI controller device bindings
10 address on the SPI bus. Should be set to 1.
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
20 - ti,davinci-spi-intr-line: interrupt line used to connect the SPI
26 - clocks: spi clk phandle
35 and an args specifier containing the SPI device id
45 SPI slave nodes can contain the following properties.
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| D | spi-xlp.txt | 1 SPI Master controller for Netlogic XLP MIPS64 SOCs
4 Currently this SPI controller driver is supported for the following
9 - compatible : Should be "netlogic,xlp832-spi".
11 on the SPI bus.
14 - clocks : Phandle of the spi clock
17 SPI slave nodes must be children of the SPI master node and can contain
18 properties described in Documentation/devicetree/bindings/spi/spi-bus.txt.
22 spi: xlp_spi@3a100 {
23 compatible = "netlogic,xlp832-spi";
36 spi-max-frequency = <40000000>;
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| D | microchip,spi-pic32.txt | 1 Microchip PIC32 SPI Master controller
4 - compatible: Should be "microchip,pic32mzda-spi".
6 - interrupts: Should contain all three spi interrupts in sequence
9 - clocks: Phandle of the clock generating SPI clock on the bus.
12 See: Documentation/devicetree/bindings/spi/spi-bus.txt
18 named "spi-tx" for transmit and named "spi-rx" for receive.
22 spi1: spi@1f821000 {
23 compatible = "microchip,pic32mzda-spi";
33 dma-names = "spi-rx", "spi-tx";
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| D | spi-sifive.yaml | 4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
7 title: SiFive SPI controller
15 - $ref: "spi-controller.yaml#"
20 - const: sifive,fu540-c000-spi
24 Should be "sifive,<chip>-spi" and "sifive,spi<version>".
26 "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
28 SPI v0 IP block with no chip integration tweaks.
31 SPI RTL that corresponds to the IP block version numbers can be found here -
32 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi
37 - description: SPI registers region
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| /Documentation/devicetree/bindings/mtd/ |
| D | aspeed-smc.txt | 2 * Aspeed SPI Flash Memory Controller
5 three chip selects, two of which are always of SPI type and the third
6 can be SPI or NOR type flash. These bindings only describe SPI.
8 The two SPI flash memory controllers in the AST2500 each support two
14 "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
16 "aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
27 The child nodes are the SPI flash modules which must have a compatible
28 property as specified in bindings/mtd/jedec,spi-nor.txt
30 Optionally, the child node can contain properties for SPI mode (may be
32 - spi-max-frequency - max frequency of spi bus
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| D | nxp-spifi.txt | 1 * NXP SPI Flash Interface (SPIFI)
3 NXP SPIFI is a specialized SPI interface for serial Flash devices.
4 It supports one Flash device with 1-, 2- and 4-bits width in SPI
21 The SPI Flash must be a child of the SPIFI node and must have a
22 compatible property as specified in bindings/mtd/jedec,spi-nor.txt
25 - spi-cpol : Controller only supports mode 0 and 3 so either
26 both spi-cpol and spi-cpha should be present or
28 - spi-cpha : See above
29 - spi-rx-bus-width : Used to select how many pins that are used
32 See bindings/spi/spi-bus.txt for more information.
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| /Documentation/devicetree/bindings/net/ |
| D | qca,qca7000.txt | 4 be configured either as SPI or UART slave. This configuration is done by
7 (a) Ethernet over SPI
9 In order to use the QCA7000 as SPI device it must be defined as a child of a
10 SPI master in the device tree.
14 - reg : Should specify the SPI chip select
18 - spi-cpha : Must be set
19 - spi-cpol : Must be set
22 - spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at.
24 are invalid. Missing the property will set the SPI
26 - qca,legacy-mode : Set the SPI data transfer of the QCA7000 to legacy mode.
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| /Documentation/devicetree/bindings/iio/resolver/ |
| D | ad2s90.txt | 7 - reg: SPI chip select number for the device
8 - spi-max-frequency: set maximum clock frequency, must be 830000
9 - spi-cpol and spi-cpha:
10 Either SPI mode (0,0) or (1,1) must be used, so specify none or both of
11 spi-cpha, spi-cpol.
14 Documentation/devicetree/bindings/spi/spi-bus.txt
20 implemented in the spi code, to satisfy it, SCLK's period should be at most
28 spi-max-frequency = <830000>;
29 spi-cpol;
30 spi-cpha;
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | ti-adc084s021.txt | 5 - reg : SPI chip select number for the device
7 - spi-cpol : Per spi-bus bindings
8 - spi-cpha : Per spi-bus bindings
9 - spi-max-frequency : Per spi-bus bindings
16 spi-cpol;
17 spi-cpha;
18 spi-max-frequency = <16000000>;
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| /Documentation/driver-api/ |
| D | spi.rst | 1 Serial Peripheral Interface (SPI)
4 SPI is the "Serial Peripheral Interface", widely used with embedded
8 line, and a "Master In, Slave Out" (MISO) data line. SPI is a full
15 The SPI bus facilities listed here provide a generalized interface to
16 declare SPI busses and devices, manage them according to the standard
18 only "master" side interfaces are supported, where Linux talks to SPI
20 to support implementing SPI slaves would necessarily look different.)
26 SPI shift register (maximizing throughput). Such drivers bridge between
27 whatever bus they sit on (often the platform bus) and SPI, and expose
28 the SPI side of their device as a :c:type:`struct spi_controller
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| /Documentation/driver-api/mtd/ |
| D | spi-nor.rst | 2 SPI NOR framework
8 SPI bus controllers (drivers/spi/) only deal with streams of bytes; the bus
11 arbitrary streams of bytes, but rather are designed specifically for SPI NOR.
14 find the right LUT sequence. Unfortunately, the SPI subsystem has no notion of
15 opcodes, addresses, or data payloads; a SPI controller simply knows to send or
18 details of the SPI NOR protocol.
23 This framework just adds a new layer between the MTD and the SPI bus driver.
24 With this new layer, the SPI NOR controller driver does not depend on the
33 SPI bus driver
35 SPI NOR chip
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