Searched full:sram (Results 1 – 25 of 62) sorted by relevance
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| /Documentation/devicetree/bindings/sram/ |
| D | sram.yaml | 4 $id: http://devicetree.org/schemas/sram/sram.yaml#
7 title: Generic on-chip SRAM
15 Each child of the sram node specifies a region of reserved memory. Each
25 pattern: "^sram(@.*)?"
30 - mmio-sram
32 - rockchip,rk3288-pmu-sram
40 SRAM clock.
50 Should translate from local addresses within the sram to bus addresses.
54 The flag indicating, that SRAM memory region has not to be remapped
59 "^([a-z]*-)?sram(-section)?@[a-f0-9]+$":
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| D | allwinner,sun4i-a10-system-control.yaml | 4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
14 The SRAM controller found on most Allwinner devices is represented
15 by a regular node for the SRAM controller itself, with sub-nodes
16 representing the SRAM handled by the SRAM controller.
27 - const: allwinner,sun4i-a10-sram-controller
42 - const: allwinner,sun50i-a64-sram-controller
59 "^sram@[a-z0-9]+":
64 const: mmio-sram
67 "^sram-section?@[a-f0-9]+$":
73 - const: allwinner,sun4i-a10-sram-a3-a4
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | cache_sram.txt | 1 * Freescale PQ3 and QorIQ based Cache SRAM
5 as SRAM. This cache SRAM representation in the device
10 - compatible : should be "fsl,p2020-cache-sram"
11 - fsl,cache-sram-ctlr-handle : points to the L2 controller
12 - reg : offset and length of the cache-sram.
16 cache-sram@fff00000 {
17 fsl,cache-sram-ctlr-handle = <&L2>;
19 compatible = "fsl,p2020-cache-sram";
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| /Documentation/devicetree/bindings/crypto/ |
| D | mv_cesa.txt | 9 region. Can also contain an entry for the SRAM attached to the CESA,
12 - reg-names: "regs". Can contain an "sram" entry, but this representation
17 - marvell,crypto-srams: phandle to crypto SRAM definitions
20 - marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
21 specified the whole SRAM is used (2KB)
31 marvell,crypto-sram-size = <0x600>;
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| D | marvell-cesa.txt | 13 region. Can also contain an entry for the SRAM attached to the CESA,
16 - reg-names: "regs". Can contain an "sram" entry, but this representation
26 - marvell,crypto-srams: phandle to crypto SRAM definitions
29 - marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
30 specified the whole SRAM is used (2KB)
43 marvell,crypto-sram-size = <0x600>;
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | mpu.txt | 14 - sram: Phandle to the ocmcram node
17 - pm-sram: Phandles to ocmcram nodes to be used for power management.
20 data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
52 pm-sram = <&pm_sram_code
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| /Documentation/devicetree/bindings/arm/ |
| D | juno,scpi.txt | 4 Juno SRAM and Shared Memory for SCPI
8 - compatible : should be "arm,juno-sram-ns" for Non-secure SRAM
13 - reg : The base offset and size of the reserved area with the SRAM
14 - compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
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| D | arm,scpi.txt | 59 SRAM and Shared Memory for SCPI
62 A small area of SRAM is reserved for SCPI communication between application
65 The properties should follow the generic mmio-sram description found in [3]
70 - reg : The base offset and size of the reserved area with the SRAM
71 - compatible : should be "arm,scp-shmem" for Non-secure SRAM based
112 [3] Documentation/devicetree/bindings/sram/sram.yaml
117 sram: sram@50000000 {
118 compatible = "arm,juno-sram-ns", "mmio-sram";
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| D | amlogic,scpi.txt | 8 AMLOGIC SRAM and Shared Memory for SCPI
12 - compatible : should be "amlogic,meson-gxbb-sram"
17 - compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared
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| D | arm,scmi.txt | 109 SRAM and Shared Memory for SCMI
112 A small area of SRAM is reserved for SCMI communication between application
115 The properties should follow the generic mmio-sram description found in [4]
120 - reg : The base offset and size of the reserved area with the SRAM
121 - compatible : should be "arm,scmi-shmem" for Non-secure SRAM based
128 [4] Documentation/devicetree/bindings/sram/sram.yaml
134 sram@50000000 {
135 compatible = "mmio-sram";
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| /Documentation/devicetree/bindings/net/ |
| D | marvell-orion-net.txt | 43 - marvell,tx-sram-addr: address of transmit descriptor buffer located in SRAM.
44 - marvell,tx-sram-size: size of transmit descriptor buffer located in SRAM.
46 - marvell,rx-sram-addr: address of receive descriptor buffer located in SRAM.
47 - marvell,rx-sram-size: size of receive descriptor buffer located in SRAM.
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| D | allwinner,sun4i-a10-emac.yaml | 29 allwinner,sram:
30 description: Phandle to the device SRAM
39 - allwinner,sram
51 allwinner,sram = <&emac_sram 1>;
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| D | marvell-neta-bm.txt | 8 - internal-mem: a phandle to BM internal SRAM definition.
38 - internal SRAM node:
41 compatible = "mmio-sram";
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| /Documentation/devicetree/bindings/clock/ |
| D | hi6220-clock.txt | 28 - hisilicon,hi6220-clk-sram: phandle to the syscon managing the SoC internal sram;
29 the driver need use the sram to pass parameters for frequency change.
44 hisilicon,hi6220-clk-sram = <&sram>;
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ingenic,vpu.yaml | 27 - description: sram registers
34 - const: sram
69 <0x132f0000 0x7000>; /* SRAM */
70 reg-names = "aux", "tcsm0", "tcsm1", "sram";
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| D | mtk,scp.txt | 10 regions, SRAM and CFG.
12 regions. These should be named "sram" & "cfg".
33 reg-names = "sram", "cfg";
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| D | ti,k3-dsp-rproc.yaml | 76 sram:
81 phandles to one or more reserved on-chip SRAM regions. The regions
82 should be defined as child nodes of the respective SRAM node, and
84 Documentation/devicetree/bindings/sram/sram.yaml
95 - description: Address and Size of the L2 SRAM internal memory region
113 - description: Address and Size of the L2 SRAM internal memory region
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| /Documentation/devicetree/bindings/media/ |
| D | allegro.txt | 14 length of the memory mapped sram
15 - reg-names: must include "regs" and "sram"
26 reg-names = "regs", "sram";
37 reg-names = "regs", "sram";
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| D | allwinner,sun4i-a10-video-engine.yaml | 46 allwinner,sram:
48 description: Phandle to the device SRAM
65 - allwinner,sram
83 allwinner,sram = <&ve_sram 1>;
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| /Documentation/devicetree/bindings/fsi/ |
| D | fsi-master-ast-cf.txt | 19 - aspeed,sram = <phandle>; : Reference to the SRAM node.
34 aspeed,sram = <&sram>;
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| /Documentation/devicetree/bindings/memory-controllers/ti/ |
| D | emif.txt | 32 - sram : Phandles for generic sram driver nodes,
35 data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
76 sram = <&pm_sram_code
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| /Documentation/devicetree/bindings/bus/ |
| D | allwinner,sun50i-a64-de2.yaml | 33 allwinner,sram:
35 The SRAM that needs to be claimed to access the display engine
59 - allwinner,sram
68 allwinner,sram = <&de2_sram 1>;
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| /Documentation/devicetree/bindings/mailbox/ |
| D | mailbox.txt | 41 sram: sram@50000000 {
42 compatible = "mmio-sram";
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | pl353-smc.txt | 4 interfaces.i.e NAND and SRAM/NOR interfaces.
32 0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region
33 0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region
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| /Documentation/devicetree/bindings/mtd/ |
| D | microchip,mchp23k256.txt | 1 * MTD SPI driver for Microchip 23K256 (and similar) serial SRAM
12 spi-sram@0 {
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