Home
last modified time | relevance | path

Searched full:sifive (Results 1 – 17 of 17) sorted by relevance

/Documentation/devicetree/bindings/spi/
Dspi-sifive.yaml4 $id: http://devicetree.org/schemas/spi/spi-sifive.yaml#
7 title: SiFive SPI controller
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
20 - const: sifive,fu540-c000-spi
21 - const: sifive,spi0
24 Should be "sifive,<chip>-spi" and "sifive,spi<version>".
26 "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated
27 onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive
[all …]
/Documentation/devicetree/bindings/pwm/
Dpwm-sifive.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/pwm/pwm-sifive.yaml#
8 title: SiFive PWM controller
11 - Yash Shah <yash.shah@sifive.com>
12 - Sagar Kadam <sagar.kadam@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
16 Unlike most other PWM controllers, the SiFive PWM controller currently
23 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/pwm
28 - const: sifive,fu540-c000-pwm
29 - const: sifive,pwm0
[all …]
/Documentation/devicetree/bindings/timer/
Dsifive,clint.yaml4 $id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
7 title: SiFive Core Local Interruptor
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
26 - const: sifive,fu540-c000-clint
27 - const: sifive,clint0
30 Should be "sifive,<chip>-clint" and "sifive,clint<version>".
32 "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
33 onto the SiFive FU540 chip, and "sifive,clint0" for the SiFive
35 Please refer to sifive-blocks-ip-versioning.txt for details
53 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
/Documentation/devicetree/bindings/serial/
Dsifive-serial.yaml4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
20 - const: sifive,fu540-c000-uart
21 - const: sifive,uart0
24 Should be something similar to "sifive,<chip>-uart"
26 and "sifive,uart<version>" for the general UART IP
32 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
[all …]
/Documentation/devicetree/bindings/sifive/
Dsifive-blocks-ip-versioning.txt1 DT compatible string versioning for SiFive open-source IP blocks
4 strings for open-source SiFive IP blocks. HDL for these IP blocks
7 https://github.com/sifive/sifive-blocks
10 in the form "sifive,<ip-block-name><integer version number>".
12 An example is "sifive,uart0" from:
14 https://github.com/sifive/sifive-blocks/blob/v1.0/src/main/scala/devices/uart/UART.scala#L43
23 "sifive,uart0" to indicate that their driver is compatible with the
25 upstream sifive-blocks commits. It is expected that most drivers will
30 "sifive,fu540-c000-uart". This way, if SoC-specific
33 IP block-specific compatible string (such as "sifive,uart0") should
[all …]
/Documentation/devicetree/bindings/riscv/
Dsifive.yaml4 $id: http://devicetree.org/schemas/riscv/sifive.yaml#
7 title: SiFive SoC-based boards
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
14 SiFive SoC-based boards
22 - sifive,hifive-unleashed-a00
23 - const: sifive,fu540-c000
24 - const: sifive,fu540
Dsifive-l2-cache.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
8 title: SiFive L2 Cache Controller
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Yash Shah <yash.shah@sifive.com>
13 - Paul Walmsley <paul.walmsley@sifive.com>
16 The SiFive Level 2 Cache Controller is used to provide access to fast copies
29 - sifive,fu540-c000-ccache
37 - const: sifive,fu540-c000-ccache
85 compatible = "sifive,fu540-c000-ccache", "cache";
Dcpus.yaml10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
30 - sifive,rocket0
31 - sifive,e5
32 - sifive,e51
33 - sifive,u54-mc
34 - sifive,u54
35 - sifive,u5
98 // Example 1: SiFive Freedom U540G Development Kit
105 compatible = "sifive,rocket0", "riscv";
[all …]
/Documentation/devicetree/bindings/dma/
Dsifive,fu540-c000-pdma.yaml4 $id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml#
7 title: SiFive Unleashed Rev C000 Platform DMA
10 - Green Wan <green.wan@sifive.com>
11 - Palmer Debbelt <palmer@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
15 Platform DMA is a DMA engine of SiFive Unleashed. It supports 4
23 https://static.dev.sifive.com/FU540-C000-v1.0.pdf
28 - const: sifive,fu540-c000-pdma
51 compatible = "sifive,fu540-c000-pdma";
/Documentation/devicetree/bindings/gpio/
Dsifive,gpio.yaml4 $id: http://devicetree.org/schemas/gpio/sifive,gpio.yaml#
7 title: SiFive GPIO controller
10 - Yash Shah <yash.shah@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
16 - const: sifive,fu540-c000-gpio
17 - const: sifive,gpio0
55 #include <dt-bindings/clock/sifive-fu540-prci.h>
57 compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
/Documentation/devicetree/bindings/interrupt-controller/
Dsifive,plic-1.0.0.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
33 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
35 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
38 - Sagar Kadam <sagar.kadam@sifive.com>
39 - Paul Walmsley <paul.walmsley@sifive.com>
45 - const: sifive,fu540-c000-plic
46 - const: sifive,plic-1.0.0
[all …]
Driscv,cpu-intc.txt49 compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";
/Documentation/devicetree/bindings/clock/sifive/
Dfu540-prci.yaml2 # Copyright (C) 2020 SiFive, Inc.
5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
11 - Sagar Kadam <sagar.kadam@sifive.com>
12 - Paul Walmsley <paul.walmsley@sifive.com>
18 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
27 const: sifive,fu540-c000-prci
56 compatible = "sifive,fu540-c000-prci";
/Documentation/devicetree/bindings/net/
Dmacb.txt18 Use "sifive,fu540-c000-gem" for SiFive FU540-C000 SoC.
21 For "sifive,fu540-c000-gem", second range is required to specify the
/Documentation/devicetree/bindings/i2c/
Di2c-ocores.txt6 "sifive,fu540-c000-i2c", "sifive,i2c0"
8 FU540-C000 SoC. Please refer to sifive-blocks-ip-versioning.txt
/Documentation/devicetree/bindings/cpu/
Dcpu-topology.txt497 compatible = "sifive,fu540g", "sifive,fu500";
498 model = "sifive,hifive-unleashed-a00";
525 compatible = "sifive,rocket0", "riscv";
531 compatible = "sifive,rocket0", "riscv";
536 compatible = "sifive,rocket0", "riscv";
541 compatible = "sifive,rocket0", "riscv";
/Documentation/devicetree/bindings/
Dvendor-prefixes.yaml963 "^sifive,.*":
964 description: SiFive, Inc.