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/Documentation/devicetree/bindings/usb/
Dusb.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
19 $ref: /schemas/types.yaml#/definitions/phandle-array
23 phy-names:
27 usb-phy:
28 $ref: /schemas/types.yaml#/definitions/phandle-array
37 UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is selected, UTMI+ low
39 serial is specified and High-Speed Inter-Chip feature if HSIC is
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Dcdns,usb3.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence USBSS-DRD controller bindings
10 - Pawel Laszczak <pawell@cadence.com>
18 - description: OTG controller registers
19 - description: XHCI Host controller registers
20 - description: DEVICE controller registers
22 reg-names:
24 - const: otg
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Dti,hd3ss3220.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
12 description: |-
14 Configuration (CC) logic and 5V VCONN sourcing for ecosystems implementing USB Type-C. The
35 description: Super Speed (SS) MUX inputs connected to SS capable connector.
36 $ref: /connector/usb-connector.yaml#/properties/ports/properties/port@1
40 description: Output of 2:1 MUX connected to Super Speed (SS) data bus.
43 - port@0
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Dnvidia,tegra-xudc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: "http://devicetree.org/schemas/usb/nvidia,tegra-xudc.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
14 - Nagarjuna Kristam <nkristam@nvidia.com>
15 - JC Kuo <jckuo@nvidia.com>
16 - Thierry Reding <treding@nvidia.com>
21 - enum:
22 - nvidia,tegra210-xudc # For Tegra210
23 - nvidia,tegra186-xudc # For Tegra186
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Dusb-drd.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/usb-drd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
13 otg-rev:
16 which the device and its descriptors are compliant, in binary-coded
18 features (HNP/SRP/ADP) is enabled. If ADP is required, otg-rev should be
24 Tells Dual-Role USB controllers that we want to work on a particular
30 hnp-disable:
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/Documentation/hwmon/
Df71882fg.rst10 Addresses scanned: none, address read from Super I/O config space
18 Addresses scanned: none, address read from Super I/O config space
26 Addresses scanned: none, address read from Super I/O config space
34 Addresses scanned: none, address read from Super I/O config space
42 Addresses scanned: none, address read from Super I/O config space
50 Addresses scanned: none, address read from Super I/O config space
58 Addresses scanned: none, address read from Super I/O config space
66 Addresses scanned: none, address read from Super I/O config space
74 Addresses scanned: none, address read from Super I/O config space
82 Addresses scanned: none, address read from Super I/O config space
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Dnct6775.rst15 Addresses scanned: ISA address retrieved from Super I/O registers
19 * Nuvoton NCT5572D/NCT6771F/NCT6772F/NCT6775F/W83677HG-I
23 Addresses scanned: ISA address retrieved from Super I/O registers
31 Addresses scanned: ISA address retrieved from Super I/O registers
39 Addresses scanned: ISA address retrieved from Super I/O registers
47 Addresses scanned: ISA address retrieved from Super I/O registers
55 Addresses scanned: ISA address retrieved from Super I/O registers
63 Addresses scanned: ISA address retrieved from Super I/O registers
71 Addresses scanned: ISA address retrieved from Super I/O registers
79 Addresses scanned: ISA address retrieved from Super I/O registers
[all …]
Dit87.rst10 Addresses scanned: from Super I/O config space (8 I/O ports)
18 Addresses scanned: from Super I/O config space (8 I/O ports)
24 Addresses scanned: from Super I/O config space (8 I/O ports)
32 Addresses scanned: from Super I/O config space (8 I/O ports)
40 Addresses scanned: from Super I/O config space (8 I/O ports)
48 Addresses scanned: from Super I/O config space (8 I/O ports)
56 Addresses scanned: from Super I/O config space (8 I/O ports)
64 Addresses scanned: from Super I/O config space (8 I/O ports)
72 Addresses scanned: from Super I/O config space (8 I/O ports)
80 Addresses scanned: from Super I/O config space (8 I/O ports)
[all …]
Dw83627ehf.rst10 Addresses scanned: ISA address retrieved from Super I/O registers
18 Addresses scanned: ISA address retrieved from Super I/O registers
22 * Winbond W83627DHG-P
26 Addresses scanned: ISA address retrieved from Super I/O registers
34 Addresses scanned: ISA address retrieved from Super I/O registers
42 Addresses scanned: ISA address retrieved from Super I/O registers
46 * Winbond W83667HG-B
50 Addresses scanned: ISA address retrieved from Super I/O registers
54 * Nuvoton NCT6775F/W83667HG-I
58 Addresses scanned: ISA address retrieved from Super I/O registers
[all …]
Dpc87427.rst10 Addresses scanned: none, address read from Super I/O config space
21 -----------
23 The National Semiconductor Super I/O chip includes complete hardware
36 --------------
38 Fan rotation speeds are reported as 14-bit values from a gated clock
41 An alarm is triggered if the rotation speed drops below a programmable
42 limit. Another alarm is triggered if the speed is too low to be measured
46 Fan Speed Control
47 -----------------
49 Fan speed can be controlled by PWM outputs. There are 4 possible modes:
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Df71805f.rst10 Addresses scanned: none, address read from Super I/O config space
18 Addresses scanned: none, address read from Super I/O config space
26 Addresses scanned: none, address read from Super I/O config space
44 -----------
46 The Fintek F71805F/FG Super I/O chip includes complete hardware monitoring
53 The Fintek F71872F/FG Super I/O chip is almost the same, with two
57 The Fintek F71806F/FG Super-I/O chip is essentially the same as the
65 ------------------
67 Voltages are sampled by an 8-bit ADC with a LSB of 8 mV. The supported
84 in1 VIN1 VTT1.2V 10K - 1.00 1.20 V
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Dpc87360.rst10 Addresses scanned: none, address read from Super I/O config space
22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
42 -----------
44 The National Semiconductor PC87360 Super I/O chip contains monitoring and
48 The National Semiconductor PC87365 and PC87366 Super I/O chips are complete
56 PC87360 - 2 2 - 0xE1
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Dsmsc47m1.rst10 Addresses scanned: none, address read from Super I/O config space
26 Addresses scanned: none, address read from Super I/O config space
34 Addresses scanned: none, address read from Super I/O config space
44 - Mark D. Studebaker <mdsxyz123@yahoo.com>,
45 - With assistance from Bruce Allen <ballen@uwm.edu>, and his
48 - http://www.lsc-group.phys.uwm.edu/%7Eballen/driver/
50 - Gabriele Gorla <gorlik@yahoo.com>,
51 - Jean Delvare <jdelvare@suse.de>
54 -----------
56 The Standard Microsystems Corporation (SMSC) 47M1xx Super I/O chips
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Ddme1737.rst18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
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/Documentation/devicetree/bindings/phy/
Dsocionext,uniphier-usb3ss-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 Super-Speed (SS) PHY
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about Super-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro4-usb3-ssphy
22 - socionext,uniphier-pro5-usb3-ssphy
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Dnvidia,tegra124-xusb-padctl.txt11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
12 super-speed USB. Other lanes are for various types of low-speed, full-speed
13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
14 contains a software-configurable mux that sits between the I/O controller
17 In addition to per-lane configuration, USB 3.0 ports may require additional
18 settings on a per-board basis.
20 Pads will be represented as children of the top-level XUSB pad controller
23 PHY bindings, as described by the phy-bindings.txt file in this directory.
34 --------------------
35 - compatible: Must be:
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Dsocionext,uniphier-usb3hs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-usb3-hsphy
22 - socionext,uniphier-pxs2-usb3-hsphy
[all …]
/Documentation/driver-api/usb/
Dusb3-debug-port.rst19 3) have a USB 3.0 super-speed A-to-A debugging cable.
30 super-speed port). The debug device is fully compliant with
32 performance full-duplex serial link between the debug target
41 Other uses include simpler, lockless logging instead of a full-
58 "usbcore.autosuspend=-1"
63 should be a USB 3.0 super-speed A-to-A debugging cable.
74 # tail -f /var/log/kern.log
75 [ 1815.983374] usb 4-3: new SuperSpeed USB device number 4 using xhci_hcd
76 [ 1815.999595] usb 4-3: LPM exit latency is zeroed, disabling LPM.
77 [ 1815.999899] usb 4-3: New USB device found, idVendor=1d6b, idProduct=0004
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/Documentation/ABI/testing/
Dconfigfs-usb-gadget-ecm1 What: /config/usb-gadget/gadget/functions/ecm.name
8 - network device interface name associated with
11 - queue length multiplier for high and
12 super speed
14 - MAC address of host's end of this
17 - MAC address of device's end of this
Dconfigfs-usb-gadget-ncm1 What: /config/usb-gadget/gadget/functions/ncm.name
7 ifname - network device interface name associated with
9 qmult - queue length multiplier for high and
10 super speed
11 host_addr - MAC address of host's end of this
13 dev_addr - MAC address of device's end of this
Dconfigfs-usb-gadget-subset1 What: /config/usb-gadget/gadget/functions/geth.name
11 super speed
Dconfigfs-usb-gadget-eem1 What: /config/usb-gadget/gadget/functions/eem.name
11 super speed
Dsysfs-bus-pci-drivers-xhci_hcd5 xHCI compatible USB host controllers (i.e. super-speed
9 the equivalent of a very high performance full-duplex
Dconfigfs-usb-gadget-rndis1 What: /config/usb-gadget/gadget/functions/rndis.name
11 super speed
Dconfigfs-usb-gadget1 What: /config/usb-gadget
5 This group contains sub-groups corresponding to created
8 What: /config/usb-gadget/gadget
20 max_speed maximum speed the driver supports. Valid
21 names are super-speed-plus, super-speed,
22 high-speed, full-speed, and low-speed.
34 What: /config/usb-gadget/gadget/configs
40 What: /config/usb-gadget/gadget/configs/config
51 What: /config/usb-gadget/gadget/configs/config/strings
55 This group contains subdirectories for language-specific
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