Searched full:xilinx (Results 1 – 25 of 62) sorted by relevance
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| /Documentation/devicetree/bindings/arm/ |
| D | xilinx.yaml | 4 $id: http://devicetree.org/schemas/arm/xilinx.yaml#
7 title: Xilinx Zynq Platforms Device Tree Bindings
10 - Michal Simek <michal.simek@xilinx.com>
13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
49 - description: Xilinx internal board zc1232
55 - description: Xilinx internal board zc1254
61 - description: Xilinx internal board zc1275
67 - description: Xilinx 96boards compatible board zcu100
73 - description: Xilinx 96boards compatible board Ultra96
81 - description: Xilinx evaluation board zcu102
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| /Documentation/devicetree/bindings/ |
| D | xilinx.txt | 1 d) Xilinx IP cores
3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
4 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
89 That covers the general approach to binding xilinx IP cores into the
92 i) Xilinx ML300 Framebuffer
105 ii) Xilinx SystemACE
107 The Xilinx SystemACE device is used to program FPGAs from an FPGA
114 iii) Xilinx EMAC and Xilinx TEMAC
116 Xilinx Ethernet devices. In addition to general xilinx properties
121 iv) Xilinx Uartlite
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| /Documentation/ABI/stable/ |
| D | sysfs-driver-firmware-zynqmp | 4 Contact: "Jolly Shah" <jollys@xilinx.com>
13 other Xilinx software products: GLOBAL_GEN_STORAGE{4:6}.
25 Users: Xilinx
30 Contact: "Jolly Shah" <jollys@xilinx.com>
40 Four registers are used by the FSBL and other Xilinx
54 Users: Xilinx
59 Contact: "Jolly Shah" <jollys@xilinx.com>
91 Users: Xilinx
96 Contact: "Jolly Shah" <jollys@xilinx.com>
115 Users: Xilinx
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| /Documentation/devicetree/bindings/clock/ |
| D | xlnx,versal-clk.yaml | 7 title: Xilinx Versal clock controller
10 - Michal Simek <michal.simek@xilinx.com>
11 - Jolly Shah <jolly.shah@xilinx.com>
12 - Rajan Vaja <rajan.vaja@xilinx.com>
15 The clock controller is a hardware block of Xilinx versal clock tree. It
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| /Documentation/devicetree/bindings/fpga/ |
| D | xilinx-slave-serial.txt | 1 Xilinx Slave Serial SPI FPGA Manager
3 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the
9 - https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
10 - https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
11 - https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
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| D | xilinx-pr-decoupler.txt | 1 Xilinx LogiCORE Partial Reconfig Decoupler Softcore
3 The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
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| D | xilinx-zynq-fpga-mgr.txt | 1 Xilinx Zynq FPGA Manager
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| /Documentation/devicetree/bindings/media/xilinx/ |
| D | video.txt | 1 DT bindings for Xilinx video IP cores
4 Xilinx video IP cores process video streams by acting as video sinks and/or
18 The following properties are common to all Xilinx video IP cores.
35 [UG934] https://www.xilinx.com/support/documentation/ip_documentation/axi_videoip/v1_0/ug934_axi_vi…
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| D | xlnx,video.txt | 1 Xilinx Video IP Pipeline (VIPP)
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
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| D | xlnx,csi2rxss.yaml | 4 $id: http://devicetree.org/schemas/media/xilinx/xlnx,csi2rxss.yaml#
7 title: Xilinx MIPI CSI-2 Receiver Subsystem
10 - Vishal Sagar <vishal.sagar@xilinx.com>
13 The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
20 For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
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| D | xlnx,v-tc.txt | 1 Xilinx Video Timing Controller (VTC)
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| /Documentation/devicetree/bindings/crypto/ |
| D | xlnx,zynqmp-aes.yaml | 7 title: Xilinx ZynqMP AES-GCM Hardware Accelerator Device Tree Bindings
10 - Kalyani Akula <kalyani.akula@xilinx.com>
11 - Michal Simek <michal.simek@xilinx.com>
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| /Documentation/devicetree/bindings/mailbox/ |
| D | xlnx,zynqmp-ipi-mailbox.txt | 1 Xilinx IPI Mailbox Controller
4 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
5 messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
9 | Xilinx ZynqMP IPI Controller |
26 | Xilinx IPI Agent Block |
39 - xlnx,ipi-id: local Xilinx IPI agent ID
60 - xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is
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| /Documentation/admin-guide/media/ |
| D | platform-cardlist.rst | 77 xilinx-tpg Xilinx Video Test Pattern Generator
78 xilinx-video Xilinx Video IP (EXPERIMENTAL)
79 xilinx-vtc Xilinx Video Timing Controller
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| /Documentation/devicetree/bindings/dma/xilinx/ |
| D | xlnx,zynqmp-dpdma.yaml | 4 $id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dpdma.yaml#
7 title: Xilinx ZynqMP DisplayPort DMA Controller Device Tree Bindings
10 These bindings describe the DMA engine included in the Xilinx ZynqMP
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| D | xilinx_dma.txt | 1 Xilinx AXI VDMA engine, it does transfers between memory and video devices.
6 Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
11 Xilinx AXI CDMA engine, it does transfers between memory-mapped source
14 Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream
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| /Documentation/devicetree/bindings/rtc/ |
| D | xlnx-rtc.txt | 1 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
3 RTC controller for the Xilinx Zynq MPSoC Real Time Clock
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| /Documentation/driver-api/xilinx/ |
| D | eemi.rst | 2 Xilinx Zynq MPSoC EEMI Documentation
5 Xilinx Zynq MPSoC Firmware Interface
40 https://www.xilinx.com/support/documentation/user_guides/ug1200-eemi-api.pdf
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| D | index.rst | 3 Xilinx FPGA
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| /Documentation/devicetree/bindings/pci/ |
| D | xilinx-versal-cpm.yaml | 4 $id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
7 title: CPM Host Controller device tree for Xilinx Versal SoCs
10 - Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | xilinx-xadc.txt | 1 Xilinx XADC device driver
4 bindings are very similar. The Xilinx XADC is a ADC that can be found in the
5 series 7 FPGAs from Xilinx. The XADC has a DRP interface for communication.
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| /Documentation/devicetree/bindings/phy/ |
| D | xlnx,zynqmp-psgtr.yaml | 7 title: Xilinx ZynqMP Gigabit Transceiver PHY Device Tree Bindings
13 This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The
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| /Documentation/devicetree/bindings/usb/ |
| D | udc-xilinx.txt | 1 Xilinx USB2 device controller
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| /Documentation/devicetree/bindings/misc/ |
| D | xlnx,sd-fec.txt | 1 * Xilinx SDFEC(16nm) IP *
23 - reg: Should contain Xilinx SDFEC 16nm Hardened IP block registers
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| /Documentation/devicetree/bindings/display/xlnx/ |
| D | xlnx,zynqmp-dpsub.yaml | 7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
41 (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)
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