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/Documentation/devicetree/bindings/net/
Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
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/Documentation/devicetree/bindings/soc/ti/
Dti,pruss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
23 peripheral interfaces, fast real-time responses, or specialized data handling.
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/Documentation/devicetree/bindings/mtd/
Ddenali,nand.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - altr,socfpga-denali-nand
16 - socionext,uniphier-denali-nand-v5a
17 - socionext,uniphier-denali-nand-v5b
19 reg-names:
25 - const: nand_data
26 - const: denali_reg
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Dallwinner,sun4i-a10-nand.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/allwinner,sun4i-a10-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: "nand-controller.yaml"
13 - Chen-Yu Tsai <wens@csie.org>
14 - Maxime Ripard <mripard@kernel.org>
17 "#address-cells": true
18 "#size-cells": true
22 - allwinner,sun4i-a10-nand
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Dst,stm32-fmc2-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/st,stm32-fmc2-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@st.com>
15 - st,stm32mp15-fmc2
16 - st,stm32mp1-fmc2-nfc
27 - description: tx DMA channel
28 - description: rx DMA channel
29 - description: ecc DMA channel
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Dingenic,nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: nand-controller.yaml#
18 - ingenic,jz4740-nand
19 - ingenic,jz4725b-nand
20 - ingenic,jz4780-nand
24 - description: Bank number, offset and size of first attached NAND chip
25 - description: Bank number, offset and size of second attached NAND chip
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/Documentation/ABI/stable/
Dsysfs-module7 module name will always show up if the module is loaded as a
9 will only show up if it has a version or at least one
12 Note: The conditions of creation in the built-in case are not
38 KernelVersion: Android Common Kernel -- android12-5.10+
40 Description: This read-only file will appear if modpost was supplied with an
49 Git: g[a-f0-9]\+(-dirty)\?
50 Mercurial: hg[a-f0-9]\+(-dirty)\?
51 Subversion: svn[0-9]\+
Dsysfs-class-tpm4 Contact: linux-integrity@vger.kernel.org
5 Description: The device/ directory under a specific TPM instance exposes
12 Contact: linux-integrity@vger.kernel.org
13 Description: The "active" property prints a '1' if the TPM chip is accepting
16 visible to the OS, but will only accept a restricted set of
24 Contact: linux-integrity@vger.kernel.org
32 Contact: linux-integrity@vger.kernel.org
41 Manufacturer is a hex dump of the 4 byte manufacturer info
42 space in a TPM. TCG version shows the TCG TPM spec level that
49 Contact: linux-integrity@vger.kernel.org
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/Documentation/devicetree/bindings/timer/
Dingenic,tcu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 For a description of the TCU hardware and drivers, have a look at
11 Documentation/mips/ingenic-tcu.rst.
14 - Paul Cercueil <paul@crapouillou.net>
21 - ingenic,jz4740-tcu
22 - ingenic,jz4725b-tcu
23 - ingenic,jz4770-tcu
24 - ingenic,jz4780-tcu
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Dmrvl,mmp-timer.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/mrvl,mmp-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Lezcano <daniel.lezcano@linaro.org>
11 - Thomas Gleixner <tglx@linutronix.de>
12 - Rob Herring <robh+dt@kernel.org>
16 pattern: '^timer@[a-f0-9]+$'
19 const: mrvl,mmp-timer
31 - compatible
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/Documentation/devicetree/bindings/phy/
Dmarvell,mmp3-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/marvell,mmp3-usb-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Lubomir Rintel <lkundrak@v3.sk>
15 pattern: '^usb-phy@[a-f0-9]+$'
18 const: marvell,mmp3-usb-phy
24 '#phy-cells':
28 - compatible
29 - reg
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/Documentation/devicetree/bindings/crypto/
Dti,sa2ul.yaml1 # SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <t-kristo@ti.com>
15 - ti,j721e-sa2ul
16 - ti,am654-sa2ul
21 power-domains:
26 - description: TX DMA Channel
27 - description: RX DMA Channel #1
28 - description: RX DMA Channel #2
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/Documentation/devicetree/bindings/clock/
Dingenic,cgu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
11 typically includes a variety of PLLs, multiplexers, dividers & gates in order
16 - Paul Cercueil <paul@crapouillou.net>
23 - ingenic,jz4740-cgu
24 - ingenic,jz4725b-cgu
25 - ingenic,jz4770-cgu
26 - ingenic,jz4780-cgu
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/Documentation/devicetree/bindings/usb/
Dti,keystone-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Roger Quadros <rogerq@ti.com>
15 - enum:
16 - ti,keystone-dwc3
17 - ti,am654-dwc3
22 '#address-cells':
25 '#size-cells':
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/Documentation/devicetree/bindings/media/
Dmarvell,mmp2-ccic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/marvell,mmp2-ccic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Lubomir Rintel <lkundrak@v3.sk>
15 pattern: '^camera@[a-f0-9]+$'
18 const: marvell,mmp2-ccic
36 # Documentation/devicetree/bindings/media/video-interfaces.txt
38 remote-endpoint: true
39 hsync-active: true
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/Documentation/devicetree/bindings/memory-controllers/
Dexynos-srom.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
33 <bank-number> 0 <parent address of bank> <size>
37 "^.*@[0-3],[a-f0-9]+$":
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/Documentation/devicetree/bindings/mfd/
Dgoogle,cros-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benson Leung <bleung@chromium.org>
11 - Enric Balletbo i Serra <enric.balletbo@collabora.com>
12 - Guenter Roeck <groeck@chromium.org>
15 Google's ChromeOS EC is a microcontroller which talks to the AP and
23 - description:
25 const: google,cros-ec-i2c
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/Documentation/xtensa/
Dmmu.rst9 (symbol defined), so it needs to be position-independent.
13 - This code fragment is run only on an MMU v3.
14 - TLBs are in their reset state.
15 - ITLBCFG and DTLBCFG are zero (reset state).
16 - RASID is 0x04030201 (reset state).
17 - PS.RING is zero (reset state).
18 - LITBASE is zero (reset state, PC-relative literals); required to be PIC.
24 - VA = virtual address (two upper nibbles of it);
25 - PA = physical address (two upper nibbles of it);
26 - pc = physical range that contains this code;
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/Documentation/devicetree/bindings/gpu/
Darm,mali-bifrost.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-bifrost.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
14 pattern: '^gpu@[a-f0-9]+$'
18 - enum:
19 - amlogic,meson-g12a-mali
20 - realtek,rtd1619-mali
21 - rockchip,px30-mali
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Darm,mali-utgard.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
11 - Maxime Ripard <mripard@kernel.org>
12 - Heiko Stuebner <heiko@sntech.de>
16 pattern: '^gpu@[a-f0-9]+$'
19 - items:
20 - const: allwinner,sun8i-a23-mali
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Darm,mali-midgard.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpu/arm,mali-midgard.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
14 pattern: '^gpu@[a-f0-9]+$'
17 - items:
18 - enum:
19 - samsung,exynos5250-mali
20 - const: arm,mali-t604
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/Documentation/devicetree/bindings/sram/
Dallwinner,sun4i-a10-system-control.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
4 $id: http://devicetree.org/schemas/sram/allwinner,sun4i-a10-system-control.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
15 by a regular node for the SRAM controller itself, with sub-nodes
19 "#address-cells":
22 "#size-cells":
27 - const: allwinner,sun4i-a10-sram-controller
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/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra20-pmc
18 - nvidia,tegra30-pmc
19 - nvidia,tegra114-pmc
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/Documentation/userspace-api/ioctl/
Dioctl-number.rst21 system calls 'write' and 'read'. For example, a SET_FOO ioctl would
23 a GET_FOO ioctl would be _IOR, although the kernel would actually write
28 many drivers share a partial letter with other drivers.
30 If you are writing a driver for a new device and need a letter, pick an
33 patch to Linus Torvalds. Or you can e-mail me at <mec@shout.net> and
36 The second argument to _IO, _IOW, _IOR, or _IOWR is a sequence number
50 if a program calls an ioctl on the wrong device, it will get an
67 no attempt to list non-X86 architectures or ioctls from drivers/staging/.
73 0x00 00-1F linux/fs.h conflict!
74 0x00 00-1F scsi/scsi_ioctl.h conflict!
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/Documentation/input/devices/
Dalps.rst1 ----------------------
3 ----------------------
6 ------------
10 Since roughly mid-2010 several new ALPS touchpads have been released and
11 integrated into a variety of laptops and netbooks. These new touchpads
14 adequate. The design choices were to re-define the alps_model_data
23 (Compatibility ID) definition as a way to uniquely identify the
24 different ALPS variants but there did not appear to be a 1:1 mapping.
29 ---------
32 E8-E6-E6-E6-E9. An ALPS touchpad should respond with either 00-00-0A or
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