Searched full:accelerator (Results 1 – 25 of 59) sorted by relevance
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| /Documentation/devicetree/bindings/crypto/ |
| D | img-hash.txt | 1 Imagination Technologies hardware hash accelerator
3 The hash accelerator provides hardware hashing acceleration for
8 - compatible : "img,hash-accelerator"
15 "hash" Used to clock data through the accelerator
20 compatible = "img,hash-accelerator";
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| D | xlnx,zynqmp-aes.yaml | 7 title: Xilinx ZynqMP AES-GCM Hardware Accelerator Device Tree Bindings
14 The ZynqMP AES-GCM hardened cryptographic accelerator is used to
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| D | rockchip-crypto.txt | 1 Rockchip Electronics And Security Accelerator
11 "sclk" used to clock crypto accelerator
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| D | picochip-spacc.txt | 1 Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings
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| D | fsl-imx-sahara.yaml | 7 title: Freescale SAHARA Cryptographic Accelerator included in some i.MX chips
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| D | mv_cesa.txt | 1 Marvell Cryptographic Engines And Security Accelerator
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| D | samsung-sss.yaml | 18 -- Public Key Accelerator (PKA)
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| D | marvell-cesa.txt | 1 Marvell Cryptographic Engines And Security Accelerator
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| /Documentation/devicetree/bindings/dma/ |
| D | ste-dma40.txt | 110 48: Crypto Accelerator 1
111 49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
112 50: Hash Accelerator 1 TX
123 61: Crypto Accelerator 0
124 62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
125 63: Hash Accelerator 0 TX
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| /Documentation/devicetree/bindings/powerpc/4xx/ |
| D | ppc440spe-adma.txt | 1 PPC440SPe DMA/XOR (DMA Controller and XOR Accelerator)
60 iii) XOR Accelerator node
64 - compatible : "amcc,xor-accelerator";
71 compatible = "amcc,xor-accelerator";
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | iva.txt | 1 * TI - IVA (Imaging and Video Accelerator) subsystem
3 The IVA contain various audio, video or imaging HW accelerator
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| /Documentation/misc-devices/ |
| D | uacce.rst | 6 Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
8 So accelerator can access any data structure of the main cpu.
13 Uacce takes the hardware accelerator as a heterogeneous processor, while
21 | User application (CPU) | | Hardware Accelerator |
95 The accelerator device present itself as an Uacce object, which exports as
175 match the right accelerator accordingly.
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | k3-ringacc.yaml | 8 title: Texas Instruments K3 NavigatorSS Ring Accelerator
15 The Ring Accelerator (RA) is a machine which converts read/write accesses
25 The Ring Accelerator is a hardware module that is responsible for accelerating
63 description: TI-SCI device id of the ring accelerator
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| /Documentation/powerpc/ |
| D | cxl.rst | 2 Coherent Accelerator Interface (CXL)
8 The coherent accelerator interface is designed to allow the
11 Accelerator Interface Architecture (CAIA).
13 IBM refers to this as the Coherent Accelerator Processor Interface
17 Coherent in this context means that the accelerator and CPUs can
46 The POWER Service Layer (PSL) and the Accelerator Function Unit
52 The AFU is the core part of the accelerator (eg. the compression,
86 this mode, only one userspace process can use the accelerator at
91 applications may use the accelerator (although specific AFUs may
102 A portion of the accelerator MMIO space can be directly mapped
[all …]
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| D | vas-api.rst | 5 Virtual Accelerator Switchboard (VAS) userspace API
11 Power9 processor introduced Virtual Accelerator Switchboard (VAS) which
13 (hardware accelerator) referred to as the Nest Accelerator (NX). The NX
31 requests directly to NX accelerator.
82 accelerator. It finds CPU on which the user process is executing and
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| /Documentation/ABI/testing/ |
| D | sysfs-driver-hid-logitech-lg4ff | 72 Description: Controls whether a combined value of accelerator and brake is
74 which can do not work with separate accelerator/brake axis.
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| D | sysfs-driver-uacce | 26 Description: Algorithms supported by this accelerator, separated by new line.
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| /Documentation/devicetree/bindings/net/ |
| D | keystone-netcp.txt | 4 The network coprocessor (NetCP) is a hardware accelerator that processes
7 accelerator (PA) module to perform packet classification operations such as
9 generation. NetCP can also optionally include a Security Accelerator (SA)
31 | |-> Packet Accelerator
33 | |-> Security Accelerator
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| D | hisilicon-hns-nic.txt | 7 - ae-handle: accelerator engine handle for hns,
10 - port-id: is the index of port provided by DSAF (the accelerator). DSAF can
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| /Documentation/devicetree/bindings/rng/ |
| D | ks-sa-rng.txt | 3 On Keystone SoCs HWRNG module is a submodule of the Security Accelerator.
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| /Documentation/devicetree/bindings/powerpc/ |
| D | ibm,vas.txt | 1 * IBM Powerpc Virtual Accelerator Switchboard (VAS)
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| /Documentation/devicetree/bindings/gpu/ |
| D | samsung-g2d.yaml | 7 title: Samsung SoC 2D Graphics Accelerator
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| /Documentation/devicetree/bindings/interconnect/ |
| D | qcom,bcm-voter.yaml | 13 The Bus Clock Manager (BCM) is a dedicated hardware accelerator that manages
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| /Documentation/devicetree/bindings/media/ |
| D | qcom,msm8916-venus.yaml | 14 The Venus IP is a video encode and decode accelerator present
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| /Documentation/userspace-api/accelerators/ |
| D | ocxl.rst | 2 OpenCAPI (Open Coherent Accelerator Processor Interface)
9 It allows an accelerator (which could be a FPGA, ASICs, ...) to access
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