Searched full:accesses (Results 1 – 25 of 196) sorted by relevance
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| /Documentation/driver-api/ |
| D | device-io.rst | 10 Bus-Independent Device Accesses
30 part of the CPU's address space is interpreted not as accesses to
31 memory, but as accesses to a device. Some architectures define devices
54 historical accident, these are named byte, word, long and quad accesses.
55 Both read and write accesses are supported; there is no prefetch support
119 Port Space Accesses
127 addresses is generally not as fast as accesses to the memory mapped
136 Accesses to this space are provided through a set of functions which
137 allow 8-bit, 16-bit and 32-bit accesses; also known as byte, word and
143 that accesses to their ports are slowed down. This functionality is
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| /Documentation/core-api/ |
| D | unaligned-memory-access.rst | 2 Unaligned Memory Accesses
15 unaligned accesses, why you need to write code that doesn't cause them,
22 Unaligned memory accesses occur when you try to read N bytes of data starting
59 - Some architectures are able to perform unaligned memory accesses
61 - Some architectures raise processor exceptions when unaligned accesses
64 - Some architectures raise processor exceptions when unaligned accesses
72 memory accesses to happen, your code will not work correctly on certain
103 to pad structures so that accesses to fields are suitably aligned (assuming
136 lead to unaligned accesses when accessing fields that do not satisfy
183 Here is another example of some code that could cause unaligned accesses::
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| D | dma-attributes.rst | 87 - You know that the accesses to this memory won't thrash the TLB.
88 You might know that the accesses are likely to be sequential or
128 accesses to DMA buffers in both privileged "supervisor" and unprivileged
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| /Documentation/dev-tools/ |
| D | kcsan.rst | 94 instrumentation or e.g. DMA accesses. These reports will only be generated if
100 It may be desirable to disable data race detection for specific accesses,
105 any data races due to accesses in ``expr`` should be ignored and resulting
140 accesses are aligned writes up to word size.
190 In an execution, two memory accesses form a *data race* if they *conflict*,
194 Accesses and Data Races" in the LKMM`_.
196 .. _"Plain Accesses and Data Races" in the LKMM: https://git.kernel.org/pub/scm/linux/kernel/git/to…
236 KCSAN relies on observing that two accesses happen concurrently. Crucially, we
243 address set up, and then observe the watchpoint to fire, two accesses to the
253 compiler instrumenting plain accesses. For each instrumented plain access:
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| /Documentation/devicetree/bindings/ |
| D | common-properties.txt | 13 - big-endian: Boolean; force big endian register accesses
16 - little-endian: Boolean; force little endian register accesses
19 - native-endian: Boolean; always use register accesses matched to the
30 default to LE for their MMIO accesses.
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | baikal,bt1-l2-ctl.yaml | 29 description: Cycles of latency for Way-select RAM accesses
36 description: Cycles of latency for Tag RAM accesses
43 description: Cycles of latency for Data RAM accesses
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| D | omap-gpmc.txt | 86 - gpmc,bus-turnaround-ns: Turn-around time between successive accesses
97 accesses to a different CS
99 accesses to the same CS
106 burst accesses, defines the number of
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| /Documentation/i2c/ |
| D | i2c-topology.rst | 152 This means that accesses to D2 are lockout out for the full duration
153 of the entire operation. But accesses to D3 are possibly interleaved
216 This means that accesses to both D2 and D3 are locked out for the full
261 When device D1 is accessed, accesses to D2 are locked out for the
263 are locked). But accesses to D3 and D4 are possibly interleaved at
264 any point. Accesses to D3 locks out D1 and D2, but accesses to D4
282 When device D1 is accessed, accesses to D2 and D3 are locked out
284 root adapter). But accesses to D4 are possibly interleaved at any
295 mux. In that case, any interleaved accesses to D4 might close M2
316 When D1 is accessed, accesses to D2 are locked out for the full
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| /Documentation/devicetree/bindings/mtd/ |
| D | gpio-control-nand.txt | 10 resource describes the data bus connected to the NAND flash and all accesses
23 location used to guard against bus reordering with regards to accesses to
26 read to ensure that the GPIO accesses have completed.
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| /Documentation/admin-guide/hw-vuln/ |
| D | special-register-buffer-data-sampling.rst | 7 infer values returned from special register accesses. Special register
8 accesses are accesses to off core registers. According to Intel's evaluation,
69 accesses from other logical processors will be delayed until the special
81 #. Executing RDRAND, RDSEED or EGETKEY will delay memory accesses from other
83 legacy locked cache-line-split accesses.
90 processors memory accesses. The opt-out mechanism does not affect Intel SGX
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| /Documentation/hwmon/ |
| D | w83627hf.rst | 5 * Winbond W83627HF (ISA accesses ONLY)
41 This driver implements support for ISA accesses *only* for
45 This driver supports ISA accesses, which should be more reliable
46 than i2c accesses. Also, for Tyan boards which contain both a
51 If you really want i2c accesses for these Super I/O chips,
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| /Documentation/process/ |
| D | volatile-considered-harmful.rst | 39 meaning that data accesses will not be optimized across them. So the
43 accesses to that data.
53 registers. Within the kernel, register accesses, too, should be protected
55 accesses within a critical section. But, within the kernel, I/O memory
56 accesses are always done through accessor functions; accessing I/O memory
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| /Documentation/ |
| D | atomic_t.txt | 194 smp_mb__before_atomic() orders all earlier accesses against the RMW op
195 itself and all accesses following it, and smp_mb__after_atomic() orders all
196 later accesses against the RMW op and all accesses preceding it. However,
197 accesses between the smp_mb__{before,after}_atomic() and the RMW op are not
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| D | memory-barriers.txt | 76 - Acquires vs memory accesses.
156 The set of accesses as seen by the memory system in the middle can be arranged
229 (*) On any given CPU, dependent memory accesses will be issued in order, with
289 (*) It _must_ be assumed that overlapping memory accesses may be merged or
495 ACQUIRE on a given variable, all memory accesses preceding any prior
497 words, within a given variable's critical section, all accesses of all
526 (*) There is no guarantee that any of the memory accesses specified before a
529 access queue that accesses of the appropriate type may not cross.
534 of the first CPU's accesses occur, but see the next point:
537 from a second CPU's accesses, even _if_ the second CPU uses a memory
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| /Documentation/devicetree/bindings/thermal/ |
| D | mediatek-thermal.txt | 5 instead it directly controls the AUXADC via AHB bus accesses. For this reason
7 apmixedsys register space via AHB bus accesses, so a phandle to the APMIXEDSYS
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| /Documentation/admin-guide/mm/ |
| D | idle_page_tracking.rst | 39 Only accesses to user memory pages are tracked. These are pages mapped to a
61 2. Wait until the workload accesses its working set.
82 The kernel internally keeps track of accesses to user memory pages in order to
108 mapped to, otherwise we will not be able to detect accesses to the page coming
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| /Documentation/devicetree/bindings/iommu/ |
| D | msm,iommu-v0.txt | 27 required for iommu's register accesses.
29 required by iommu for bus accesses.
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| /Documentation/devicetree/bindings/arm/altera/ |
| D | socfpga-sdram-edac.txt | 2 The EDAC accesses a range of registers in the SDRAM controller.
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| /Documentation/networking/dsa/ |
| D | bcm_sf2.rst | 26 The switch hardware block is typically interfaced using MMIO accesses and
32 which is used for indirect PHY accesses)
66 MDIO indirect accesses
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| /Documentation/trace/ |
| D | mmiotrace.rst | 12 Jeff Muizelaar created a tool for tracing MMIO accesses with the Nouveau
68 accesses to areas that are ioremapped while mmiotrace is active.
126 MMIO accesses are recorded via page faults. Just before __ioremap() returns,
166 zero if it is not recorded. PID is always zero as tracing MMIO accesses
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| /Documentation/litmus-tests/atomic/ |
| D | Atomic-RMW+mb__after_atomic-is-stronger-than-acquire.litmus | 8 * the RMW are ordered before the subsequential memory accesses.
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| /Documentation/devicetree/bindings/net/ |
| D | smsc-lan91c111.txt | 10 - reg-io-width : Mask of sizes (in bytes) of the IO accesses that
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | k3-ringacc.yaml | 15 The Ring Accelerator (RA) is a machine which converts read/write accesses
16 from/to a constant address into corresponding read/write accesses from/to a
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| /Documentation/devicetree/bindings/nds32/ |
| D | atl2c.txt | 7 reducing DRAM accesses.
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | dmm.txt | 5 accesses such as priority generation amongst initiators, configuration of SDRAM
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