Searched +full:active +full:- +full:low (Results 1 – 25 of 334) sorted by relevance
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-bcm6358.txt | 5 which can either be controlled by software (exporting the 74x164 as spi-gpio.
6 See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or
10 - compatible : should be "brcm,bcm6358-leds".
11 - #address-cells : must be 1.
12 - #size-cells : must be 0.
13 - reg : BCM6358 LED controller address and size.
16 - brcm,clk-div : SCK signal divider. Possible values are 1, 2, 4 and 8.
18 - brcm,clk-dat-low : Boolean, makes clock and data signals active low.
21 Each LED is represented as a sub-node of the brcm,bcm6358-leds device.
23 LED sub-node required properties:
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| D | leds-bcm6328.txt | 7 as spi-gpio. See Documentation/devicetree/bindings/gpio/gpio-74x164.txt), or
10 exporting the 74x164 as spi-gpio prevents those LEDs to be hardware
18 explained later in brcm,link-signal-sources). Even if a LED is hardware
24 - compatible : should be "brcm,bcm6328-leds".
25 - #address-cells : must be 1.
26 - #size-cells : must be 0.
27 - reg : BCM6328 LED controller address and size.
30 - brcm,serial-leds : Boolean, enables Serial LEDs.
32 - brcm,serial-mux : Boolean, enables Serial LEDs multiplexing.
34 - brcm,serial-clk-low : Boolean, makes clock signal active low.
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| /Documentation/devicetree/bindings/power/supply/ |
| D | max8903-charger.txt | 4 - compatible: "maxim,max8903" for MAX8903 Battery Charger
5 - dok-gpios: Valid DC power has been detected (active low, input), optional if uok-gpios is provided
6 - uok-gpios: Valid USB power has been detected (active low, input), optional if dok-gpios is provid…
9 - cen-gpios: Charge enable pin (active low, output)
10 - chg-gpios: Charger status pin (active low, input)
11 - flt-gpios: Fault pin (active low, output)
12 - dcm-gpios: Current limit mode setting (DC=1 or USB=0, output)
13 - usus-gpios: USB suspend pin (active high, output)
18 max8903-charger {
20 dok-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
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| D | lt3651-charger.txt | 1 Analog Devices LT3651 Charger Power Supply bindings: lt3651-charger
4 - compatible: Should contain one of the following:
5 * "lltc,ltc3651-charger", (DEPRECATED: Use "lltc,lt3651-charger")
6 * "lltc,lt3651-charger"
7 - lltc,acpr-gpios: Connect to ACPR output. See remark below.
10 - lltc,fault-gpios: Connect to FAULT output. See remark below.
11 - lltc,chrg-gpios: Connect to CHRG output. See remark below.
13 The lt3651 outputs are open-drain type and active low. The driver assumes the
14 GPIO reports "active" when the output is asserted, so if the pins have been
15 connected directly, the GPIO flags should be set to active low also.
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| /Documentation/driver-api/gpio/ |
| D | intro.rst | 16 - The descriptor-based interface is the preferred way to manipulate GPIOs,
17 and is described by all the files in this directory excepted gpio-legacy.txt.
18 - The legacy integer-based interface which is considered deprecated (but still
19 usable for compatibility reasons) is documented in gpio-legacy.txt.
21 The remainder of this document applies to the new descriptor-based interface.
22 gpio-legacy.txt contains the same information applied to the legacy
23 integer-based interface.
29 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
37 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
38 non-dedicated pin can be configured as a GPIO; and most chips have at least
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | st,st-mipid02.txt | 1 STMicroelectronics MIPID02 CSI-2 to PARALLEL bridge
3 MIPID02 has two CSI-2 input ports, only one of those ports can be active at a
4 time. Active port input stream will be de-serialized and its content outputted
6 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2 second
11 YUV420 8-bit, YUV422 8-bit and YUV420 10-bit.
14 - compatible: shall be "st,st-mipid02"
15 - clocks: reference to the xclk input clock.
16 - clock-names: shall be "xclk".
17 - VDDE-supply: sensor digital IO supply. Must be 1.8 volts.
18 - VDDIN-supply: sensor internal regulator supply. Must be 1.8 volts.
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| D | ov7670.txt | 8 - compatible: should be "ovti,ov7670"
9 - clocks: reference to the xclk input clock.
10 - clock-names: should be "xclk".
13 - hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
14 - vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH respectively.
17 - reset-gpios: reference to the GPIO connected to the resetb pin, if any.
18 Active is low.
19 - powerdown-gpios: reference to the GPIO connected to the pwdn pin, if any.
20 Active is high.
21 - ov7670,pclk-hb-disable: a boolean property to suppress pixel clock output
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| D | tvp7002.txt | 7 - compatible : Must be "ti,tvp7002"
10 - hsync-active: HSYNC Polarity configuration for the bus. Default value when
13 - vsync-active: VSYNC Polarity configuration for the bus. Default value when
16 - pclk-sample: Clock polarity of the bus. Default value when this property is
19 - sync-on-green-active: Active state of Sync-on-green signal property of the
21 0 = Normal Operation (Active Low, Default)
24 - field-even-active: Active-high Field ID output polarity control of the bus.
27 0 = Normal Operation (Active Low, Default)
31 video-interfaces.txt.
44 hsync-active = <1>;
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| D | aptina,mt9v111.txt | 2 ----------------------------
4 The Aptina MT9V111 is a 1/4-Inch VGA-format digital image sensor with a core
7 The sensor has an active pixel array of 640x480 pixels and can output a number
8 of image resolution and formats controllable through a simple two-wires
12 --------------------
14 - compatible: shall be "aptina,mt9v111".
15 - clocks: reference to the system clock input provider.
18 --------------------
20 - enable-gpios: output enable signal, pin name "OE#". Active low.
21 - standby-gpios: low power state control signal, pin name "STANDBY".
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| D | ov5640.txt | 1 * Omnivision OV5640 MIPI CSI-2 / parallel sensor
4 - compatible: should be "ovti,ov5640"
5 - clocks: reference to the xclk input clock.
6 - clock-names: should be "xclk".
7 - DOVDD-supply: Digital I/O voltage supply, 1.8 volts
8 - AVDD-supply: Analog voltage supply, 2.8 volts
9 - DVDD-supply: Digital core voltage supply, 1.5 volts
12 - reset-gpios: reference to the GPIO connected to the reset pin, if any.
13 This is an active low signal to the OV5640.
14 - powerdown-gpios: reference to the GPIO connected to the powerdown pin,
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| /Documentation/devicetree/bindings/power/reset/ |
| D | gpio-poweroff.txt | 9 When the power-off handler is called, the gpio is configured as an
10 output, and drive active, so triggering a level triggered power off
11 condition. This will also cause an inactive->active edge condition, so
13 the GPIO is set to inactive, thus causing an active->inactive edge,
15 delay the GPIO is driver active again. If the power is still on and
19 - compatible : should be "gpio-poweroff".
20 - gpios : The GPIO to set high/low, see "gpios property" in
22 low to power down the board set it to "Active Low", otherwise set
23 gpio to "Active High".
26 - input : Initially configure the GPIO line as an input. Only reconfigure
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| D | gpio-restart.txt | 6 handler. If the optional properties 'open-source' is not found, the GPIO line
11 priority order. The gpio is configured as an output, and driven active,
13 inactive->active edge condition, triggering positive edge triggered
14 reset. After a delay specified by active-delay, the GPIO is set to
15 inactive, thus causing an active->inactive edge, triggering negative edge
16 triggered reset. After a delay specified by inactive-delay, the GPIO
17 is driven active again. After a delay specified by wait-delay, the
21 - compatible : should be "gpio-restart".
22 - gpios : The GPIO to set high/low, see "gpios property" in
24 low to reset the board set it to "Active Low", otherwise set
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| /Documentation/devicetree/bindings/net/ |
| D | mdio-mux-gpio.txt | 8 - compatible : mdio-mux-gpio.
9 - gpios : GPIO specifiers for each GPIO line. One or more must be specified.
16 compatible = "cavium,octeon-3860-mdio";
17 #address-cells = <1>;
18 #size-cells = <0>;
23 An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
27 mdio-mux {
28 compatible = "mdio-mux-gpio";
30 mdio-parent-bus = <&smi1>;
31 #address-cells = <1>;
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| D | mdio-mux.txt | 8 - #address-cells = <1>;
9 - #size-cells = <0>;
12 - mdio-parent-bus : phandle to the parent MDIO bus.
14 - Other properties specific to the multiplexer/switch hardware.
17 - #address-cells = <1>;
18 - #size-cells = <0>;
19 - reg : The sub-bus number.
26 compatible = "cavium,octeon-3860-mdio";
27 #address-cells = <1>;
28 #size-cells = <0>;
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| D | sff,sfp.txt | 1 Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
6 - compatible : must be one of
10 - i2c-bus : phandle of an I2C bus controller for the SFP two wire serial
15 - mod-def0-gpios : GPIO phandle and a specifier of the MOD-DEF0 (AKA Mod_ABS)
16 module presence input gpio signal, active (module absent) high. Must
19 - los-gpios : GPIO phandle and a specifier of the Receiver Loss of Signal
20 Indication input gpio signal, active (signal lost) high
22 - tx-fault-gpios : GPIO phandle and a specifier of the Module Transmitter
23 Fault input gpio signal, active (fault condition) high
25 - tx-disable-gpios : GPIO phandle and a specifier of the Transmitter Disable
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| /Documentation/hwmon/ |
| D | ds620.rst | 20 -----------
23 high and low temperature limits which can be user defined (i.e. programmed
24 into non-volatile on-chip registers). Temperature range is -55 degree Celsius
30 PO is always low. If .pomode == 1, the thermostat is in PO_LOW mode. I.e., the
31 output pin PO becomes active when the temperature falls below temp1_min and
32 stays active until the temperature goes above temp1_max.
35 output pin becomes active when the temperature goes above temp1_max and stays
36 active until the temperature falls below temp1_min.
38 The PO output pin of the DS620 operates active-low.
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| /Documentation/devicetree/bindings/sound/ |
| D | tlv320adcx140.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Texas Instruments TLV320ADCX140 Quad Channel Analog-to-Digital Converter
11 - Dan Murphy <dmurphy@ti.com>
14 The TLV320ADCX140 are multichannel (4-ch analog recording or 8-ch digital
15 PDM microphones recording), high-performance audio, analog-to-digital
28 - const: ti,tlv320adc3140
29 - const: ti,tlv320adc5140
30 - const: ti,tlv320adc6140
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | atmel,aic.txt | 4 - compatible: Should be:
5 - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
7 - "microchip,<chip>-aic" where <chip> can be "sam9x60"
9 - interrupt-controller: Identifies the node as an interrupt controller.
10 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
14 1 = low-to-high edge triggered.
15 2 = high-to-low edge triggered.
16 4 = active high level-sensitive.
17 8 = active low level-sensitive.
19 Default flag for internal sources should be set to 4 (active high).
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| /Documentation/devicetree/bindings/media/ |
| D | pxa-camera.txt | 4 - compatible: Should be "marvell,pxa270-qci"
5 - reg: register base and size
6 - interrupts: the interrupt number
7 - any required generic properties defined in video-interfaces.txt
10 - clocks: input clock (see clock-bindings.txt)
11 - clock-output-names: should contain the name of the clock driving the
13 - clock-frequency: host interface is driving MCLK, and MCLK rate is this rate
18 compatible = "marvell,pxa270-qci";
23 clock-names = "ciclk";
24 clock-frequency = <50000000>;
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| D | allwinner,sun6i-a31-csi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/media/allwinner,sun6i-a31-csi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - allwinner,sun6i-a31-csi
17 - allwinner,sun8i-a83t-csi
18 - allwinner,sun8i-h3-csi
19 - allwinner,sun8i-v3s-csi
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| /Documentation/devicetree/bindings/gpio/ |
| D | brcm,brcmstb-gpio.txt | 3 The controller's registers are organized as sets of eight 32-bit
9 - compatible:
10 Must be "brcm,brcmstb-gpio"
12 - reg:
16 - #gpio-cells:
19 bit[0]: polarity (0 for active-high, 1 for active-low)
21 - gpio-controller:
24 - brcm,gpio-bank-widths:
30 - interrupts:
33 - interrupts-extended:
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| D | gpio-nmk.txt | 4 - compatible : Should be "st,nomadik-gpio".
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller.
7 - #gpio-cells : Should be two:
10 - bits[3:0] trigger type and level flags:
11 1 = low-to-high edge triggered.
12 2 = high-to-low edge triggered.
13 4 = active high level-sensitive.
14 8 = active low level-sensitive.
15 - gpio-controller : Marks the device node as a GPIO controller.
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| /Documentation/devicetree/bindings/reset/ |
| D | snps,dw-reset.txt | 9 - compatible: should be one of the following.
10 "snps,dw-high-reset" - for active high configuration
11 "snps,dw-low-reset" - for active low configuration
13 - reg: physical base address of the controller and length of memory mapped
16 - #reset-cells: must be 1.
20 dw_rst_1: reset-controller@0000 {
21 compatible = "snps,dw-high-reset";
23 #reset-cells = <1>;
26 dw_rst_2: reset-controller@1000 {i
27 compatible = "snps,dw-low-reset";
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| /Documentation/devicetree/bindings/leds/irled/ |
| D | spi-ir-led.txt | 8 - compatible: should be "ir-spi-led".
11 - duty-cycle: 8 bit value that represents the percentage of one period
12 in which the signal is active. It can be 50, 60, 70, 75, 80 or 90.
13 - led-active-low: boolean value that specifies whether the output is
15 - power-supply: specifies the power source. It can either be a regulator
16 or a gpio which enables a regulator, i.e. a regulator-fixed as
18 Documentation/devicetree/bindings/regulator/fixed-regulator.yaml
23 compatible = "ir-spi-led";
25 spi-max-frequency = <5000000>;
26 power-supply = <&vdd_led>;
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| /Documentation/devicetree/bindings/regulator/ |
| D | gpio-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/gpio-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
18 - $ref: "regulator.yaml#"
22 const: regulator-gpio
24 regulator-name: true
26 enable-gpios:
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