Searched full:ahb (Results 1 – 25 of 84) sorted by relevance
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| /Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra20-ahb.txt | 1 NVIDIA Tegra AHB
4 - compatible : For Tegra20, must contain "nvidia,tegra20-ahb". For
5 Tegra30, must contain "nvidia,tegra30-ahb". Otherwise, must contain
6 '"nvidia,<chip>-ahb", "nvidia,tegra30-ahb"' where <chip> is tegra124,
14 ahb: ahb@6000c004 {
15 compatible = "nvidia,tegra20-ahb";
16 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
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| /Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun5i-a13-ahb-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun5i-a13-ahb-clk.yaml#
7 title: Allwinner A13 AHB Clock Device Tree Bindings
20 const: allwinner,sun5i-a13-ahb-clk
44 ahb@1c20054 {
46 compatible = "allwinner,sun5i-a13-ahb-clk";
49 clock-output-names = "ahb";
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| D | nspire-clock.txt | 5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
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| D | allwinner,sun4i-a10-ahb-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml#
7 title: Allwinner A10 AHB Clock Device Tree Bindings
21 - allwinner,sun4i-a10-ahb-clk
51 const: allwinner,sun4i-a10-ahb-clk
82 ahb@1c20054 {
84 compatible = "allwinner,sun4i-a10-ahb-clk";
87 clock-output-names = "ahb";
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| D | allwinner,sun9i-a80-ahb-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-ahb-clk.yaml#
7 title: Allwinner A80 AHB Clock Device Tree Bindings
20 const: allwinner,sun9i-a80-ahb-clk
46 compatible = "allwinner,sun9i-a80-ahb-clk";
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| D | qca,ath79-pll.txt | 3 The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
20 - clock-output-names: should be "cpu", "ddr", "ahb"
32 clock-output-names = "cpu", "ddr", "ahb";
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| D | allwinner,sun4i-a10-gates-clk.yaml | 26 - const: allwinner,sun4i-a10-ahb-gates-clk
27 - const: allwinner,sun5i-a10s-ahb-gates-clk
28 - const: allwinner,sun5i-a13-ahb-gates-clk
29 - const: allwinner,sun7i-a20-ahb-gates-clk
100 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
102 clocks = <&ahb>;
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| /Documentation/devicetree/bindings/iommu/ |
| D | nvidia,tegra30-smmu.txt | 10 - nvidia,ahb : phandle to the ahb bus connected to SMMU.
20 nvidia,ahb = <&ahb>;
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| /Documentation/devicetree/bindings/misc/ |
| D | intel,ixp4xx-ahb-queue-manager.yaml | 5 $id: "http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml#"
8 title: Intel IXP4xx AHB Queue Manager
14 The IXP4xx AHB Queue Manager maintains queues as circular buffers in
26 - const: intel,ixp4xx-ahb-queue-manager
48 compatible = "intel,ixp4xx-ahb-queue-manager";
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| /Documentation/devicetree/bindings/dma/ |
| D | arm-pl08x.txt | 15 - lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
16 - lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
17 - mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
18 - mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
21 which AHB master that is used.
33 - dmas: List of DMA controller phandle, request channel and AHB master id
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| D | milbeaut-m10v-hdmac.txt | 1 * Milbeaut AHB DMA Controller
3 Milbeaut AHB DMA controller has transfer capability below.
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-ath79.txt | 6 - clocks: phandle of the AHB clock.
7 - clock-names: has to be "ahb".
20 clock-names = "ahb";
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| /Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie.txt | 86 - "iface" Configuration AHB clock
121 - "ahb" AHB clock
128 - "iface" AHB clock
156 - "ahb" AHB reset
181 - "ahb" AHB reset
182 - "phy_ahb" PHY AHB reset
194 - "ahb" AHB Reset
206 - "ahb" AHB reset
294 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
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| /Documentation/devicetree/bindings/watchdog/ |
| D | alphascale-asm9260.txt | 10 "ahb" - ahb gate.
29 clock-names = "mod", "ahb";
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| /Documentation/devicetree/bindings/media/ |
| D | coda.txt | 17 - clocks : Should contain the ahb and per clocks, in the order
19 - clock-names : Should be "ahb", "per"
29 clock-names = "ahb", "per";
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| D | rockchip,vdec.yaml | 29 - description: The Video Decoder AHB interface clock
36 - const: ahb
68 clock-names = "axi", "ahb", "cabac", "core";
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,geni-se.yaml | 32 - const: m-ahb
33 - const: s-ahb
37 - description: Master AHB Clock
38 - description: Slave AHB Clock
190 clock-names = "m-ahb", "s-ahb";
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| /Documentation/devicetree/bindings/rtc/ |
| D | alphascale,asm9260-rtc.txt | 10 * "ahb" for the SoC RTC clock
17 clock-names = "ahb";
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| /Documentation/devicetree/bindings/crypto/ |
| D | allwinner,sun4i-a10-crypto.yaml | 44 - const: ahb
51 const: ahb
82 clock-names = "ahb", "mod";
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| /Documentation/devicetree/bindings/phy/ |
| D | qcom,usb-ss.yaml | 29 - description: PHY AHB clock
35 - const: ahb
76 clock-names = "ref", "ahb", "pipe";
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| D | qcom,usb-hs-28nm.yaml | 29 - description: PHY AHB clock
35 - const: ahb
82 clock-names = "ref", "ahb", "sleep";
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| /Documentation/devicetree/bindings/ata/ |
| D | imx-sata.yaml | 33 - description: ahb clock
39 - const: ahb
82 clock-names = "sata", "sata_ref", "ahb";
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| /Documentation/devicetree/bindings/arm/stm32/ |
| D | st,mlahb.yaml | 7 title: STMicroelectronics STM32 ML-AHB interconnect bindings
14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
57 mlahb: ahb@38000000 {
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| /Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,aips-bus.yaml | 7 title: i.MX AHB to IP Bridge
14 AHB bus and peripherals with the lower bandwidth IP Slave (IPS)
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| /Documentation/devicetree/bindings/mmc/ |
| D | allwinner,sun4i-a10-mmc.yaml | 70 - const: ahb
79 const: ahb
96 clock-names = "ahb", "mmc";
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