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/Documentation/devicetree/bindings/pinctrl/
Daxis,artpec6-pinctrl.txt74 clocks = <&pll2div24>, <&apb_pclk>;
75 clock-names = "uart_clk", "apb_pclk";
83 clocks = <&pll2div24>, <&apb_pclk>;
84 clock-names = "uart_clk", "apb_pclk";
/Documentation/devicetree/bindings/watchdog/
Darm,sp805.yaml52 - const: apb_pclk
69 clocks = <&wdt_clk>, <&apb_pclk>;
70 clock-names = "wdog_clk", "apb_pclk";
/Documentation/devicetree/bindings/timer/
Darm,sp804.yaml57 clock, apb_pclk. A single clock can also be specified if the same
70 # requires the "apb_pclk" name, so we need this property.
71 # Use "timer0clk", "timer1clk", "apb_pclk" for new DTs.
96 clock-names = "timer1", "timer2", "apb_pclk";
/Documentation/devicetree/bindings/arm/
Dcoresight.txt62 providing the interconnect should be "apb_pclk", and some
162 clock-names = "apb_pclk";
177 clock-names = "apb_pclk";
192 clock-names = "apb_pclk";
253 clock-names = "apb_pclk";
288 clock-names = "apb_pclk";
333 clock-names = "apb_pclk";
349 clock-names = "apb_pclk";
367 clock-names = "apb_pclk";
384 clock-names = "apb_pclk";
Dsp810.txt16 should be: "refclk", "timclk", "apb_pclk"
40 clock-names = "refclk", "timclk", "apb_pclk";
Dcoresight-cpu-debug.txt24 the interconnect should be "apb_pclk" and the clock is
47 clock-names = "apb_pclk";
Dprimecell.yaml34 const: apb_pclk
Dcoresight-cti.yaml233 clock-names = "apb_pclk";
244 clock-names = "apb_pclk";
260 clock-names = "apb_pclk";
303 clock-names = "apb_pclk";
/Documentation/devicetree/bindings/crypto/
Drockchip-crypto.txt12 "apb_pclk" used to clock dma
25 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
/Documentation/devicetree/bindings/nvmem/
Drockchip-otp.txt9 - clock-names: Should be "otp", "apb_pclk" and "phy".
24 clock-names = "otp", "apb_pclk", "phy";
/Documentation/devicetree/bindings/memory-controllers/
Dpl353-smc.txt10 - clock-names : List of input clock names - "memclk", "apb_pclk"
26 clock-names = "memclk", "apb_pclk";
Darm,pl172.txt21 - clock-names: Must contain "mpmcclk" and "apb_pclk".
94 clock-names = "mpmcclk", "apb_pclk";
/Documentation/devicetree/bindings/serial/
Dsnps-dw-apb-uart.yaml58 - const: apb_pclk
137 clocks = <&baudclk>, <&apb_pclk>;
138 clock-names = "baudclk", "apb_pclk";
Dpl011.yaml70 - const: apb_pclk
121 clock-names = "uartclk", "apb_pclk";
/Documentation/devicetree/bindings/iio/adc/
Drockchip-saradc.yaml40 - const: apb_pclk
75 clock-names = "saradc", "apb_pclk";
/Documentation/devicetree/bindings/mailbox/
Darm,mhu.yaml71 - const: apb_pclk
103 clock-names = "apb_pclk";
127 clock-names = "apb_pclk";
/Documentation/devicetree/bindings/dma/
Darm-pl08x.txt14 - clock-names: Must contain "apb_pclk"
44 clock-names = "apb_pclk";
/Documentation/devicetree/bindings/spi/
Dspi-rockchip.yaml52 - const: apb_pclk
100 clock-names = "spiclk", "apb_pclk";
/Documentation/devicetree/bindings/thermal/
Drockchip-thermal.txt17 - clock-names : Shall be "tsadc" for the converter-clock, and "apb_pclk" for
42 clock-names = "tsadc", "apb_pclk";
/Documentation/devicetree/bindings/clock/
Dhix5hd2-clock.txt29 clock-names = "apb_pclk";
Dlsi,axm5516-clks.txt26 clock-names = "apb_pclk";
Dhi3670-clock.txt42 clock-names = "uartclk", "apb_pclk";
Dhi3660-clock.txt46 clock-names = "uartclk", "apb_pclk";
Drenesas,r9a06g032-sysctrl.txt44 clock-names = "baudclk", "apb_pclk";
/Documentation/devicetree/bindings/display/
Darm,pl11x.txt21 - clock-names: should contain "clcdclk" and "apb_pclk"
79 clock-names = "clcdclk", "apb_pclk";

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