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/Documentation/driver-api/md/ |
D | raid5-cache.rst | 7 caches data to the RAID disks. The cache can be in write-through (supported 8 since 4.4) or write-back mode (supported since 4.10). mdadm (supported since 9 3.4) has a new option '--write-journal' to create array with cache. Please 10 refer to mdadm manual for details. By default (RAID array starts), the cache is 11 in write-through mode. A user can switch it to write-back mode by:: 13 echo "write-back" > /sys/block/md0/md/journal_mode 15 And switch it back to write-through mode by:: 17 echo "write-through" > /sys/block/md0/md/journal_mode 19 In both modes, all writes to the array will hit cache disk first. This means 22 write-through mode [all …]
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/Documentation/scsi/ |
D | sd-parameters.rst | 1 .. SPDX-License-Identifier: GPL-2.0 8 --------------- 16 write back 1 0 on on 17 write back, no read (daft) 1 1 on off 20 To set cache type to "write back" and save this setting to the drive:: 22 # echo "write back" > cache_type 24 To modify the caching mode without making the change persistent, prepend 25 "temporary " to the cache type string. E.g.:: 27 # echo "temporary write back" > cache_type
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/Documentation/ABI/testing/ |
D | sysfs-class-bdi | 14 non-block filesystems which provide their own BDI, such as NFS 17 MAJOR:MINOR-fuseblk 23 The default backing dev, used for non-block device backed 28 read_ahead_kb (read-write) 30 Size of the read-ahead window in kilobytes 32 min_ratio (read-write) 35 total write-back cache that relates to its current average 36 writeout speed in relation to the other devices. 39 percentage of the write-back cache to a particular device. 42 max_ratio (read-write) [all …]
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D | sysfs-platform-hidma-mgmt | 1 What: /sys/devices/platform/hidma-mgmt*/chanops/chan*/priority 10 What: /sys/devices/platform/hidma-mgmt*/chanops/chan*/weight 19 What: /sys/devices/platform/hidma-mgmt*/chreset_timeout_cycles 25 Contains the platform specific cycle value to wait after a 31 What: /sys/devices/platform/hidma-mgmt*/dma_channels 38 of HIDMA hardware. The value may change from chip to chip. 40 What: /sys/devices/platform/hidma-mgmt*/hw_version_major 48 What: /sys/devices/platform/hidma-mgmt*/hw_version_minor 56 What: /sys/devices/platform/hidma-mgmt*/max_rd_xactions 63 read transactions that can be issued back to back. [all …]
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D | sysfs-bus-most | 8 might return <1-1.1:1.0> 25 directory is created that allows applications to read and 34 This is used to set an arbitrary DCI register address an 35 application wants to read from or write to. 43 This is used to read and write the DCI register whose address 52 This is used to check and configure the MAC address. 60 This is used to check and configure the MAC address. 68 This is used to check and configure the MAC address. 76 This is used to check and configure the MEP filter address. 84 This is used to check and configure the MEP hash table. [all …]
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/Documentation/admin-guide/ |
D | dell_rbu.rst | 15 It does not cover the support needed from applications to enable the BIOS to 16 update itself with the image downloaded in to the memory. 25 Please go to http://support.dell.com register and you can find info on 28 Libsmbios can also be used to update BIOS on Dell systems go to 34 using the driver breaks the image in to packets of fixed sizes and the driver 36 maintains a link list of packets for reading them back. 40 The rbu driver needs to have an application (as mentioned above) which will 41 inform the BIOS to enable the update in the next system reboot. 57 copied to a single contiguous block of physical memory. 63 changed to packets during the driver load time by specifying the load [all …]
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D | kernel-per-CPU-kthreads.rst | 2 Reducing OS jitter due to per-cpu kthreads 5 This document lists per-CPU kthreads in the Linux kernel and presents 6 options to control their OS jitter. Note that non-per-CPU kthreads are 7 not listed here. To reduce OS jitter from non-per-CPU kthreads, bind 8 them to a "housekeeping" CPU dedicated to such work. 13 - Documentation/core-api/irq/irq-affinity.rst: Binding interrupts to sets of CPUs. 15 - Documentation/admin-guide/cgroup-v1: Using cgroups to bind tasks to sets of CPUs. 17 - man taskset: Using the taskset command to bind tasks to sets 20 - man sched_setaffinity: Using the sched_setaffinity() system 21 call to bind tasks to sets of CPUs. [all …]
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/Documentation/devicetree/bindings/sound/ |
D | fsl,asrc.txt | 5 output clock. The driver currently works as a Front End of DPCM with other Back 6 Ends Audio controller such as ESAI, SSI and SAI. It has three pairs to support 11 - compatible : Compatible list, should contain one of the following 13 "fsl,imx35-asrc", 14 "fsl,imx53-asrc", 15 "fsl,imx8qm-asrc", 16 "fsl,imx8qxp-asrc", 18 - reg : Offset and length of the register set for the device. 20 - interrupts : Contains the spdif interrupt. 22 - dmas : Generic dma devicetree binding as described in [all …]
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/Documentation/devicetree/bindings/dma/ |
D | qcom_hidma_mgmt.txt | 14 instance can use like maximum read/write request and number of bytes to 18 - compatible: "qcom,hidma-mgmt-1.0"; 19 - reg: Address range for DMA device 20 - dma-channels: Number of channels supported by this DMA controller. 21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can 23 fragmented to multiples of this amount. This parameter is used while 26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can 28 fragmented to multiples of this amount. This parameter is used while 31 - max-write-transactions: This value is how many times a write burst is 32 applied back to back while writing to the destination before yielding [all …]
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/Documentation/devicetree/bindings/arm/msm/ |
D | qcom,idle-state.txt | 3 ARM provides idle-state node to define the cpuidle states, as defined in [1]. 4 cpuidle-qcom is the cpuidle driver for Qualcomm SoCs and uses these idle 6 The idle states supported by the QCOM SoC are defined as - 13 Standby: Standby does a little more in addition to architectural clock gating. 15 clocks. In addition to gating the clocks, QCOM cpus use this instruction as a 16 trigger to execute the SPM state machine. The SPM state machine waits for the 17 interrupt to trigger the core back in to active. This triggers the cache 18 hierarchy to enter standby states, when all cpus are idle. An interrupt brings 19 the SPM state machine out of its wait, the next step is to ensure that the 20 cache hierarchy is also out of standby, and then the cpu is allowed to resume [all …]
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/Documentation/sphinx/ |
D | parallel-wrapper.sh | 2 # SPDX-License-Identifier: GPL-2.0+ 5 # environment (as exported by scripts/jobserver-exec), or fall back to 6 # the "auto" parallelism when "-jN" is not specified at the top-level 13 if [ -z "$parallel" ] ; then 14 # If no parallelism is specified at the top-level make, then 15 # fall back to the expected "-jauto" mode that the "htmldocs" 17 auto=$(perl -e 'open IN,"'"$sphinx"' --version 2>&1 |"; 24 if [ -n "$auto" ] ; then 28 # Only if some parallelism has been determined do we add the -jN option. 29 if [ -n "$parallel" ] ; then [all …]
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/Documentation/block/ |
D | deadline-iosched.rst | 5 This little file attempts to document how the deadline io scheduler works. 7 of interest to power users. 10 ----------------------- 11 Refer to Documentation/block/switching-sched.rst for information on 12 selecting an io scheduler on a per-device basis. 14 ------------------------------------------------------------------------------ 17 ----------------------- 19 The goal of the deadline io scheduler is to attempt to guarantee a start 27 ----------------------- 29 Similar to read_expire mentioned above, but for writes. [all …]
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/Documentation/maintainer/ |
D | rebasing-and-merging.rst | 1 .. SPDX-License-Identifier: GPL-2.0 8 Git source-code management system. Git is a powerful tool with a lot of 10 ways to use those features. This document looks in particular at the use 15 One thing to be aware of in general is that, unlike many other projects, 19 maintainers result from a desire to avoid merges, while others come from 27 referred to as rebasing since both are done with the ``git rebase`` 30 - Changing the parent (starting) commit upon which a series of patches is 36 - Changing the history of a set of patches by fixing (or deleting) broken 37 commits, adding patches, adding tags to commit changelogs, or changing 39 type of operation will be referred to as "history modification" [all …]
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/Documentation/powerpc/ |
D | dawr-power9.rst | 6 if it points to cache inhibited (CI) memory. Currently Linux has no way to 26 PPC_PTRACE_GETHWDBGINFO call. This results in GDB falling back to 29 h_set_mode(DAWR) and h_set_dabr() will now return an error to the 35 migration from POWER8 to POWER9, at the cost of silently losing the 49 host. The watchpoint will fail and GDB will fall back to software 53 and configure the hardware to use the DAWR. This will run at full 55 guest is migrated to a POWER9 host, the watchpoint will be lost on the 56 POWER9. Loads and stores to the watchpoint locations will not be 58 migrated back to the POWER8 host, it will start working again. 62 Kernels (since ~v5.2) have an option to force enable the DAWR via:: [all …]
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D | transactional_memory.rst | 5 POWER kernel support for this feature is currently limited to supporting 8 This file aims to sum up how it is supported by Linux and what behaviour you 17 instructions are presented to delimit transactions; transactions are 18 guaranteed to either complete atomically or roll back and undo any partial 49 transactional or non-transactional accesses within the system. In this 50 example, the transaction completes as though it were normal straight-line code 52 atomic move of money from the current account to the savings account has been 59 state will roll back to that at the 'tbegin', and control will continue from 60 'tbegin+4'. The branch to abort_handler will be taken this second time; the 69 - Conflicts with cache lines used by other processors [all …]
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/Documentation/devicetree/bindings/iommu/ |
D | ti,omap-iommu.txt | 4 - compatible : Should be one of, 5 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances 6 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances 7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances 8 "ti,dra7-iommu" for DRA7xx IOMMU instances 9 - ti,hwmods : Name of the hwmod associated with the IOMMU instance 10 - reg : Address space for the configuration registers 11 - interrupts : Interrupt specifier for the IOMMU instance 12 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices, 14 also refer to the generic bindings document for more info [all …]
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/Documentation/vm/ |
D | zswap.rst | 11 in the process of being swapped out and attempts to compress them into a 12 dynamically allocated RAM-based memory pool. zswap basically trades CPU cycles 13 for potentially reduced swap I/O. This trade-off can also result in a 29 throttling by the hypervisor. This allows more work to get done with less 30 impact to the guest workload and guests sharing the I/O subsystem 32 drastically reducing life-shortening writes. 34 Zswap evicts pages from compressed cache on an LRU basis to the backing swap 43 An example command to enable zswap at runtime, assuming sysfs is mounted 50 back into memory all of the pages stored in the compressed pool. The 52 either invalidated or faulted back into memory. In order to force all [all …]
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/Documentation/admin-guide/device-mapper/ |
D | era.rst | 2 dm-era 8 dm-era is a target that behaves similar to the linear target. In 11 maintains the current era as a monotonically increasing 32-bit 15 partially invalidating the contents of a cache to restore cache 16 coherency after rolling back a vendor snapshot. 36 ---------- 38 Possibly move to a new era. You shouldn't assume the era has 43 ------------------ 45 Create a clone of the metadata, to allow a userland process to read it. 48 ------------------ [all …]
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D | writecache.rst | 6 doesn't cache reads because reads are supposed to be cached in page cache 14 1. type of the cache device - "p" or "s" 16 - p - persistent memory 17 - s - SSD 26 offset from the start of cache device in 512-byte sectors 46 applicable only to persistent memory - use the FUA flag 47 when writing data from persistent memory back to the 50 applicable only to persistent memory - don't use the FUA 51 flag when writing back data and send the FLUSH request 54 - some underlying devices perform better with fua, some [all …]
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/Documentation/x86/ |
D | mtrr.rst | 1 .. SPDX-License-Identifier: GPL-2.0 7 :Authors: - Richard Gooch <rgooch@atnf.csiro.au> - 3 Jun 1999 8 - Luis R. Rodriguez <mcgrof@do-not-panic.com> - April 9, 2015 16 arch_phys_wc_add() in combination with ioremap_wc() to make MTRR effective on 17 non-PAT systems while a no-op but equally effective on PAT enabled systems. 21 firmware may still have implemented access to MTRRs which would be controlled 24 the platform code would need uncachable access to some of its fan control 26 place other than mtrr_type_lookup() to ensure any OS specific mapping requests 31 For details refer to :doc:`pat`. 35 the Memory Type Range Registers (MTRRs) may be used to control [all …]
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/Documentation/device-mapper/ |
D | dm-bow.txt | 4 dm_bow is a device mapper driver that uses the free space on a device to back up 6 change, or rolled back by removing the dm_bow device and running a command line 9 dm_bow has three states, set by writing ‘1’ or ‘2’ to /sys/block/dm-?/bow/state. 10 It is only possible to go from state 0 (initial state) to state 1, and then from 11 state 1 to state 2. 13 State 0: dm_bow collects all trims to the device and assumes that these mark 16 FITRIM ioctl on the file system then switch to state 1. These trims are not 17 propagated to the underlying device. 19 State 1: All writes to the device cause the underlying data to be backed up to 23 that sector 0 is used to keep a log of the latest changes, both to indicate that [all …]
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/Documentation/core-api/ |
D | gfp_mask-from-fs-io.rst | 14 allocating memory to prevent recursion deadlocks caused by direct 15 memory reclaim calling back into the FS or IO paths and blocking on 16 already held resources (e.g. locks - most commonly those used for the 19 The traditional way to avoid this deadlock problem is to clear __GFP_FS 22 used as shortcut. It turned out though that above approach has led to 24 deeper consideration which leads to problems because an excessive use 25 of GFP_NOFS/GFP_NOIO can lead to memory over-reclaim or other memory 33 ``memalloc_noio_restore`` which allow to mark a scope to be a critical 36 mask so no memory allocation can recurse back in the FS/IO. 38 .. kernel-doc:: include/linux/sched/mm.h [all …]
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/Documentation/sound/hd-audio/ |
D | models.rst | 2 HD-Audio Codec-Specific Models 8 3-jack in back and a headphone out 9 3stack-digout 10 3-jack in back, a HP out and a SPDIF out 12 5-jack in back, 2-jack in front 13 5stack-digout 14 5-jack in back, 2-jack in front, a SPDIF out 16 6-jack in back, 2-jack in front 17 6stack-digout 18 6-jack with a SPDIF out [all …]
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/Documentation/devicetree/bindings/timer/ |
D | arm,arch_timer.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Marc Zyngier <marc.zyngier@arm.com> 11 - Mark Rutland <mark.rutland@arm.com> 13 ARM cores may have a per-core architected timer, which provides per-cpu timers, 14 or a memory mapped architected timer, which provides up to 8 frames with a 17 The per-core architected timer is attached to a GIC to deliver its 18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC 19 to deliver its interrupts via SPIs. [all …]
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/Documentation/admin-guide/pm/ |
D | strategies.rst | 1 .. SPDX-License-Identifier: GPL-2.0 13 The Linux kernel supports two major high-level power management strategies. 15 One of them is based on using global low-power states of the whole system in 17 significantly reduced, referred to as :doc:`sleep states <sleep-states>`. The 20 designated devices, triggering a transition to the ``working state`` in which 22 is affected by the state changes, this strategy is referred to as the 23 :doc:`system-wide power management <system-wide>`. 25 The other strategy, referred to as the :doc:`working-state power management 26 <working-state>`, is based on adjusting the power states of individual hardware 29 correspond to any particular physical configuration of it, but can be treated as [all …]
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